flashrom September 2013

flashrom@flashrom.org

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142 discussions

[commit] r1741 - trunk
by repository service 12 Sep '13

12 Sep '13

Author: stefanct Date: Thu Sep 12 17:48:35 2013 New Revision: 1741 URL: http://flashrom.org/trac/flashrom/changeset/1741 Log: sbxxx: Add detection for the remaining AMD chipset families. Also, correct prettyprinting of the registers of the various families, and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. Tested reading/writing on ASRock IMB-A180, and chipset detection on one of each affected generation by Chris Goodrich from Sage. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/sb600spi.c Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Thu Sep 12 16:04:31 2013 (r1740) +++ trunk/sb600spi.c Thu Sep 12 17:48:35 2013 (r1741) @@ -57,7 +57,28 @@ static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; - if (dev->device_id == 0x780e) { + msg_pdbg2("Trying to determine the generation of the SPI interface... "); + if (dev->device_id == 0x438d) { + amd_gen = CHIPSET_SB6XX; + msg_pdbg("SB6xx detected.\n"); + } else if (dev->device_id == 0x439d) { + struct pci_dev *smbus_dev = pci_dev_find(0x1002, 0x4385); + if (smbus_dev == NULL) + return; + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x39 && rev <= 0x3D) { + amd_gen = CHIPSET_SB7XX; + msg_pdbg("SB7xx/SP5100 detected.\n"); + } else if (rev >= 0x40 && rev <= 0x42) { + amd_gen = CHIPSET_SB89XX; + msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n"); + } else { + msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n" + "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom(a)flashrom.org\n", + rev); + amd_gen = CHIPSET_SB89XX; + } + } else if (dev->device_id == 0x780e) { /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) * although they use different SPI interfaces. */ #ifdef USE_YANGTZE_HEURISTICS @@ -94,7 +115,11 @@ "the output of lspci -nnvx, thanks!.\n", rev); } #endif - } + } else + msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!\n", + __func__, dev->vendor_id, dev->device_id); } static void reset_internal_fifo_pointer(void) @@ -250,7 +275,7 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ - if (dev->device_id == 0x438d) + if (amd_gen == CHIPSET_SB6XX) return 0; /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at @@ -336,6 +361,10 @@ sb600_spibar += tmp & 0xfff; determine_generation(dev); + if (amd_gen == CHIPSET_AMD_UNKNOWN) { + msg_perr("Could not determine chipset generation."); + return ERROR_NONFATAL; + } if (amd_gen == CHIPSET_YANGTZE) { msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" @@ -343,35 +372,89 @@ return ERROR_NONFATAL; } - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - /* FIXME: Set bit 3,6,7 if not already set. - * Set bit 5, otherwise SPI accesses are pointless in LPC mode. - * See doc 42413 AMD SB700/710/750 RPR. + /* How to read the following table and similar ones in this file: + * "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info. + * "<-" means the bit/register meaning is identical to the next non-"?" chipset to the left. "<-" thus + * never refers to another "?". + * If a "?" chipset is between two chipsets with identical meaning, we assume the meaning didn't change + * twice in between, i.e. the meaning is unchanged for the "?" chipset. Usually we assume that + * succeeding hardware supports the same functionality as its predecessor unless proven different by + * tests or documentation, hence "?" will often be implemented equally to "<-". + * + * Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 3 rsvd <- <- ? <- ? RouteTpm2Spi + * 2 rsvd AbortEnable rsvd ? <- ? <- + * 1 rsvd SpiRomEnable <- ? <- ? <- + * 0 rsvd AltSpiCSEnable rsvd ? <- ? <- */ - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - /* FIXME: If SpiAccessMacRomEn or SpiHostAccessRomEn are zero on - * SB700 or later, reads and writes will be corrupted. Abort in this - * case. Make sure to avoid this check on SB600. + if (amd_gen >= CHIPSET_SB7XX) { + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + + tmp = pci_read_byte(dev, 0xba); + msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); + + tmp = pci_read_byte(dev, 0xbb); + /* FIXME: Set bit 3,6,7 if not already set. + * Set bit 5, otherwise SPI accesses are pointless in LPC mode. + * See doc 42413 AMD SB700/710/750 RPR. + */ + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1); + msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1); + } + + /* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0) + * See the chipset support matrix for SPI Base_Addr above for an explanation of the symbols used. + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 17 rsvd <- <- ? <- ? <- + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0] + * 19 SpiArbEnable <- <- ? <- ? <- + * 20 (FifoPtrClr) <- <- ? <- ? <- + * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess + * 22 SpiAccessMacRomEn <- <- ? <- ? <- + * 23 SpiHostAccessRomEn <- <- ? <- ? <- + * 24:26 ArbWaitCount <- <- ? <- ? <- + * 27 SpiBridgeDisable <- <- ? <- ? rsvd + * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + * 31 rsvd <- SpiBusy ? <- ? <- */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + tmp = mmio_readl(sb600_spibar + 0x00); + msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + + msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", + (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); + + if (amd_gen != CHIPSET_YANGTZE) + msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1); + + switch (amd_gen) { + case CHIPSET_SB7XX: + msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); + case CHIPSET_SB89XX: + case CHIPSET_HUDSON234: + msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); + default: break; + } + msg_pdbg("\n"); + + if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { + msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); + return ERROR_NONFATAL; + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + if (amd_gen >= CHIPSET_SB89XX) { + tmp = mmio_readb(sb600_spibar + 0x1D); + msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) {

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[PATCH 2/2] sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.
by Stefan Tauner 12 Sep '13

12 Sep '13

Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 63 insertions(+), 8 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index febeabb..91268c0 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -272,6 +272,62 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, return 0; } +struct spispeed { + const char *const name; + const int8_t speed; +}; + +static const struct spispeed spispeeds[] = { + { "66 MHz", 0x00 }, + { "33 MHz", 0x01 }, + { "22 MHz", 0x02 }, + { "16.5 MHz", 0x03 }, +}; + +static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +{ + bool success = false; + uint8_t speed = spispeed->speed; + + msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); + if (amd_gen != CHIPSET_YANGTZE) { + rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); + success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + } + + if (!success) { + msg_perr("Setting SPI clock failed.\n"); + return 1; + } + return 0; +} + +static int handle_speed(struct pci_dev *dev) +{ + uint32_t tmp; + int8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + + /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used. + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + */ + if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { + bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); + if (fast_read) { + msg_pdbg("Disabling them temporarily.\n"); + rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), + sb600_spibar + 0x00); + } + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); + } + return set_speed(dev, &spispeeds[spispeed_idx]); +} + static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ @@ -322,9 +378,6 @@ int sb600_probe_spi(struct pci_dev *dev) uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" - }; char *arg = extract_programmer_param("amd_imc_force"); if (arg && !strcmp(arg, "yes")) { @@ -411,7 +464,7 @@ int sb600_probe_spi(struct pci_dev *dev) * See the chipset support matrix for SPI Base_Addr above for an explanation of the symbols used. * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze * 17 rsvd <- <- ? <- ? <- - * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0] + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0]<1> * 19 SpiArbEnable <- <- ? <- ? <- * 20 (FifoPtrClr) <- <- ? <- ? <- * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess @@ -420,8 +473,10 @@ int sb600_probe_spi(struct pci_dev *dev) * 24:26 ArbWaitCount <- <- ? <- ? <- * 27 SpiBridgeDisable <- <- ? <- ? rsvd * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- - * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]<1> * 31 rsvd <- SpiBusy ? <- ? <- + * + * <1> see handle_speed */ tmp = mmio_readl(sb600_spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); @@ -447,9 +502,6 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); - if (amd_gen >= CHIPSET_SB89XX) { tmp = mmio_readb(sb600_spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); @@ -494,6 +546,9 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; } + if (handle_speed(dev) != 0) + return ERROR_FATAL; + if (sb600_handle_imc(dev, amd_imc_force) != 0) return ERROR_FATAL; -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Makefile: Warn if user tries to compile for libpayload w/o crossgcc.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Thu, 29 Aug 2013 03:05:46 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > While flashrom is not as picky on compilers as coreboot, there is still a > high probablilty of breakage when one combines libpayload and distribution > compilers. Print a warning if we detect that to give the daring user a hint how > to resolve the explosions potentially following below it. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> r1740 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1740 - trunk
by repository service 12 Sep '13

12 Sep '13

Author: stefanct Date: Thu Sep 12 16:04:31 2013 New Revision: 1740 URL: http://flashrom.org/trac/flashrom/changeset/1740 Log: Makefile: Warn if user tries to compile for libpayload w/o crossgcc. While flashrom is not as picky on compilers as coreboot, there is still a high probablilty of breakage when one combines libpayload and distribution compilers. Print a warning if we detect that to give the daring user a hint how to resolve the explosions potentially following below it. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Sep 12 10:38:23 2013 (r1739) +++ trunk/Makefile Thu Sep 12 16:04:31 2013 (r1740) @@ -734,6 +734,11 @@ @echo $(TARGET_OS)|wc -w|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ ( echo "unknown. Aborting."; exit 1) @printf "%s\n" '$(TARGET_OS)' +ifeq ($(TARGET_OS), libpayload) + @$(CC) --version 2>&1 | grep -q coreboot || \ + ( echo "Warning: It seems you are not using coreboot's reference compiler."; \ + echo "This might work but usually does not, please beware." ) +endif define LIBPCI_TEST /* Avoid a failing test due to libpci header symbol shadowing breakage */

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Re: [flashrom] [PATCH] nicintel_eeprom: New programmer for Intel Nics eeproms
by Stefan Tauner 12 Sep '13

12 Sep '13

On Thu, 12 Sep 2013 11:25:39 +0200 Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> wrote: > ping? Hi Ricardo, I would have hoped for a more generic patch that adds some eeprom-specific infrastructure, but your approach seems to be legit when implementing this with the current infrastructure in flashrom. Sorry for not mentioning the opaque API before, that is of course the easiest way to get such things to work. Would it be even possible to probe for IDs of the EEPROMs with the interface on the Intel NICs? What EEPROM model(s) do see on your boards? I have not reviewed your patch in detail yet. There are probably a few coding style issues etc., but we can fix that ourselves if we have to. The bigger question is if we want to add something like it at all. I don't see good reason why we should not, but I need to discuss this with my colleague(s) (and that usually takes more time than one would expect). In any case your code is out there and can be used even if it does not get merged into vanilla flashrom eventually and your work is much appreciated, thank you. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Fix ROM decoding on VIA VT82C596 and VT82C686A/B.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Mon, 12 Aug 2013 22:19:50 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > These support an additional bit which we did not turn on yet. > Without this patch they decode up to 512 kB, with this up to 1 MB. > > Disentangle the enables of unrelated but mostly compatible chipsets > too, add some more debug output and set the max_rom_decode limits. > Also, make warnings really only warnings. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1739. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1739 - trunk
by repository service 12 Sep '13

12 Sep '13

Author: stefanct Date: Thu Sep 12 10:38:23 2013 New Revision: 1739 URL: http://flashrom.org/trac/flashrom/changeset/1739 Log: Fix ROM decoding on VIA VT82C596 and VT82C686A/B. These support an additional bit which we did not turn on yet. Without this patch they decode up to 512 kB, with this up to 1 MB. Disentangle the enables of unrelated but mostly compatible chipsets too, add some more debug output and set the max_rom_decode limits. Also, make warnings really only warnings. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Sep 12 10:29:06 2013 (r1738) +++ trunk/chipset_enable.c Thu Sep 12 10:38:23 2013 (r1739) @@ -884,22 +884,29 @@ return 0; } -/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ -static int enable_flash_amd8111(struct pci_dev *dev, const char *name) +/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B. + * + * ROM decode control register matrix + * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B + * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <- + * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <- + * 5 00E8... <- <- FFF00000h-FFF7FFFFh <- + */ +static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val) { #define AMD_MAPREG 0x43 #define AMD_ENREG 0x40 uint8_t old, new; - /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, AMD_MAPREG); - new = old | 0xC0; + new = old | decode_val; if (new != old) { rpci_write_byte(dev, AMD_MAPREG, new); if (pci_read_byte(dev, AMD_MAPREG) != new) { - msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", + msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", AMD_MAPREG, new, name); - } + } else + msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new); } /* Enable 'ROM write' bit. */ @@ -910,14 +917,37 @@ rpci_write_byte(dev, AMD_ENREG, new); if (pci_read_byte(dev, AMD_ENREG) != new) { - msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", + msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", AMD_ENREG, new, name); - return -1; + return ERROR_NONFATAL; } + msg_pdbg2("Set ROM enable bit successfully.\n"); return 0; } +static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name) +{ + /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ + max_rom_decode.lpc = 5 * 1024 * 1024; + return enable_flash_amd_via(dev, name, 0xC0); +} + +static int enable_flash_vt82c586(struct pci_dev *dev, const char *name) +{ + /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ + max_rom_decode.parallel = 512 * 1024; + return enable_flash_amd_via(dev, name, 0xC0); +} + +/* Works for VT82C686A/B too. */ +static int enable_flash_vt82c596(struct pci_dev *dev, const char *name) +{ + /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (1 MB) */ + max_rom_decode.parallel = 1024 * 1024; + return enable_flash_amd_via(dev, name, 0xE0); +} + static int enable_flash_sb600(struct pci_dev *dev, const char *name) { uint32_t prot; @@ -1304,8 +1334,8 @@ {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, - {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, - {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, + {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, + {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, @@ -1390,9 +1420,9 @@ {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, /* VIA southbridges */ - {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, - {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, - {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, + {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},

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Re: [flashrom] [PATCH] Enable sector erase function for selected ST M50 chips.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Tue, 27 Aug 2013 12:43:07 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Affected chips: M50FLW040A, M50FLW040B, M50FLW080A, M50FLW080B. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1738. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 2/2] Add support for ST M50LPW080.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Mon, 26 Aug 2013 22:40:15 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1737. The user did not reply in time. :( -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/2] Cleanup ST M50 driver.
by Stefan Tauner 12 Sep '13

12 Sep '13

On Mon, 26 Aug 2013 22:40:14 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > There are two locking strategies used by this umbrella family, one uniform > and one that matches the sector layout of the chip. Refactor the functions > involved and rename the overly complicated file to just stm50.c and the > functions accordingly. > > This fixes unlocking for some of the non-uniform chips, gets rid of the abuse > of page_size > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1736. The user did not reply in time. :( -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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