March 2013 - flashrom - mail.coreboot.org

Re: [flashrom] M29W512B write operation verified on 3C905C/TX
by Stefan Tauner March 14, 2013

March 14, 2013

On Tue, 5 Mar 2013 08:36:41 +0800 Lu Xie <lxie1(a)andrew.cmu.edu> wrote: > I am pretty sure my customized image was written into the rom. I flashed > the same image again after I saw the request of using "-v" parameter and > decided to pipe the output to a file. We have added an --output option to write output directly to a file BTW. > The adapter was shipped with MBA/PXE boot rom and I have flashed it with > plop boot manager. The manager is now fully functional so I can assure you > that something new has been written in the rom. Excellent, thank you. I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [coreboot] IMC on persimmon (was: Flashrom erase failure)
by Stefan Tauner March 14, 2013

March 14, 2013

On Mon, 4 Mar 2013 09:42:43 +0100 Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > Hi, > > recently I had the same problems to get Flashrom working on an embedded platform with AMD G-series processor similar to Persimmon. > I did all the patches to get Flashrom working but actually I'm not able to commit to flashrom.org. > If there is interest I would send the necessary files to someone who can do that for me. Hello Wolfgang, you can/should send any flashrom-related patches to flashrom(a)flashrom.org. They will then be tracked in our patchwork instance at http://patchwork.coreboot.org/project/flashrom/list/ and hopefully reviewed and merged eventually Please don't forget to add a signed-off. Details can be found at http://flashrom.org/Development_Guidelines Thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 2/4] Add granularity handling for AT45DB series.
by Carl-Daniel Hailfinger March 14, 2013

March 14, 2013

Am 03.03.2013 23:57 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flash.h | 2 ++ > flashrom.c | 38 +++++++++++++++++++++++--------------- > 2 files changed, 25 insertions(+), 15 deletions(-) > > diff --git a/flash.h b/flash.h > index 7dd9d9f..1df43c4 100644 > --- a/flash.h > +++ b/flash.h > @@ -66,11 +66,13 @@ enum chipbustype { > * - 128 bytes: If less than 128 bytes are written, the rest will be erased. Each write to a 128-byte region > * will trigger an automatic erase before anything is written. Very uncommon behaviour. > * - 256 bytes: If less than 256 bytes are written, the contents of the unwritten bytes are undefined. > + * - 264 bytes: FIXME Just copy the comment from 256 bytes. If that isn't completely correct, maybe this would fit: "If less than 264 bytes are written, the contents of all bytes of the write operation are undefined." AFAICS my text is inaccurate for Dataflash, though. > */ > enum write_granularity { > write_gran_256bytes = 0, /* We assume 256 byte granularity on default. */ > write_gran_1bit, > write_gran_1byte, > + write_gran_264bytes, Should we reverse the order of the values in that enum to have an ordering by size? > }; > > /* > diff --git a/flashrom.c b/flashrom.c > index 225b6f0..fc5e34a 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -676,6 +676,21 @@ out_free: > return ret; > } > > +static int need_erase_n_byte(uint8_t *have, uint8_t *want, unsigned int len, unsigned int n) Different name for the function maybe? Not sure, it doesn't sound too bad. > +{ > + unsigned int i, j, limit; > + for (j = 0; j < len / n; j++) { > + limit = min (n, len - j * n); > + /* Are 'have' and 'want' identical? */ > + if (!memcmp(have + j * n, want + j * n, limit)) > + continue; > + /* have needs to be in erased state. */ > + for (i = 0; i < limit; i++) > + if (have[j * n + i] != 0xff) > + return 1; > + } > + return 0; > +} > /* > * Check if the buffer @have can be programmed to the content of @want without > * erasing. This is only possible if all chunks of size @gran are either kept > @@ -693,7 +708,7 @@ out_free: > int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran) > { > int result = 0; > - unsigned int i, j, limit; > + unsigned int i; > > switch (gran) { > case write_gran_1bit: > @@ -711,20 +726,10 @@ int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granul > } > break; > case write_gran_256bytes: > - for (j = 0; j < len / 256; j++) { > - limit = min (256, len - j * 256); > - /* Are 'have' and 'want' identical? */ > - if (!memcmp(have + j * 256, want + j * 256, limit)) > - continue; > - /* have needs to be in erased state. */ > - for (i = 0; i < limit; i++) > - if (have[j * 256 + i] != 0xff) { > - result = 1; > - break; > - } > - if (result) > - break; > - } > + result = need_erase_n_byte(have, want, len, 256); > + break; > + case write_gran_264bytes: > + result = need_erase_n_byte(have, want, len, 264); The refactoring of that code is a really good idea. > break; > default: > msg_cerr("%s: Unsupported granularity! Please report a bug at " > @@ -772,6 +777,9 @@ static unsigned int get_next_write(uint8_t *have, uint8_t *want, unsigned int le > case write_gran_256bytes: > stride = 256; > break; > + case write_gran_264bytes: > + stride = 264; > + break; > default: > msg_cerr("%s: Unsupported granularity! Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); Overall, I like it. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Intel C602 support
by Stefan Tauner March 13, 2013

March 13, 2013

On Wed, 13 Mar 2013 13:15:32 +0000 Greg Schardt <gschardt(a)ddn.com> wrote: > I have modified the flashrom code to allow reads and writes to unprotected regions to occur, but am still blocked by having the ME region locked. Do you have any idea how the AFUDOS utility is able to modify the Management Engine region even though it should be locked? I would have thought that the Region Access Control settings would be in effect once the BIOS finished booting, before DOS could start. According to documentation, asserting HDA_SDO is the only way to override these settings, do you think that is the mechanism being used? AFAIK updating the ME directly is not possible if the locks are enabled (HDA_SDO is one way to disable them but that does not work after boot either). The ME probably is able to update itself and there is probably an interface for the host to transfer an image to it, but that's speculation. Are you sure afudos changes the ME region at all? AFAIK updating the ME (region) is not always needed. The problem is we do not know if this is true in all cases... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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testing DELL Dimension 4100
by Bertho Grandpied March 13, 2013

March 13, 2013

Testing Dell Dimension 4100 : Pentium III and Intel 815 (82815 + 82801BA, ICH2) based desktop machine from ca yr 2000. This chipset should be supported IIUC, but flash chip is not detected :( Flashrom was run under MS-DOS (log appended) - notice how I had to specify the "not-a-laptop" override because of insufficient DMI tables. Please notice also the "warning" about being unable to set Bios Control at 0x4e : thus the question arises, is that Intel chipset variant supported or is it not ? Additionally I ran 'Linux/sensors-detct' FWIW : "probing for Super-I/O at 0x2e/2f", "SMSC LPC47M10x/112/13x" fan sensors were found. Any further software probe I can try before opening up the box in the hope of finding what BIOS chip was used by visual inspection ? Regards... __________________________________________________________________ flashrom v0.9.6.1-r1624 on MS-DOS 7 (i686) flashrom was built with libpci 3.1.5, GCC 4.4.4, little endian Command line (7 args): c:/flashrom/flashrom.exe -p internal:laptop=this_is_not_a_laptop -V -r DELL.BIN -o READ.LOG Calibrating delay loop... OS timer resolution is 50000 usecs, 486M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 200000 myus = 270000 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Computer Corporation " DMI string system-product-name: "XPS-Z " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation " DMI string baseboard-product-name: "D815EEA " DMI string baseboard-version: "AAA10383-402 " DMI string chassis-type: "Unknown" DMI chassis-type is not specific enough. ======================================================================== WARNING! You may be running flashrom on an unsupported laptop.(....) You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "Intel ICH2" with PCI ID 8086:2440. Enabling flash write... BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled WARNING: Setting Bios Control at 0x4e from 0x02 to 0x03 on ICH2 failed. New value is 0x02. FAILED! The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xb2, id2 0xf1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:1f:0 reg 0x4e _________________________________________________________________ -- Czerno

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Re: [flashrom] Hello ! ERASE FAILED ASUS P5VD2-MX SE
by Idwer Vollering March 13, 2013

March 13, 2013

2013/3/13 Rémi charest <remicharest(a)gmail.com>: > Hello it seems my motherboard isn't really supported... Can you add > support for my board please ? Certainly.. run and attach the output of 'lspci -nnvvvxxx' (as root). Beware that writing, when a board enable is applied, trashes the LOM MAC address: http://www.flashrom.org/pipermail/flashrom/2012-March/009017.html > I'm wiLling to help if i can (linux noob here). > > Thanks ! > > I DID: flashrom -p internal -w P5V0701.ROM > ON : flashrom v0.9.6.1-r1564 on Linux 3.7.10-1-ARCH (i686) > > TERMINAL SAID: > Calibrating delay loop... OK. > Found chipset "VIA VT8237A". Enabling flash write... OK. > Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address > 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... ERASE FAILED at 0x00014000! Expected=0xff, > Read=0x17, failed byte count from 0x00014000-0x00014fff: 0xfe7 > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at 0x00010000! > Expected=0xff, Read=0x17, failed byte count from 0x00010000-0x0001ffff: > 0xfee5 > ERASE FAILED! > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Good. It seems nothing was changed. > Writing to the flash chip apparently didn't do anything. > This means we have to add special support for your board, programmer or > flash chip. > Please report this on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org! > > > MY MOTHERBOARD: > ASUS P5VD2-MX SE > version: Rev 1.xx > BIOS American Megatrends Inc. > version: 0602

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Re: [flashrom] Intel C602 support
by Stefan Tauner March 13, 2013

March 13, 2013

On Mon, 6 Aug 2012 12:07:47 -0700 Greg Schardt <gschardt(a)ddn.com> wrote: > Can you explain why doing a read operation failed? I expected that reads would work and writes would fail. each region can have 4 different access states: read/write, read-only, write-only (never seen in practice), locked (neither read nor write allowed) (see FREG in the public datasheets for any newer intel southbridge >ICH8). flashrom disables writes by default if it detects locked or read-only regions as a safety measurement and still allows reads because they can not lead to the same severe damage. in case of locked regions reads of addresses inside those regions will of course fail. there are some patches available that are not merged yet that allow to specify the addresses to be read/written, which allow to read/write the readable/writable address ranges. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Hello ! ERASE FAILED ASUS P5VD2-MX SE
by Rémi charest March 13, 2013

March 13, 2013

Hello it seems my motherboard isn't really supported... Can you add support for my board please ? I'm wiLling to help if i can (linux noob here). Thanks ! I DID: flashrom -p internal -w P5V0701.ROM ON : flashrom v0.9.6.1-r1564 on Linux 3.7.10-1-ARCH (i686) TERMINAL SAID: Calibrating delay loop... OK. Found chipset "VIA VT8237A". Enabling flash write... OK. *Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address 0xfff80000.* Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00014000! Expected=0xff, Read=0x17, failed byte count from 0x00014000-0x00014fff: 0xfe7 ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00010000! Expected=0xff, Read=0x17, failed byte count from 0x00010000-0x0001ffff: 0xfee5 ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! MY MOTHERBOARD: ASUS P5VD2-MX SE version: Rev 1.xx BIOS American Megatrends Inc. version: 0602 date: 05/08/2007 taille: 64KiB capacité: 448KiB Fonctionnalités: isa pci pnp apm upgrade shadowing escd cdboot bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification -- AVIS DE CONFIDENTIALITÉ: Ce courriel est destiné exclusivement au(x) destinataire(s) mentionné(s) ci-dessus et peut contenir de l'information privilégiée, confidentielle et/ou régie selon la loi de divulgation en vigueur. Si vous avez reçu ce message par erreur, ou s'il ne vous est pas destiné, veuillez le mentionner immédiatement à l'expéditeur et effacer ce courriel. Merci de votre coopération. CONFIDENTIALITY NOTICE: This e-mail message is intended only for the named recipient(s) above and may contain information that is privileged, confidential and/or exempt from disclosure under applicable law. If you have received this message in error, or are not the named recipient(s), please immediately notify the sender and delete this e-mail message. No virus found in this incoming message. Checked by Anti-Virus. -- No virus found in this outgoing message. Checked by Anti-Virus.

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Dell Precision T5600
by Clement Fevrier March 11, 2013

March 11, 2013

Hi, I'm running Ubuntu 12.04 and I was testing flashrom on my new workstation, a Dell Precision T5600 but it's not working. Here the log: $ sudo flashrom -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-38-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 3770M loops per second, 10 myus = 11 us, 100 myus = 105 us, 1000 myus = 1045 us, 10000 myus = 10111 us, 4 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Precision T5600" DMI string system-version: "01" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "0Y56T3" DMI string baseboard-version: "A01" DMI string chassis-type: "Tower" Found chipset "Intel X79" with PCI ID 8086:1d41. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa WARNING: Setting 0xdc from 0xa to 0xb on X79 failed. New value is 0xa. Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0bff0600 FREG1: BIOS region (0x00600000-0x00bfffff) is read-write. 0x5C: 0x05ff0006 FREG2: WARNING: Management Engine region (0x00006000-0x005fffff) is locked. 0x60: 0x00050002 FREG3: Gigabit Ethernet region (0x00002000-0x00005fff) is read-write. 0x64: 0x00010001 FREG4: Platform Data region (0x00001000-0x00001fff) is read-write. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84030 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=0, SME=0, SCF=0 0x94: 0x0606 (PREOP) 0x96: 0x743b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0420019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000800 (FPB) Enabling hardware sequencing due to multiple flash chips detected. SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 12288 kB. The flash address space (0x000000 - 0x3fffff) is divided at address 0x800000 in two partitions. The first partition ranges from 0x000000 to 0x7fffff. In that range are 2048 erase blocks with 4096 B each. The second partition ranges from 0x800000 to 0x3fffff. In that range are 1024 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xc9, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xc9, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xc9, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x00, id2 0x68, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xc9, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xc9, id2 0x05, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9e, id2 0x4a, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific). No operations were specified. Restoring MMIO space at 0x7fb8c9c668a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- Clement Fevrier Institut Neel, CNRS/UJF 38042 Grenoble, France email: clement.fevrier(a)grenoble.cnrs.fr tel: +33 4 76 88 12 38

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Report: MSI B75MA-E33 (MS-7808) V1.1 read
by dpcimanager＠users.sourceforge.net March 10, 2013

March 10, 2013

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r /var/folders/84/lxwdgbz177x9kf6b1sw_kt4h0000gn/T/DPCIMNCgIT.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 453M loops per second, 10 myus = 10 us, 100 myus = 103 us, 1000 myus = 978 us, 10000 myus = 9672 us, 4 myus = 3 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7808" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "B75MA-E33 (MS-7808)" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "Intel B75" with PCI ID 8086:1e49. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc6d: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x3b, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00a23551 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x0fff0a00 FREG1: BIOS region (0x00a00000-0x00ffffff) is read-write. 0x5C: 0x09ff0001 FREG2: Management Engine region (0x00001000-0x009fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xfc4010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=4 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05203b02 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x64900025 FLILL 0x00000000 --- Details --- Component 1 density: 16 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x0fff0a00 FLREG2 0x09ff0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00a00000 - 0x00ffffff Region 2 (ME ) 0x00001000 - 0x009fffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xca, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xca, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xca, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x2a, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x52, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xca, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x52, id2 0xf0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xca, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x04, id2 0x69, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific). Reading flash... Reading 16777216 bytes starting at 0x000000. done. Restoring MMIO space at 0x10b83d8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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