February 2013 - flashrom - mail.coreboot.org

80/100/132 column line width policy
by Carl-Daniel Hailfinger 15 Dec '18

15 Dec '18

Hi, we're hitting the 80 column limit in our code in ways which actually reduce readability for the code. Examples are various multiline messages and complicated nested code where refactoring to a separate function doesn't make sense. Keeping the old 80 column limit is not really an option anymore. Standard terminal sizes have one of 80, 100 or 132 columns. Given the monitor resolutions many people have nowadays, I think it is safe to say that you can fit two xterms with 100 columns horizonally next to each other. 100 columns should also be sufficient for a msg_p* of roughly 80 columns of text. 132 columns provide more leeway, but IMHO that would be too wide for good readability (and my screen can't fit two xterms side-by-side anymore). Of course some files have sections where any column limit is not acceptable (board lists etc.), but the column limit violations should be limited to the affected file sections, not whole files. Comments? I'd like to get this decided today or tomorrow so we know where we need line breaks in Stefan Tauner's new struct flashchip patch. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 9

External programmers
by Carl-Daniel Hailfinger 25 Dec '15

25 Dec '15

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Re: [flashrom] flashrom on PowerPC
by Stefan Tauner 20 Nov '15

20 Nov '15

On Wed, 27 Jul 2011 18:20:19 +0200 Mattias Mattsson <vitplister(a)gmail.com> wrote: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > i am resending this patch (unchanged) because patchwork did not pick it up correctly. please do send one patch per mail only in the future until we have something really working. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

FAILED: HM77 (Macbook Pro retina)
by Trammell Hudson 29 Dec '14

29 Dec '14

No changes were written to the executable portions of the ROM. The data regions at 0x2000-0x2FFF, 0x6400-0x67FF, 0xC000-0x14FFF, 0x1C000, 0x3C000, 0x40000-0x4BFFF were overwritten correctly. My firmware image differed only in those regions below 0x190000, so it might have successfully written to the entire 0x0-0x4BFFF (or even higher) space. The ROM image that I was writing had changes in the executable firmware volume starting at 0x190000. These were not written to the ROM. I have successfully rebooted and can reflash via external SPI if necessary for further tests. Output log from flashrom -V during the write process: flashrom v0.9.6.1-r1564 on Darwin 12.0.0 (x86_64) flashrom was built with libpci 3.1.7, GCC 4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2336.1.00), little endian Command line (8 args): ./flashrom -p internal -V -f -o /Volumes/NO NAME/write.log -w /Volumes/NO NAME/mbp101.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1597M loops per second, 10 myus = 9 us, 100 myus = 127 us, 1000 myus = 1003 us, 10000 myus = 9928 us, 4 myus = 4 us, OK. Initializing internal programmer Error accessing low megabyte, 0x100000 bytes at 0x00000000 Failed getting access to coreboot low tables. dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel HM77" with PCI ID 8086:1e57. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x9f, read w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x01, write w/o addr, none op[4]: 0x05, read w/o addr, none op[5]: 0x20, write w/ addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0xff, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x06 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0190 FREG1: BIOS region (0x00190000-0x007fffff) is read-write. 0x5C: 0x018f0001 FREG2: Management Engine region (0x00001000-0x0018ffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x866f0190 PR0: WARNING: 0x00190000-0x0066ffff is read-only. 0x78: 0x9fff0692 PR1: WARNING: 0x00692000-0x01ffffff is read-only. 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xfc4200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=4 0x94: 0x0606 (PREOP) 0x96: 0x3c6c (OPTYPE) 0x98: 0x0103029f (OPMENU) 0x9C: 0xffd82005 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x64900024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0190 FLREG2 0x018f0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00190000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x0018ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L6405" (8192 kB, SPI). Write/erase is not working yet on your programmer in its current configuration. Continuing anyway. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EERASE FAILED at 0x00001000! Expected=0xff, Read=0x20, failed byte count from 0x00000000-0x0000ffff: 0xada4 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:EW, 0x020000-0x02ffff:S, 0x030000-0x03ffff:EW, 0x040000-0x04ffff:EW, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:S, 0x110000-0x11ffff:S, 0x120000-0x12ffff:S, 0x130000-0x13ffff:S, 0x140000-0x14ffff:S, 0x150000-0x15ffff:S, 0x160000-0x16ffff:S, 0x170000-0x17ffff:S, 0x180000-0x18ffff:S, 0x190000-0x19ffff:ETransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=6, DBC=0, SME=0, SCF=4 Running OPCODE 0xd8 failed at address 0x190000 (payload length was 0). spi_block_erase_d8 failed during command execution at address 0x190000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0x104cb28a0 Restoring PCI config space for 00:1f:0 reg 0xdc

3 3

[PATCH] Add en29lv640b
by Rudolf Marek 11 Aug '14

11 Aug '14

Hi Following patch adds the en29lv640b which needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on bifferboard. Please check the patch and let me know. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks Rudolf

4 6

[PATCH] Rename programmer registration functions
by Carl-Daniel Hailfinger 20 Jul '14

20 Jul '14

register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rename_register_programmer_register_master/ogp_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ogp_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ogp_spi.c (Arbeitskopie) @@ -140,7 +140,7 @@ if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_ogp)) + if (register_spi_bitbang_master(&bitbang_spi_master_ogp)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/flash.h =================================================================== --- flashrom-rename_register_programmer_register_master/flash.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flash.h (Arbeitskopie) @@ -154,7 +154,7 @@ chipaddr virtual_memory; /* Some flash devices have an additional register space. */ chipaddr virtual_registers; - struct registered_programmer *pgm; + struct registered_master *pgm; }; #define TEST_UNTESTED 0 @@ -215,7 +215,7 @@ void map_flash_registers(struct flashctx *flash); int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashctx *flash); -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *fill_flash, int force); +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *fill_flash, int force); int read_flash_to_file(struct flashctx *flash, const char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-rename_register_programmer_register_master/drkaiser.c =================================================================== --- flashrom-rename_register_programmer_register_master/drkaiser.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/drkaiser.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_drkaiser = { +static const struct par_master par_programmer_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -85,7 +85,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + register_par_master(&par_programmer_drkaiser, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/it87spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it87spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it87spi.c (Arbeitskopie) @@ -113,7 +113,7 @@ static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_it87xx = { +static const struct spi_master spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -199,7 +199,7 @@ if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ - register_spi_programmer(&spi_programmer_it87xx); + register_spi_master(&spi_programmer_it87xx); return 0; } Index: flashrom-rename_register_programmer_register_master/gfxnvidia.c =================================================================== --- flashrom-rename_register_programmer_register_master/gfxnvidia.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/gfxnvidia.c (Arbeitskopie) @@ -66,7 +66,7 @@ chipaddr addr); static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_gfxnvidia = { +static const struct par_master par_programmer_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -112,7 +112,7 @@ /* Write/erase doesn't work. */ programmer_may_write = 0; - register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); + register_par_master(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nicrealtek.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicrealtek.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicrealtek.c (Arbeitskopie) @@ -40,7 +40,7 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicrealtek = { +static const struct par_master par_programmer_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -82,7 +82,7 @@ if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + register_par_master(&par_programmer_nicrealtek, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/serprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/serprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/serprog.c (Arbeitskopie) @@ -320,7 +320,7 @@ unsigned char *readarr); static int serprog_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static struct spi_programmer spi_programmer_serprog = { +static struct spi_master spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -337,7 +337,7 @@ const chipaddr addr); static void serprog_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_serprog = { +static const struct par_master par_programmer_serprog = { .chip_readb = serprog_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -673,10 +673,9 @@ sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; if (serprog_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_serprog); + register_spi_master(&spi_programmer_serprog); if (serprog_buses_supported & BUS_NONSPI) - register_par_programmer(&par_programmer_serprog, - serprog_buses_supported & BUS_NONSPI); + register_par_master(&par_programmer_serprog, serprog_buses_supported & BUS_NONSPI); return 0; } Index: flashrom-rename_register_programmer_register_master/bitbang_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/bitbang_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/bitbang_spi.c (Arbeitskopie) @@ -63,7 +63,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_bitbang = { +static const struct spi_master spi_programmer_bitbang = { .type = SPI_CONTROLLER_BITBANG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -82,9 +82,9 @@ } #endif -int bitbang_spi_init(const struct bitbang_spi_master *master) +int register_spi_bitbang_master(const struct bitbang_spi_master *master) { - struct spi_programmer pgm = spi_programmer_bitbang; + struct spi_master pgm = spi_programmer_bitbang; /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, * we catch it here. Same goes for missing initialization of bitbanging * functions. @@ -99,7 +99,7 @@ } pgm.data = master; - register_spi_programmer(&pgm); + register_spi_master(&pgm); /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); Index: flashrom-rename_register_programmer_register_master/satamv.c =================================================================== --- flashrom-rename_register_programmer_register_master/satamv.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satamv.c (Arbeitskopie) @@ -46,7 +46,7 @@ chipaddr addr); static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satamv = { +static const struct par_master par_programmer_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -156,7 +156,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; - register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); + register_par_master(&par_programmer_satamv, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/dummyflasher.c =================================================================== --- flashrom-rename_register_programmer_register_master/dummyflasher.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dummyflasher.c (Arbeitskopie) @@ -119,7 +119,7 @@ static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_programmer spi_programmer_dummyflasher = { +static const struct spi_master spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -130,7 +130,7 @@ .write_aai = default_spi_write_aai, }; -static const struct par_programmer par_programmer_dummy = { +static const struct par_master par_programmer_dummy = { .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, @@ -401,12 +401,10 @@ return 1; } if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) - register_par_programmer(&par_programmer_dummy, - dummy_buses_supported & - (BUS_PARALLEL | BUS_LPC | - BUS_FWH)); + register_par_master(&par_programmer_dummy, + dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); if (dummy_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_dummyflasher); + register_spi_master(&spi_programmer_dummyflasher); return 0; } Index: flashrom-rename_register_programmer_register_master/cli_classic.c =================================================================== --- flashrom-rename_register_programmer_register_master/cli_classic.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/cli_classic.c (Arbeitskopie) @@ -421,10 +421,10 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_programmer_count; j++) { + for (j = 0; j < registered_master_count; j++) { startchip = 0; while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_programmers[j], startchip, &flashes[chipcount], 0); + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); if (startchip == -1) break; chipcount++; @@ -446,12 +446,12 @@ "automatically.\n"); } if (force && read_it && chip_to_probe) { - struct registered_programmer *pgm; + struct registered_master *pgm; int compatible_programmers = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); /* This loop just counts compatible controllers. */ - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; /* chip is still set from the chip_to_probe earlier in this function. */ if (pgm->buses_supported & chip->bustype) compatible_programmers++; @@ -464,8 +464,8 @@ if (compatible_programmers > 1) msg_cinfo("More than one compatible controller found for the requested flash " "chip, using the first one.\n"); - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; startchip = probe_flash(pgm, 0, &flashes[0], 1); if (startchip != -1) break; Index: flashrom-rename_register_programmer_register_master/internal.c =================================================================== --- flashrom-rename_register_programmer_register_master/internal.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/internal.c (Arbeitskopie) @@ -145,7 +145,7 @@ const chipaddr addr); static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_internal = { +static const struct par_master par_programmer_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, @@ -348,7 +348,7 @@ * The error code might have been a warning only. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) - register_par_programmer(&par_programmer_internal, internal_buses_supported); + register_par_master(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-rename_register_programmer_register_master/ichspi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ichspi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ichspi.c (Arbeitskopie) @@ -1514,7 +1514,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_programmer spi_programmer_ich7 = { +static const struct spi_master spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, .max_data_write = 64, @@ -1525,7 +1525,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_programmer spi_programmer_ich9 = { +static const struct spi_master spi_programmer_ich9 = { .type = SPI_CONTROLLER_ICH9, .max_data_read = 64, .max_data_write = 64, @@ -1536,7 +1536,7 @@ .write_aai = default_spi_write_aai, }; -static const struct opaque_programmer opaque_programmer_ich_hwseq = { +static const struct opaque_master opaque_programmer_ich_hwseq = { .max_data_read = 64, .max_data_write = 64, .probe = ich_hwseq_probe, @@ -1623,7 +1623,7 @@ } ich_init_opcodes(); ich_set_bbar(0); - register_spi_programmer(&spi_programmer_ich7); + register_spi_master(&spi_programmer_ich7); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1808,9 +1808,9 @@ } hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); - register_opaque_programmer(&opaque_programmer_ich_hwseq); + register_opaque_master(&opaque_programmer_ich_hwseq); } else { - register_spi_programmer(&spi_programmer_ich9); + register_spi_master(&spi_programmer_ich9); } break; } @@ -1833,7 +1833,7 @@ return 0; } -static const struct spi_programmer spi_programmer_via = { +static const struct spi_master spi_programmer_via = { .type = SPI_CONTROLLER_VIA, .max_data_read = 16, .max_data_write = 16, @@ -1854,7 +1854,7 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; - register_spi_programmer(&spi_programmer_via); + register_spi_master(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Index: flashrom-rename_register_programmer_register_master/nicintel_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel_spi.c (Arbeitskopie) @@ -196,7 +196,7 @@ if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_nicintel)) + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/opaque.c =================================================================== --- flashrom-rename_register_programmer_register_master/opaque.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/opaque.c (Arbeitskopie) @@ -50,9 +50,9 @@ return flash->pgm->opaque.erase(flash, blockaddr, blocklen); } -int register_opaque_programmer(const struct opaque_programmer *pgm) +int register_opaque_master(const struct opaque_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { msg_perr("%s called with incomplete programmer definition. " Index: flashrom-rename_register_programmer_register_master/nicnatsemi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicnatsemi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicnatsemi.c (Arbeitskopie) @@ -41,7 +41,7 @@ chipaddr addr); static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicnatsemi = { +static const struct par_master par_programmer_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -75,7 +75,7 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; - register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); + register_par_master(&par_programmer_nicnatsemi, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/dediprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/dediprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dediprog.c (Arbeitskopie) @@ -736,7 +736,7 @@ return millivolt; } -static const struct spi_programmer spi_programmer_dediprog = { +static const struct spi_master spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -854,7 +854,7 @@ return 1; } - register_spi_programmer(&spi_programmer_dediprog); + register_spi_master(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Index: flashrom-rename_register_programmer_register_master/rayer_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/rayer_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/rayer_spi.c (Arbeitskopie) @@ -175,7 +175,7 @@ /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); - if (bitbang_spi_init(&bitbang_spi_master_rayer)) + if (register_spi_bitbang_master(&bitbang_spi_master_rayer)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/it85spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it85spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it85spi.c (Arbeitskopie) @@ -276,7 +276,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_it85xx = { +static const struct spi_master spi_programmer_it85xx = { .type = SPI_CONTROLLER_IT85XX, .max_data_read = 64, .max_data_write = 64, @@ -312,7 +312,7 @@ * a debug message about it. */ /* Set this as SPI controller. */ - register_spi_programmer(&spi_programmer_it85xx); + register_spi_master(&spi_programmer_it85xx); } return ret; } Index: flashrom-rename_register_programmer_register_master/buspirate_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/buspirate_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/buspirate_spi.c (Arbeitskopie) @@ -132,7 +132,7 @@ static int buspirate_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_buspirate = { +static const struct spi_master spi_programmer_buspirate = { .type = SPI_CONTROLLER_BUSPIRATE, .max_data_read = 12, .max_data_write = 12, @@ -407,7 +407,7 @@ return 1; } - register_spi_programmer(&spi_programmer_buspirate); + register_spi_master(&spi_programmer_buspirate); return 0; } Index: flashrom-rename_register_programmer_register_master/linux_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/linux_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/linux_spi.c (Arbeitskopie) @@ -46,7 +46,7 @@ static int linux_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_linux = { +static const struct spi_master spi_programmer_linux = { .type = SPI_CONTROLLER_LINUX, .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ @@ -115,7 +115,7 @@ return 1; } - register_spi_programmer(&spi_programmer_linux); + register_spi_master(&spi_programmer_linux); return 0; } Index: flashrom-rename_register_programmer_register_master/atahpt.c =================================================================== --- flashrom-rename_register_programmer_register_master/atahpt.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/atahpt.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t atahpt_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_atahpt = { +static const struct par_master par_programmer_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -80,7 +80,7 @@ if (register_shutdown(atahpt_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + register_par_master(&par_programmer_atahpt, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nic3com.c =================================================================== --- flashrom-rename_register_programmer_register_master/nic3com.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nic3com.c (Arbeitskopie) @@ -60,7 +60,7 @@ chipaddr addr); static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nic3com = { +static const struct par_master par_programmer_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -116,7 +116,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); + register_par_master(&par_programmer_nic3com, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/spi.c (Arbeitskopie) @@ -167,9 +167,9 @@ return flash->pgm->spi.write_aai(flash, buf, start, len); } -int register_spi_programmer(const struct spi_programmer *pgm) +int register_spi_master(const struct spi_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->write_aai || !pgm->write_256 || !pgm->read || !pgm->command || !pgm->multicommand || Index: flashrom-rename_register_programmer_register_master/ft2232_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ft2232_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ft2232_spi.c (Arbeitskopie) @@ -142,7 +142,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_ft2232 = { +static const struct spi_master spi_programmer_ft2232 = { .type = SPI_CONTROLLER_FT2232, .max_data_read = 64 * 1024, .max_data_write = 256, @@ -356,7 +356,7 @@ // msg_pdbg("\nft2232 chosen\n"); - register_spi_programmer(&spi_programmer_ft2232); + register_spi_master(&spi_programmer_ft2232); return 0; Index: flashrom-rename_register_programmer_register_master/satasii.c =================================================================== --- flashrom-rename_register_programmer_register_master/satasii.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satasii.c (Arbeitskopie) @@ -43,7 +43,7 @@ static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satasii = { +static const struct par_master par_programmer_satasii = { .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -90,7 +90,7 @@ if (register_shutdown(satasii_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + register_par_master(&par_programmer_satasii, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/wbsio_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/wbsio_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/wbsio_spi.c (Arbeitskopie) @@ -68,7 +68,7 @@ static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_wbsio = { +static const struct spi_master spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -90,7 +90,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; - register_spi_programmer(&spi_programmer_wbsio); + register_spi_master(&spi_programmer_wbsio); return 0; } Index: flashrom-rename_register_programmer_register_master/pony_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/pony_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/pony_spi.c (Arbeitskopie) @@ -158,7 +158,7 @@ return 1; } - if (bitbang_spi_init(&bitbang_spi_master_pony)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony)) { return 1; } return 0; Index: flashrom-rename_register_programmer_register_master/nicintel.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel.c (Arbeitskopie) @@ -48,7 +48,7 @@ chipaddr addr); static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicintel = { +static const struct par_master par_programmer_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -110,7 +110,7 @@ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; - register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); + register_par_master(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/sb600spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/sb600spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/sb600spi.c (Arbeitskopie) @@ -194,7 +194,7 @@ return 0; } -static const struct spi_programmer spi_programmer_sb600 = { +static const struct spi_master spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = 8, .max_data_write = 5, @@ -320,7 +320,7 @@ /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - register_spi_programmer(&spi_programmer_sb600); + register_spi_master(&spi_programmer_sb600); return 0; } Index: flashrom-rename_register_programmer_register_master/mcp6x_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Arbeitskopie) @@ -161,7 +161,7 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (bitbang_spi_init(&bitbang_spi_master_mcp6x)) { + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; Index: flashrom-rename_register_programmer_register_master/programmer.c =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.c (Arbeitskopie) @@ -96,10 +96,10 @@ return; } -int register_par_programmer(const struct par_programmer *pgm, +int register_par_master(const struct par_master *pgm, const enum chipbustype buses) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->chip_writeb || !pgm->chip_writew || !pgm->chip_writel || !pgm->chip_writen || !pgm->chip_readb || !pgm->chip_readw || !pgm->chip_readl || !pgm->chip_readn) { @@ -115,20 +115,20 @@ } /* The limit of 4 is totally arbitrary. */ -#define PROGRAMMERS_MAX 4 -struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; -int registered_programmer_count = 0; +#define MASTERS_MAX 4 +struct registered_master registered_masters[MASTERS_MAX]; +int registered_master_count = 0; -/* This function copies the struct registered_programmer parameter. */ -int register_programmer(struct registered_programmer *pgm) +/* This function copies the struct registered_master parameter. */ +int register_programmer(struct registered_master *pgm) { - if (registered_programmer_count >= PROGRAMMERS_MAX) { + if (registered_master_count >= MASTERS_MAX) { msg_perr("Tried to register more than %i programmer " - "interfaces.\n", PROGRAMMERS_MAX); + "interfaces.\n", MASTERS_MAX); return ERROR_FLASHROM_LIMIT; } - registered_programmers[registered_programmer_count] = *pgm; - registered_programmer_count++; + registered_masters[registered_master_count] = *pgm; + registered_master_count++; return 0; } @@ -138,8 +138,8 @@ int i; enum chipbustype ret = BUS_NONE; - for (i = 0; i < registered_programmer_count; i++) - ret |= registered_programmers[i].buses_supported; + for (i = 0; i < registered_master_count; i++) + ret |= registered_masters[i].buses_supported; return ret; } Index: flashrom-rename_register_programmer_register_master/flashrom.c =================================================================== --- flashrom-rename_register_programmer_register_master/flashrom.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flashrom.c (Arbeitskopie) @@ -949,7 +949,7 @@ return 1; } -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *flash, int force) +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *flash, int force) { const struct flashchip *chip; unsigned long base = 0; Index: flashrom-rename_register_programmer_register_master/programmer.h =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.h (Arbeitskopie) @@ -445,7 +445,7 @@ #endif /* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master); +int register_spi_bitbang_master(const struct bitbang_spi_master *master); /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 @@ -517,7 +517,7 @@ #define MAX_DATA_UNSPECIFIED 0 #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 -struct spi_programmer { +struct spi_master { enum spi_controller type; unsigned int max_data_read; unsigned int max_data_write; @@ -538,7 +538,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -int register_spi_programmer(const struct spi_programmer *programmer); +int register_spi_master(const struct spi_master *programmer); /* The following enum is needed by ich_descriptor_tool and ich* code. */ enum ich_chipset { @@ -580,7 +580,7 @@ #endif /* opaque.c */ -struct opaque_programmer { +struct opaque_master { int max_data_read; int max_data_write; /* Specific functions for this programmer */ @@ -590,7 +590,7 @@ int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); const void *data; }; -int register_opaque_programmer(const struct opaque_programmer *pgm); +int register_opaque_master(const struct opaque_master *pgm); /* programmer.c */ int noop_shutdown(void); @@ -603,7 +603,7 @@ uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr); uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr); void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { +struct par_master { void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr); void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr); void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr); @@ -614,18 +614,18 @@ void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); const void *data; }; -int register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); -struct registered_programmer { +int register_par_master(const struct par_master *pgm, const enum chipbustype buses); +struct registered_master { enum chipbustype buses_supported; union { - struct par_programmer par; - struct spi_programmer spi; - struct opaque_programmer opaque; + struct par_master par; + struct spi_master spi; + struct opaque_master opaque; }; }; -extern struct registered_programmer registered_programmers[]; -extern int registered_programmer_count; -int register_programmer(struct registered_programmer *pgm); +extern struct registered_master registered_masters[]; +extern int registered_master_count; +int register_programmer(struct registered_master *pgm); /* serprog.c */ #if CONFIG_SERPROG == 1 -- http://www.hailfinger.org/

3 4

[PATCH] Add IT8212F as programmer
by Kyösti Mälkki 02 Jun '14

02 Jun '14

This PCI PATA controller can use 3V parallel flash upto 128kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Index: flashrom-it8212f/Makefile =================================================================== --- flashrom-it8212f/Makefile (revision 1539) +++ flashrom-it8212f/Makefile (working copy) @@ -177,7 +177,12 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_IT8212), yes) +UNSUPPORTED_FEATURES += CONFIG_IT8212=yes +else +override CONFIG_IT8212 = no endif +endif ifeq ($(TARGET_OS), libpayload) CPPFLAGS += -DSTANDALONE @@ -344,6 +349,9 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +# Always enable ITE IT8212F PATA controllers for now. +CONFIG_IT8212 ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -503,6 +511,12 @@ PROGRAMMER_OBJS += linux_spi.o endif +ifeq ($(CONFIG_IT8212), yes) +FEATURE_CFLAGS += -D'CONFIG_IT8212=1' +PROGRAMMER_OBJS += it8212.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-it8212f/print_wiki.c =================================================================== --- flashrom-it8212f/print_wiki.c (revision 1539) +++ flashrom-it8212f/print_wiki.c (working copy) @@ -338,6 +338,9 @@ #if CONFIG_SATAMV == 1 print_supported_pcidevs_wiki(satas_mv); #endif +#if CONFIG_IT8212 == 1 + print_supported_pcidevs_wiki(ata_it82); +#endif printf("\n|}\n"); } Index: flashrom-it8212f/it8212.c =================================================================== --- flashrom-it8212f/it8212.c (revision 0) +++ flashrom-it8212f/it8212.c (revision 0) @@ -0,0 +1,110 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +static uint8_t *it8212_bar; +static uint8_t it8212_rom_enable = 0; + +#define PCI_VENDOR_ID_ITE 0x1283 + +const struct pcidev_status ata_it82[] = { + {PCI_VENDOR_ID_ITE, 0x8212, OK, "ITE", "8212F PATA RAID"}, + {}, +}; + +#define IT8212_MEMMAP_SIZE (128 * 1024) +#define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1) + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, + chipaddr addr); +static uint8_t it8212_chip_readb(const struct flashctx *flash, + const chipaddr addr); +static const struct par_programmer par_programmer_it8212 = { + .chip_readb = it8212_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = it8212_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +static int it8212_shutdown(void *data) +{ + if (! it8212_rom_enable) { + uintptr_t addr = pci_read_long(pcidev_dev, PCI_ROM_ADDRESS); + pci_write_long(pcidev_dev, PCI_ROM_ADDRESS, addr & ~0x01); + } + physunmap(it8212_bar, IT8212_MEMMAP_SIZE); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +int it8212_init(void) +{ + uintptr_t addr; + + /* Needed only for PCI accesses on some platforms. + * FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms? + */ + get_io_perms(); + + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(PCI_ROM_ADDRESS, ata_it82); + + it8212_bar = physmap("IT8212F flash", addr, IT8212_MEMMAP_SIZE); + if (it8212_bar == ERROR_PTR) + goto error_out_unmap; + if (register_shutdown(it8212_shutdown, NULL)) + return 1; + + /* To restore ROM BAR enable once we are done. */ + it8212_rom_enable = addr & 0x01; + if (! it8212_rom_enable) + pci_write_long(pcidev_dev, PCI_ROM_ADDRESS, addr | 0x01); + + max_rom_decode.parallel = IT8212_MEMMAP_SIZE; + register_par_programmer(&par_programmer_it8212, BUS_PARALLEL); + return 0; + +error_out_unmap: + physunmap(it8212_bar, IT8212_MEMMAP_SIZE); + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, + chipaddr addr) +{ + pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + +static uint8_t it8212_chip_readb(const struct flashctx *flash, + const chipaddr addr) +{ + return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} Index: flashrom-it8212f/flashrom.c =================================================================== --- flashrom-it8212f/flashrom.c (revision 1539) +++ flashrom-it8212f/flashrom.c (working copy) @@ -261,6 +261,16 @@ }, #endif +#if CONFIG_IT8212 == 1 + { + .name = "it8212", + .init = it8212_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-it8212f/programmer.h =================================================================== --- flashrom-it8212f/programmer.h (revision 1539) +++ flashrom-it8212f/programmer.h (working copy) @@ -87,6 +87,9 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +#if CONFIG_IT8212 == 1 + PROGRAMMER_IT8212, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -456,6 +459,12 @@ int linux_spi_init(void); #endif +/* it8212.c */ +#if CONFIG_IT8212 == 1 +int it8212_init(void); +extern const struct pcidev_status ata_it82[]; +#endif + /* dediprog.c */ #if CONFIG_DEDIPROG == 1 int dediprog_init(void); Index: flashrom-it8212f/print.c =================================================================== --- flashrom-it8212f/print.c (revision 1539) +++ flashrom-it8212f/print.c (working copy) @@ -538,6 +538,11 @@ programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif +#if CONFIG_IT8212 == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_IT8212].name); + print_supported_pcidevs(ata_it82); +#endif } #if CONFIG_INTERNAL == 1

2 3

[PATCH] Unlock ST M50FW002 correctly
by Carl-Daniel Hailfinger 29 May '14

29 May '14

Unlock ST M50FW002 correctly Refactor ST M50 family unlocking TODO: Unify write_lockbits_49fl00x() and unlock_block_stm50() and unlock_w39_fwh_block() and unlock_82802ab() and write_lockbits_block_49lfxxxc(). They all use exactly the same mechanism, but they don't share any code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-stm50fw002_unlock/flashchips.c =================================================================== --- flashrom-stm50fw002_unlock/flashchips.c (Revision 1437) +++ flashrom-stm50fw002_unlock/flashchips.c (Arbeitskopie) @@ -7523,9 +7523,9 @@ .total_size = 256, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ + .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = { { @@ -7536,9 +7536,12 @@ {16 * 1024, 1}, }, .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {256 * 1024, 1}, }, + .block_erase = NULL, /* Only in A/A mux mode */ } }, - .unlock = unlock_stm50flw0x0x, + .unlock = unlock_stm50fw002, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ Index: flashrom-stm50fw002_unlock/stm50flw0x0x.c =================================================================== --- flashrom-stm50fw002_unlock/stm50flw0x0x.c (Revision 1437) +++ flashrom-stm50fw002_unlock/stm50flw0x0x.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,21 @@ #include "flashchips.h" #include "chipdrivers.h" +#define STM50_UNLOCKED 0x00 + +static int unlock_block_stm50(struct flashchip *flash, int offset) +{ + chipaddr lock = flash->virtual_registers + offset + 2; + + msg_cdbg("Unlocking at 0x%x\n", offset); + chip_writeb(STM50_UNLOCKED, lock); + if (chip_readb(lock) != STM50_UNLOCKED) { + msg_cerr("Cannot unlock at 0x%x\n", offset); + return -1; + } + return 0; +} + /* * claus.gindhart(a)kontron.com * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, @@ -38,8 +54,6 @@ */ static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { - chipaddr wrprotect = flash->virtual_registers + 2; - static const uint8_t unlock_sector = 0x00; int j; /* @@ -58,22 +72,12 @@ || (offset == 0xF0000)) { // unlock each 4k-sector - for (j = 0; j < 0x10000; j += 0x1000) { - msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", - offset + j); + for (j = 0; j < 0x10000; j += 0x1000) + if (unlock_block_stm50(flash, offset + j)) return -1; - } - } } else { - msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", offset); + if (unlock_block_stm50(flash, offset)) return -1; - } } return 0; @@ -93,6 +97,27 @@ return 0; } +/* FIXME: Should this be moved to a generic walk_unlockregions()? */ +int unlock_stm50fw002(struct flashchip *flash) +{ + static const struct eraseblock unlockregions[4] = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}}; + int i, j; + int addr = 0; + + for (i = 0; i < 4; i++) { + for (j = 0; j < unlockregions[i].count; j++) { + if (unlock_block_stm50(flash, addr)) + return 1; + addr += unlockregions[i].size; + } + } + return 0; +} + /* This function is unused. */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) { Index: flashrom-stm50fw002_unlock/chipdrivers.h =================================================================== --- flashrom-stm50fw002_unlock/chipdrivers.h (Revision 1437) +++ flashrom-stm50fw002_unlock/chipdrivers.h (Arbeitskopie) @@ -146,5 +146,6 @@ /* stm50flw0x0x.c */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int unlock_stm50flw0x0x(struct flashchip *flash); +int unlock_stm50fw002(struct flashchip *flash); #endif /* !__CHIPDRIVERS_H__ */ -- http://www.hailfinger.org/

3 3

Detection of MS-7094 as MS-6702E
by Stelios Tsampas 15 May '14

15 May '14

Flashrom detects MS-7094 (http://www.msi.com/product/mb/K8T-Neo2-F-V2-0.html) as MS-6702E (http://www.msi.com/product/mb/K8T-Neo2-F--FIR.html) Note: flashrom successfully flashed MS-7094 even though it wasn't detected properly but it couldn't flash MS-6702E as it couldn't find a suitable erase command. Edit: Re-attached proper lspci output

2 2

Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Carl-Daniel Hailfinger 09 May '14

09 May '14

Am 21.07.2011 17:54 schrieb Stefan Tauner: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Does the following not work for you? dd if=/dev/urandom bs=1k count=4k of=oldimage.bin flashrom -p dummy:emulate=SST25VF032B,image=oldimage.bin -w newimage.bin Regards, Carl-Daniel -- http://www.hailfinger.org/

5 8

Add timeout check to SPI bitbang bus request
by Carl-Daniel Hailfinger 29 Apr '14

29 Apr '14

Hi Iain, your Intel 82540EM which hangs on a flashrom run should spew "Timeout!" messages with this patch. It would be nice if you could tell us how long it waits for each chip probe so I can adjust the timeout value. Please note that this patch will _not_ fix the underlying issue, but I believe that an endless loop on possibly broken hardware is worse than aborting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_timeout/flash.h =================================================================== --- flashrom-bitbang_timeout/flash.h (Revision 1185) +++ flashrom-bitbang_timeout/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define TIMEOUT_ERROR -101 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-bitbang_timeout/bitbang_spi.c =================================================================== --- flashrom-bitbang_timeout/bitbang_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/bitbang_spi.c (Arbeitskopie) @@ -53,10 +53,11 @@ return bitbang_spi_master->get_miso(); } -static void bitbang_spi_request_bus(void) +static int bitbang_spi_request_bus(void) { if (bitbang_spi_master->request_bus) - bitbang_spi_master->request_bus(); + return bitbang_spi_master->request_bus(); + return 0; } static void bitbang_spi_release_bus(void) @@ -86,7 +87,7 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ + /* FIXME: Run bitbang_spi_request_bus here or per command? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); @@ -131,13 +132,15 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int i; + int i, ret; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the * programmer to use its own SPI engine for native accesses. */ - bitbang_spi_request_bus(); + ret = bitbang_spi_request_bus(); + if (ret) + return ret; bitbang_spi_set_cs(0); for (i = 0; i < writecnt; i++) bitbang_spi_readwrite_byte(writearr[i]); Index: flashrom-bitbang_timeout/nicintel_spi.c =================================================================== --- flashrom-bitbang_timeout/nicintel_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/nicintel_spi.c (Arbeitskopie) @@ -58,6 +58,8 @@ // #define FL_BUSY 30 // #define FL_ER 31 +#define MAX_REQUEST_LOOPS 10000 + uint8_t *nicintel_spibar; const struct pcidev_status nics_intel_spi[] = { @@ -68,16 +70,27 @@ {}, }; -static void nicintel_request_spibus(void) +static void nicintel_release_spibus(void); + +static int nicintel_request_spibus(void) { uint32_t tmp; + int i = 0; tmp = pci_mmio_readl(nicintel_spibar + FLA); tmp |= 1 << FL_REQ; pci_mmio_writel(tmp, nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ; + while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) { + if (i++ > MAX_REQUEST_LOOPS) { + nicintel_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } + + return 0; } static void nicintel_release_spibus(void) Index: flashrom-bitbang_timeout/mcp6x_spi.c =================================================================== --- flashrom-bitbang_timeout/mcp6x_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/mcp6x_spi.c (Arbeitskopie) @@ -40,22 +40,37 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 +#define MAX_REQUEST_LOOPS 10000 + void *mcp6x_spibar = NULL; /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; -static void mcp6x_request_spibus(void) +static void mcp6x_release_spibus(void); + +static int mcp6x_request_spibus(void) { + int i = 0; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) { + if (i++ > MAX_REQUEST_LOOPS) { + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp6x_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } /* Update the cache. */ mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return 0; } static void mcp6x_release_spibus(void) Index: flashrom-bitbang_timeout/programmer.h =================================================================== --- flashrom-bitbang_timeout/programmer.h (Revision 1185) +++ flashrom-bitbang_timeout/programmer.h (Arbeitskopie) @@ -131,7 +131,7 @@ void (*set_sck) (int val); void (*set_mosi) (int val); int (*get_miso) (void); - void (*request_bus) (void); + int (*request_bus) (void); void (*release_bus) (void); }; -- http://www.hailfinger.org/

4 15

Flashrom stuck using 100% cpu while probing for a chip
by GatoLoko 28 Apr '14

28 Apr '14

I've tried to run flashrom -V to see if it could identify the chip on my new board (AsRock M3A-GLAN), and it got stuck while probing for the first chip. I've tried commenting out that specific chip (AMIC A25L05PT) and then it gets stuck on the next one. Then commented out all AMIC chips, and it got stuck on the next one (the first ATMEL on the list) I've tried with an older flashrom (0.9.2-r1141). It skipped some AMD chips, then got stuck on AMIC again. Talked with "tlt" and "stefanct" on irc and they asked for a strace and a gdb backtrace. Strace produced no results. Gdb log is attached. "stefanct" tried and reproduced it on a machine with nicintel_spi, but warned it was with an unsupported nic: http://paste.flashrom.org/view.php?id=738 -- GatoLoko

4 11

Large FWH support
by Kyösti Mälkki 15 Sep '13

15 Sep '13

Hi I came across two problems using 2 MiB FWH flash on two different boards with old ICH4 and ICH6 chipsets: First, ICH3/4/5 do not implement fwh_idsel= parameter. If vendor bios had the default map of 1 MiB, it did not even detect 2 MiB flash chips. For this I have patches prepared already. Before: (idsel_failure.txt) Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xbf, id2 0x5c Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content After: (idsel_ok.txt) Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xbf, id2 0x5c Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xbf, id2 0x5c Found SST flash chip "SST49LF016C" (2048 kB, FWH) at physical address 0xffe00000. Second, a board with ICH6 had all except one 512 kiB range of flash disabled by vendor bios and it would not detect 1MiB and 2MiB flash chips. NOTE: the board actually had 512kiB flash for these logs, but you can see where ther problem is. Before: (decode-disabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode disabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled ... Maximum FWH chip size: 0x80000 bytes ... Probing for SST SST49LF008C, 1024 kB: Chip size 1024 kB is bigger than supported size 512 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content I used the following as a work-around for ICH6, but this should be derived from fwh_idsel= parameter: $ setpci -s 0:1f.0 0xd8.W=0xf0c0 After: (decode-enabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled Maximum FWH chip size: 0x200000 bytes Regards, Kyösti Mälkki

2 7

[PATCH] CONFIG_DEFAULT setting
by Carl-Daniel Hailfinger 14 Sep '13

14 Sep '13

Allow easy disabling of all programmers except selected ones by setting CONFIG_DEFAULT=no. Setting CONFIG_DEFAULT=yes has no effect. Usage example: # make CONFIG_DUMMY=yes CONFIG_NIC3COM=yes CONFIG_DEFAULT=no This will disable all programmers except dummy and nic3com. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-Makefile_config_default/Makefile =================================================================== --- flashrom-Makefile_config_default/Makefile (Revision 1623) +++ flashrom-Makefile_config_default/Makefile (Arbeitskopie) @@ -52,6 +52,10 @@ # Compilation will fail for unspecified values. CONFIG_DEFAULT_PROGRAMMER ?= PROGRAMMER_INVALID +# This parameter picks the default setting for CONFIG_ variables of programmers not specified explicitly +# on the command line. +CONFIG_DEFAULT ?= yes + # If your compiler spits out excessive warnings, run make WARNERROR=no # You shouldn't have to change this flag. WARNERROR ?= yes @@ -322,65 +326,65 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' # Always enable internal/onboard support for now. -CONFIG_INTERNAL ?= yes +CONFIG_INTERNAL ?= $(CONFIG_DEFAULT) # Always enable serprog for now. Needs to be disabled on Windows. -CONFIG_SERPROG ?= yes +CONFIG_SERPROG ?= $(CONFIG_DEFAULT) # RayeR SPIPGM hardware support -CONFIG_RAYER_SPI ?= yes +CONFIG_RAYER_SPI ?= $(CONFIG_DEFAULT) # PonyProg2000 SPI hardware support -CONFIG_PONY_SPI ?= yes +CONFIG_PONY_SPI ?= $(CONFIG_DEFAULT) # Always enable 3Com NICs for now. -CONFIG_NIC3COM ?= yes +CONFIG_NIC3COM ?= $(CONFIG_DEFAULT) # Enable NVIDIA graphics cards. Note: write and erase do not work properly. -CONFIG_GFXNVIDIA ?= yes +CONFIG_GFXNVIDIA ?= $(CONFIG_DEFAULT) # Always enable SiI SATA controllers for now. -CONFIG_SATASII ?= yes +CONFIG_SATASII ?= $(CONFIG_DEFAULT) # Highpoint (HPT) ATA/RAID controller support. # IMPORTANT: This code is not yet working! CONFIG_ATAHPT ?= no # Always enable FT2232 SPI dongles for now. -CONFIG_FT2232_SPI ?= yes +CONFIG_FT2232_SPI ?= $(CONFIG_DEFAULT) # Always enable dummy tracing for now. -CONFIG_DUMMY ?= yes +CONFIG_DUMMY ?= $(CONFIG_DEFAULT) # Always enable Dr. Kaiser for now. -CONFIG_DRKAISER ?= yes +CONFIG_DRKAISER ?= $(CONFIG_DEFAULT) # Always enable Realtek NICs for now. -CONFIG_NICREALTEK ?= yes +CONFIG_NICREALTEK ?= $(CONFIG_DEFAULT) # Disable National Semiconductor NICs until support is complete and tested. CONFIG_NICNATSEMI ?= no # Always enable Intel NICs for now. -CONFIG_NICINTEL ?= yes +CONFIG_NICINTEL ?= $(CONFIG_DEFAULT) # Always enable SPI on Intel NICs for now. -CONFIG_NICINTEL_SPI ?= yes +CONFIG_NICINTEL_SPI ?= $(CONFIG_DEFAULT) # Always enable SPI on OGP cards for now. -CONFIG_OGP_SPI ?= yes +CONFIG_OGP_SPI ?= $(CONFIG_DEFAULT) # Always enable Bus Pirate SPI for now. -CONFIG_BUSPIRATE_SPI ?= yes +CONFIG_BUSPIRATE_SPI ?= $(CONFIG_DEFAULT) # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no # Always enable Marvell SATA controllers for now. -CONFIG_SATAMV ?= yes +CONFIG_SATAMV ?= $(CONFIG_DEFAULT) # Enable Linux spidev interface by default. We disable it on non-Linux targets. -CONFIG_LINUX_SPI ?= yes +CONFIG_LINUX_SPI ?= $(CONFIG_DEFAULT) # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no -- http://www.hailfinger.org/

2 2

[PATCH] Remove exit call from physmap_common
by Niklas Söderlund 14 Sep '13

14 Sep '13

Only call path where exit is reached is from physmap(). Callers of physmap() that where not prepared to handle the ERROR_PTR return value have been handled. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- chipset_enable.c | 6 ++++++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ ichspi.c | 2 ++ it85spi.c | 2 ++ mcp6x_spi.c | 2 ++ nicintel_spi.c | 2 ++ ogp_spi.c | 2 ++ physmap.c | 12 +++--------- satasii.c | 2 ++ sb600spi.c | 2 ++ 11 files changed, 27 insertions(+), 9 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index fa79511..b1738ea 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -494,6 +494,8 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; /* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -565,6 +567,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -1235,6 +1239,8 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) /* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); + if (mmcr == ERROR_PTR) + return -1; /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e diff --git a/drkaiser.c b/drkaiser.c index 83b8b3d..71981e8 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -82,6 +82,8 @@ int drkaiser_init(void) /* Map 128kB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); + if (drkaiser_bar == ERROR_PTR) + return 1; if (register_shutdown(drkaiser_shutdown, NULL)) return 1; diff --git a/gfxnvidia.c b/gfxnvidia.c index 9232677..9600675 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -102,6 +102,8 @@ int gfxnvidia_init(void) msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); + if (nvidia_bar == ERROR_PTR) + return 1; /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) diff --git a/ichspi.c b/ichspi.c index bbe2b06..f6b77ad 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1836,6 +1836,8 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) int i; ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + if (ich_spibar == ERROR_PTR) + return ERROR_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ diff --git a/it85spi.c b/it85spi.c index 0b074eb..e15a287 100644 --- a/it85spi.c +++ b/it85spi.c @@ -262,6 +262,8 @@ static int it85xx_spi_common_init(struct superio s) * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); + if (base == ERROR_PTR) + return 1; msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ diff --git a/mcp6x_spi.c b/mcp6x_spi.c index ac40557..438e661 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -149,6 +149,8 @@ int mcp6x_spi_init(int want_spi) } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); + if (mcp6x_spibar == ERROR_PTR) + return 1; #if 0 /* FIXME: Run the physunmap in a shutdown function. */ diff --git a/nicintel_spi.c b/nicintel_spi.c index 72b470b..6dc40f5 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -178,6 +178,8 @@ int nicintel_spi_init(void) nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (nicintel_spibar == ERROR_PTR) + return 1; /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be diff --git a/ogp_spi.c b/ogp_spi.c index 9b596bf..b3963c2 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -138,6 +138,8 @@ int ogp_spi_init(void) return 1; ogp_spibar = physmap("OGP registers", io_base_addr, 4096); + if (ogp_spibar == ERROR_PTR) + return 1; if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; diff --git a/physmap.c b/physmap.c index adce315..35dcfb8 100644 --- a/physmap.c +++ b/physmap.c @@ -211,13 +211,11 @@ void physunmap(void *virt_addr, size_t len) } #endif -#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 static void *physmap_common(const char *descr, unsigned long phys_addr, - size_t len, int mayfail, int readonly) + size_t len, int readonly) { void *virt_addr; @@ -261,8 +259,6 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, "and reboot, or reboot into\n" "single user mode.\n"); #endif - if (!mayfail) - exit(3); } return virt_addr; @@ -270,14 +266,12 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, void *physmap(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, - PHYSMAP_RW); + return physmap_common(descr, phys_addr, len, PHYSMAP_RW); } void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, - PHYSMAP_RO); + return physmap_common(descr, phys_addr, len, PHYSMAP_RO); } #if defined(__i386__) || defined(__x86_64__) diff --git a/satasii.c b/satasii.c index 838fff4..9f9bb7f 100644 --- a/satasii.c +++ b/satasii.c @@ -97,6 +97,8 @@ int satasii_init(void) } sii_bar = physmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE) + reg_offset; + if (sii_bar == ERROR_PTR) + return 1; /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..a4ca20b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -226,6 +226,8 @@ int sb600_probe_spi(struct pci_dev *dev) /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (sb600_spibar == ERROR_PTR) + return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */ -- 1.7.12.4

2 1

[PATCH] Remove exit call from sys_physmap_*
by Niklas Söderlund 13 Sep '13

13 Sep '13

All callers are prepared to handle error if ERROR_PTR is returned. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- physmap.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/physmap.c b/physmap.c index 5aa9874..adce315 100644 --- a/physmap.c +++ b/physmap.c @@ -173,12 +173,11 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* Open the memory device UNCACHED. Important for MMIO. */ if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { perror("Critical error: open(" MEM_DEV ")"); - exit(2); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -192,14 +191,12 @@ static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) if (-1 == fd_mem_cached) { /* Open the memory device CACHED. */ if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - msg_perr("Critical error: open(" MEM_DEV "): %s", - strerror(errno)); - exit(2); + msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno)); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, - fd_mem_cached, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, fd_mem_cached, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -209,7 +206,7 @@ void physunmap(void *virt_addr, size_t len) msg_pspew("Not unmapping zero size at %p\n", virt_addr); return; } - + munmap(virt_addr, len); } #endif -- 1.7.12.3

2 1

[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger 21 Aug '13

21 Aug '13

flashrom relies on svn to export tarballs and only prints the last svn revision in the version message even if flashrom is in a git tree. Print extended version information (version, svn revision, git hash, repository URL). Allow exporting from git trees. This should make git users first-class citizens like svn users. Side note: If anyone has an idea how to make the export target more beautiful (80 column limit etc.), please tell me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-gitfriendly/Makefile =================================================================== --- flashrom-gitfriendly/Makefile (Revision 1145) +++ flashrom-gitfriendly/Makefile (Arbeitskopie) @@ -97,13 +97,15 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/') +SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown ) RELEASE := 0.9.2 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION) RELEASENAME ?= $(VERSION) -SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"' # Always enable internal/onboard support for now. CONFIG_INTERNAL ?= yes @@ -310,7 +312,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. @@ -420,9 +422,12 @@ export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) - @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) - @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile - @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/ + @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode + @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile + @# ChangeLog should be in English, but we want UTF-8 for names. + @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules @echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/ tarball: export Index: flashrom-gitfriendly/flashrom.c =================================================================== --- flashrom-gitfriendly/flashrom.c (Revision 1145) +++ flashrom-gitfriendly/flashrom.c (Arbeitskopie) @@ -1355,6 +1355,7 @@ void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo(" from " FLASHROM_SCMURL ","); print_sysinfo(); } @@ -1362,7 +1363,6 @@ { msg_ginfo("flashrom is free software, get the source code at " "http://www.flashrom.org\n"); - msg_ginfo("\n"); } int selfcheck(void) -- http://www.hailfinger.org/

5 11

Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

[RFC] Layout handling...
by Carl-Daniel Hailfinger 12 Jul '13

12 Jul '13

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

Re: [flashrom] USB 3 PCI Card support (request to add device)
by Philipp Post 13 Jun '13

13 Jun '13

I have added some flashrom and linux logs which might be helpfull: The USB 3 PCI card has the following system properties: DRIVER=xhci_hcd PCI_CLASS=C0330 PCI_ID=1033:0194 PCI_SUBSYS_ID=1033:0194 PCI_SLOT_NAME=0000:03:00.0 MODALIAS=pci:v00001033d00000194sv00001033sd00000194bc0Csc03i30 There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 02:0a.0) and a PCI soundcard installed. Tried to read the flash rom out of the 82541PI Intel NIC without problems. /sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to "rom" which the USB 3 and the soundcard do not. I am not sure if that means that the rom is not accessible at all or if Ubuntu just does not know how. Thanks in advance, brgds Philipp -----Ursprüngliche Nachricht----- Von: Philipp Post [mailto:Post.Philipp@googlemail.com] Gesendet: Donnerstag, 24. Januar 2013 19:23 An: 'flashrom(a)flashrom.org' Betreff: USB 3 PCI Card support (request to add device) Good day, following configuration: - USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB chip and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in - IBM NetVista 8305 Desktop PC - built year 2003 The issue with the card is that it needs a flash rom update to work with Windows Vista and up, otherwise the device does not work at all in these OS ("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu 11.3 out of the box works fine. RENESAS has a rom update for the chip and a flash update tool which however does not work with PCI cards, but just chips soldered to mainboards. At least this seems to me the reason why it does not work. Chip is recognized but the RENESAS tool says "Can not load / access firmware". The tool has the option to change the device / vendor id as well via .ini file. The card used is the only PCI USB 3 card on the market and basically works very well when it works - with max PCI speed of course, which means approx. double speed of USB 2. The card exists in hardware version 1 (RENESAS chip uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to hardware version 1. The name of the manufacturer behind the card is unknown to me, but it could be an ADDONICS product. I do not have a technical drawing of the card and I fear I can not obtain one but I do have the card itself. My question: would it be possible to incorporate this card into flashrom? Would be great if someone could do it as I do not have the necessary skills to do it myself. In case you need further information, please let me know. Thanks in advance, brgds Philipp Links and further reading: -------------------------- Card Information from different sellers (same card): http://www.addonics.com/products/ad2u3pci.php http://eu.startech.com/Cards-Adapters/USB-3.0/Cards/2-Port-PCI-SuperSpeed-US B-3-Card-Adapter~PCIUSB3S2 http://www.lindy.de/premium-usb-3-karte-2-port-pci/51082.html ATMEL rom specification (contains info how to write rom images): www.atmel.com/Images/doc3689.pdf Renesas USB chip information: http://www.renesas.eu/products/soc/usb_assp/product/upd720200a/index.jsp RENESAS rom update 4.0.2.0 with Windows updater (32 + 64 Bit) and drivers: http://www.station-drivers.com/page/renesas.htm We need: "Firmware Version 4.0.2.0 pour uPD720200a" RENESAS MS DOS flash update tool (which did not do the job): http://www.computerbase.de/forum/attachment.php?attachmentid=283282&d=133832 3319 IBM NetVista 8305 Hardware Maintenance Manual: http://download.lenovo.com/ibmdl/pub/pc/pccbbs/netvista_pdf/24p2969.pdf Hardware Ids: Renesas Electronics USB 3.0 Host Controller: PCI\VEN_1033&DEV_0194&SUBSYS_01941033&REV_04\5&25043F3&0&0048F0 Renesas Electronics USB 3.0 Root Hub NUSB3\ROOT_HUB30\6&2D374EF3&2

2 6

mac address problem with nvidia MCP55V-Pro
by Jon Morby 02 Jun '13

02 Jun '13

hi … I don't suppose anyone has any experience updating or fixing MAC addresses on Nvidea nVIDIA MCP55V-Pro (Supermicro H8DMT+) ? Following an experimental reflash everything went well, except afterwards we noticed the mac address had been reset link/ether 66:77:44:22:33:12 brd ff:ff:ff:ff:ff:ff -- Jon Morby FidoNet - the internet made simple! 10 - 16 Tiller Road, London, E14 8PX tel: 0845 004 3050 / fax: 0845 004 3051

4 5

Asrock Fatal1ty Z77 Performance > unsupported - logs attached
by "Jürgen Dorn" 01 Jun '13

01 Jun '13

regards, Jürgen

2 1

Re: [flashrom] [PATCH] Enable spi clock setting in dediprog driver
by Nico Huber 06 May '13

06 May '13

Rebased this one, following patches are based on it. This adds a programmer parameter 'spispeed' to the dediprog driver to control the transfer rate on the spi bus. The following rates are available (in Hz): 375k, 750k, 1.5M, 2.18M, 3M, 8M, 12M and 24M The original driver reinitializes the programmer after setting the speed, so the initialization calls have moved into a new function dediprog_setup() which is called twice. Signed-off-by: Nico Huber <nico.huber(a)secunet.com> diff --git a/dediprog.c b/dediprog.c index a81cf83..60067a8 100644 --- a/dediprog.c +++ b/dediprog.c @@ -152,7 +152,23 @@ static int dediprog_set_spi_voltage(int millivolt) return 0; } -#if 0 +struct dediprog_spispeeds { + const char *const name; + const int speed; +}; + +static const struct dediprog_spispeeds spispeeds[] = { + { "24M", 0x0 }, + { "12M", 0x2 }, + { "8M", 0x1 }, + { "3M", 0x3 }, + { "2.18M", 0x4 }, + { "1.5M", 0x5 }, + { "750k", 0x6 }, + { "375k", 0x7 }, + { NULL, 0x0 }, +}; + /* After dediprog_set_spi_speed, the original app always calls * dediprog_set_spi_voltage(0) and then * dediprog_check_devicestring() four times in a row. @@ -160,56 +176,20 @@ static int dediprog_set_spi_voltage(int millivolt) * This looks suspiciously like the microprocessor in the SF100 has to be * restarted/reinitialized in case the speed changes. */ -static int dediprog_set_spi_speed(uint16_t speed) +static int dediprog_set_spi_speed(unsigned int spispeed_idx) { int ret; - unsigned int khz; - /* Case 1 and 2 are in weird order. Probably an organically "grown" - * interface. - * Base frequency is 24000 kHz, divisors are (in order) - * 1, 3, 2, 8, 11, 16, 32, 64. - */ - switch (speed) { - case 0x0: - khz = 24000; - break; - case 0x1: - khz = 8000; - break; - case 0x2: - khz = 12000; - break; - case 0x3: - khz = 3000; - break; - case 0x4: - khz = 2180; - break; - case 0x5: - khz = 1500; - break; - case 0x6: - khz = 750; - break; - case 0x7: - khz = 375; - break; - default: - msg_perr("Unknown frequency selector 0x%x! Aborting.\n", speed); - return 1; - } - msg_pdbg("Setting SPI speed to %u kHz\n", khz); + msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, speed, 0xff, NULL, - 0x0, DEFAULT_TIMEOUT); + ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command Set SPI Speed 0x%x failed!\n", speed); + msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; } return 0; } -#endif /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. * @start start address @@ -736,6 +716,28 @@ static int parse_voltage(char *voltage) return millivolt; } +static int dediprog_setup(void) +{ + /* URB 6. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 7. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 8. Command Prepare Receive Device String. */ + /* URB 9. Command Receive Device String. */ + if (dediprog_check_devicestring()) { + return 1; + } + /* URB 10. Command C. */ + if (dediprog_command_c()) { + return 1; + } + return 0; +} + static const struct spi_programmer spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, @@ -777,12 +779,21 @@ static int dediprog_shutdown(void *data) int dediprog_init(void) { struct usb_device *dev; - char *voltage; - int millivolt = 3500; - int ret; + char *voltage, *spispeed; + int spispeed_idx = 2, millivolt = 3500; + int i, ret; msg_pspew("%s\n", __func__); + spispeed = extract_programmer_param("spispeed"); + if (spispeed) { + for (i = 0; spispeeds[i].name; ++i) { + if (!strcasecmp(spispeeds[i].name, spispeed)) { + spispeed_idx = i; + break; + } + } + } voltage = extract_programmer_param("voltage"); if (voltage) { millivolt = parse_voltage(voltage); @@ -821,33 +832,26 @@ int dediprog_init(void) return 1; } dediprog_endpoint = 2; - + if (register_shutdown(dediprog_shutdown, NULL)) return 1; dediprog_set_leds(PASS_ON|BUSY_ON|ERROR_ON); - /* URB 6. Command A. */ - if (dediprog_command_a()) { + /* Perform basic setup. */ + if (dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } - /* URB 7. Command A. */ - if (dediprog_command_a()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 8. Command Prepare Receive Device String. */ - /* URB 9. Command Receive Device String. */ - if (dediprog_check_devicestring()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 10. Command C. */ - if (dediprog_command_c()) { + + /* After setting voltage and speed, perform setup again. */ + if (dediprog_set_spi_voltage(0) || + dediprog_set_spi_speed(spispeed_idx) || + dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } + /* URB 11. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(millivolt)) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); diff --git a/flashrom.8 b/flashrom.8 index b054c28..99e064e 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -651,6 +651,18 @@ where can be .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. +.sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus. Syntax is +.sp +.B " flashrom \-p dediprog:spispeed=frequency" +.sp +where +.B frequency +can be +.BR 375k ", " 750k ", " 1.5M ", " 2.18M ", " 3M ", " 8M ", " 12M " or " 24M +(in Hz). The default is a frequency of 12 MHz. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use

3 4

[PATCH] Bump dediprog driver to use libusb-1.0
by Nico Huber 30 Mar '13

30 Mar '13

This patch tracks the changes in the libusb interface. Nothing changed in the behaviour of the driver, so far. It will be used by a follow-up patch. It's based on "Enable spi clock setting in dediprog driver". Signed-off-by: Nico Huber <nico.huber(a)secunet.com> diff --git a/Makefile b/Makefile index b087b3d..6da7226 100644 --- a/Makefile +++ b/Makefile @@ -531,7 +531,7 @@ endif ifeq ($(CONFIG_DEDIPROG), yes) FEATURE_CFLAGS += -D'CONFIG_DEDIPROG=1' -FEATURE_LIBS += -lusb +FEATURE_LIBS += -lusb-1.0 PROGRAMMER_OBJS += dediprog.o endif diff --git a/dediprog.c b/dediprog.c index 60067a8..a558285 100644 --- a/dediprog.c +++ b/dediprog.c @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2010 Carl-Daniel Hailfinger + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +20,8 @@ #include <stdio.h> #include <string.h> -#include <usb.h> +#include <stdlib.h> +#include <libusb-1.0/libusb.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -27,7 +29,8 @@ #define FIRMWARE_VERSION(x,y,z) ((x << 16) | (y << 8) | z) #define DEFAULT_TIMEOUT 3000 -static usb_dev_handle *dediprog_handle; +static libusb_context *usb_ctx; +static libusb_device_handle *dediprog_handle; static int dediprog_firmwareversion; static int dediprog_endpoint; @@ -45,23 +48,6 @@ static void print_hex(void *buf, size_t len) } #endif -/* Might be useful for other USB devices as well. static for now. */ -static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) -{ - struct usb_bus *bus; - struct usb_device *dev; - - for (bus = usb_get_busses(); bus; bus = bus->next) - for (dev = bus->devices; dev; dev = dev->next) - if ((dev->descriptor.idVendor == vid) && - (dev->descriptor.idProduct == pid)) - return dev; - - return NULL; -} - -//int usb_control_msg(usb_dev_handle *dev, int requesttype, int request, int value, int index, char *bytes, int size, int timeout); - /* Set/clear LEDs on dediprog */ #define PASS_ON (0 << 0) #define PASS_OFF (1 << 0) @@ -95,11 +81,10 @@ static int dediprog_set_leds(int leds) target_leds = leds; } - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, - NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command Set LED 0x%x failed (%s)!\n", - leds, usb_strerror()); + msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, libusb_error_name(ret)); return 1; } @@ -138,8 +123,8 @@ static int dediprog_set_spi_voltage(int millivolt) /* Wait some time as the original driver does. */ programmer_delay(200 * 1000); } - ret = usb_control_msg(dediprog_handle, 0x42, 0x9, voltage_selector, - 0xff, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x9, voltage_selector, + 0xff, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set SPI Voltage 0x%x failed!\n", voltage_selector); @@ -182,8 +167,8 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, - NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; @@ -199,15 +184,15 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int ret; + int ret, transferred; unsigned int i; /* chunksize must be 512, other sizes will NOT work at all. */ const unsigned int chunksize = 0x200; const unsigned int count = len / chunksize; - const char count_and_chunk[] = {count & 0xff, - (count >> 8) & 0xff, - chunksize & 0xff, - (chunksize >> 8) & 0xff}; + const unsigned char count_and_chunk[] = { + count & 0xff, (count >> 8) & 0xff, + chunksize & 0xff, (chunksize >> 8) & 0xff + }; if ((start % chunksize) || (len % chunksize)) { msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " @@ -221,22 +206,20 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, /* Command Read SPI Bulk. No idea which read command is used on the * SPI side. */ - ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % 0x10000, - start / 0x10000, (char *)count_and_chunk, - sizeof(count_and_chunk), DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x20, start % 0x10000, start / 0x10000, + (unsigned char *)count_and_chunk, sizeof(count_and_chunk), + DEFAULT_TIMEOUT); if (ret != sizeof(count_and_chunk)) { - msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, - usb_strerror()); + msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, libusb_error_name(ret)); return 1; } for (i = 0; i < count; i++) { - ret = usb_bulk_read(dediprog_handle, 0x80 | dediprog_endpoint, - (char *)buf + i * chunksize, chunksize, - DEFAULT_TIMEOUT); - if (ret != chunksize) { - msg_perr("SPI bulk read %i failed, expected %i, got %i " - "%s!\n", i, chunksize, ret, usb_strerror()); + ret = libusb_bulk_transfer(dediprog_handle, 0x80 | dediprog_endpoint, + buf + i * chunksize, chunksize, &transferred, DEFAULT_TIMEOUT); + if ((ret < 0) || (transferred != chunksize)) { + msg_perr("SPI bulk read %i failed, expected %i, got %i %s!\n", + i, chunksize, ret, libusb_error_name(ret)); return 1; } } @@ -300,7 +283,7 @@ static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigned int chunksize, unsigned int start, unsigned int len, uint8_t dedi_spi_cmd) { - int ret; + int ret, transferred; unsigned int i; /* USB transfer size must be 512, other sizes will NOT work at all. * chunksize is the real data size per USB bulk transfer. The remaining @@ -308,7 +291,7 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigne */ const unsigned int count = len / chunksize; const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd}; - char usbbuf[512]; + unsigned char usbbuf[512]; /* * We should change this check to @@ -333,23 +316,21 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigne /* Command Write SPI Bulk. No idea which write command is used on the * SPI side. */ - ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, - (char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, + (unsigned char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); if (ret != sizeof(count_and_cmd)) { - msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, - usb_strerror()); + msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, libusb_error_name(ret)); return 1; } for (i = 0; i < count; i++) { memset(usbbuf, 0xff, sizeof(usbbuf)); memcpy(usbbuf, buf + i * chunksize, chunksize); - ret = usb_bulk_write(dediprog_handle, dediprog_endpoint, - usbbuf, 512, - DEFAULT_TIMEOUT); - if (ret != 512) { - msg_perr("SPI bulk write failed, expected %i, got %i " - "%s!\n", 512, ret, usb_strerror()); + ret = libusb_bulk_transfer(dediprog_handle, dediprog_endpoint, + usbbuf, 512, &transferred, DEFAULT_TIMEOUT); + if ((ret < 0) || (transferred != 512)) { + msg_perr("SPI bulk write failed, expected %i, got %i %s!\n", + 512, ret, libusb_error_name(ret)); return 1; } } @@ -438,23 +419,20 @@ static int dediprog_spi_send_command(struct flashctx *flash, msg_perr("Untested readcnt=%i, aborting.\n", readcnt); return 1; } - - ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, - readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, - DEFAULT_TIMEOUT); + + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x1, 0xff, readcnt ? 0x1 : 0x0, + (unsigned char *)writearr, writecnt, DEFAULT_TIMEOUT); if (ret != writecnt) { - msg_perr("Send SPI failed, expected %i, got %i %s!\n", - writecnt, ret, usb_strerror()); + msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, libusb_error_name(ret)); return 1; } if (!readcnt) return 0; memset(readarr, 0, readcnt); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, - (char *)readarr, readcnt, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, + readarr, readcnt, DEFAULT_TIMEOUT); if (ret != readcnt) { - msg_perr("Receive SPI failed, expected %i, got %i %s!\n", - readcnt, ret, usb_strerror()); + msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, libusb_error_name(ret)); return 1; } return 0; @@ -464,22 +442,18 @@ static int dediprog_check_devicestring(void) { int ret; int fw[3]; - char buf[0x11]; + unsigned char buf[0x11]; /* Command Prepare Receive Device String. */ memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf, - 0x1, DEFAULT_TIMEOUT); - /* The char casting is needed to stop gcc complaining about an always true comparison. */ - if ((ret != 0x1) || (buf[0] != (char)0xff)) { - msg_perr("Unexpected response to Command Prepare Receive Device" - " String!\n"); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf, 0x1, DEFAULT_TIMEOUT); + if ((ret != 0x1) || (buf[0] != 0xff)) { + msg_perr("Unexpected response to Command Prepare Receive Device String!\n"); return 1; } /* Command Receive Device String. */ memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, - 0x10, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, 0x10, DEFAULT_TIMEOUT); if (ret != 0x10) { msg_perr("Incomplete/failed Command Receive Device String!\n"); return 1; @@ -490,7 +464,7 @@ static int dediprog_check_devicestring(void) msg_perr("Device not a SF100!\n"); return 1; } - if (sscanf(buf, "SF100 V:%d.%d.%d ", &fw[0], &fw[1], &fw[2]) != 3) { + if (sscanf((const char *)buf, "SF100 V:%d.%d.%d ", &fw[0], &fw[1], &fw[2]) != 3) { msg_perr("Unexpected firmware version string!\n"); return 1; } @@ -511,13 +485,12 @@ static int dediprog_check_devicestring(void) static int dediprog_command_a(void) { int ret; - char buf[0x1]; + unsigned char buf[0x1]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf, - 0x1, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf, 0x1, DEFAULT_TIMEOUT); if (ret < 0) { - msg_perr("Command A failed (%s)!\n", usb_strerror()); + msg_perr("Command A failed (%s)!\n", libusb_error_name(ret)); return 1; } if ((ret != 0x1) || (buf[0] != 0x6f)) { @@ -535,13 +508,12 @@ static int dediprog_command_a(void) static int dediprog_command_b(void) { int ret; - char buf[0x3]; + unsigned char buf[0x3]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, - 0x3, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, 0x3, DEFAULT_TIMEOUT); if (ret < 0) { - msg_perr("Command B failed (%s)!\n", usb_strerror()); + msg_perr("Command B failed (%s)!\n", libusb_error_name(ret)); return 1; } if ((ret != 0x3) || (buf[0] != 0xff) || (buf[1] != 0xff) || @@ -563,10 +535,9 @@ static int dediprog_command_c(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, - 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command C failed (%s)!\n", usb_strerror()); + msg_perr("Command C failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -581,17 +552,16 @@ static int dediprog_command_c(void) static int dediprog_command_f(int timeout) { int ret; - char buf[0x1]; + unsigned char buf[0x1]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, - 0x1, timeout); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, 0x1, timeout); /* This check is most probably wrong. Command F always causes a timeout * in the logs, so we should check for timeout instead of checking for * success. */ if (ret != 0x1) { - msg_perr("Command F failed (%s)!\n", usb_strerror()); + msg_perr("Command F failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -605,9 +575,9 @@ static int dediprog_command_g(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command G failed (%s)!\n", usb_strerror()); + msg_perr("Command G failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -622,9 +592,9 @@ static int dediprog_command_h(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command H failed (%s)!\n", usb_strerror()); + msg_perr("Command H failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -639,9 +609,9 @@ static int dediprog_command_i(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command I failed (%s)!\n", usb_strerror()); + msg_perr("Command I failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -659,9 +629,9 @@ static int dediprog_command_j(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command J failed (%s)!\n", usb_strerror()); + msg_perr("Command J failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -764,24 +734,22 @@ static int dediprog_shutdown(void *data) if (dediprog_set_spi_voltage(0x0)) return 1; - if (usb_release_interface(dediprog_handle, 0)) { + if (libusb_release_interface(dediprog_handle, 0)) { msg_perr("Could not release USB interface!\n"); return 1; } - if (usb_close(dediprog_handle)) { - msg_perr("Could not close USB device!\n"); - return 1; - } + libusb_close(dediprog_handle); + libusb_exit(usb_ctx); return 0; } /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { - struct usb_device *dev; char *voltage, *spispeed; int spispeed_idx = 2, millivolt = 3500; int i, ret; + struct libusb_device_descriptor usb_desc; msg_pspew("%s\n", __func__); @@ -804,31 +772,31 @@ int dediprog_init(void) } /* Here comes the USB stuff. */ - usb_init(); - usb_find_busses(); - usb_find_devices(); - dev = get_device_by_vid_pid(0x0483, 0xdada); - if (!dev) { + libusb_init(&usb_ctx); + if (!usb_ctx) { + msg_perr("Could not open libusb interface!\n"); + return 1; + } + dediprog_handle = libusb_open_device_with_vid_pid(usb_ctx, 0x0483, 0xdada); + if (!dediprog_handle) { msg_perr("Could not find a Dediprog SF100 on USB!\n"); return 1; } - msg_pdbg("Found USB device (%04x:%04x).\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - dediprog_handle = usb_open(dev); - ret = usb_set_configuration(dediprog_handle, 1); - if (ret < 0) { - msg_perr("Could not set USB device configuration: %i %s\n", - ret, usb_strerror()); - if (usb_close(dediprog_handle)) - msg_perr("Could not close USB device!\n"); + ret = libusb_get_device_descriptor(libusb_get_device(dediprog_handle), &usb_desc); + if (ret != 0) + msg_pinfo("Warning: Could not get usb device descriptor: %i %s\n", ret, libusb_error_name(ret)); + else + msg_pdbg("Found USB device (%04hx:%04hx).\n", usb_desc.idVendor, usb_desc.idProduct); + ret = libusb_set_configuration(dediprog_handle, 1); + if (ret != 0) { + msg_perr("Could not set USB device configuration: %i %s\n", ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); return 1; } - ret = usb_claim_interface(dediprog_handle, 0); + ret = libusb_claim_interface(dediprog_handle, 0); if (ret < 0) { - msg_perr("Could not claim USB device interface %i: %i %s\n", - 0, ret, usb_strerror()); - if (usb_close(dediprog_handle)) - msg_perr("Could not close USB device!\n"); + msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); return 1; } dediprog_endpoint = 2;

4 6

[PATCH v5] Add Altera USB-Blaster SPI programmer.
by Kyösti Mälkki 27 Mar '13

27 Mar '13

Rebased on Revision 1650. There remains a minor glitch with Makefile: If one sets CONFIG_FT2322_SPI=no, also USB-Blaster support will be disabled. In my opinion fixing this is not within the scope of this patch. Adds support for the Altera USB-Blaster programming dongle in Active Serial (AS) mode. Tested on both original product and a clone dongle. Signed-off-by: James Laird <jhl(a)mafipulation.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 23 ++++++ README | 4 +- flashrom.8 | 6 +- flashrom.c | 12 +++ programmer.h | 12 +++ usbblaster_spi.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 278 insertions(+), 4 deletions(-) create mode 100644 usbblaster_spi.c diff --git a/Makefile b/Makefile index b948996..f7aaf95 100644 --- a/Makefile +++ b/Makefile @@ -128,6 +128,11 @@ UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no +endif endif # FIXME: Should we check for Cygwin/MSVC as well? @@ -240,6 +245,11 @@ UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no +endif endif ifneq ($(TARGET_OS), Linux) @@ -349,6 +359,9 @@ CONFIG_ATAHPT ?= no # Always enable FT2232 SPI dongles for now. CONFIG_FT2232_SPI ?= yes +# Always enable Altera USB-Blaster dongles for now. +CONFIG_USBBLASTER_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -484,6 +497,16 @@ PROGRAMMER_OBJS += ft2232_spi.o # into a hard requirement for libusb, defeating the purpose of auto-enabling. endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") +# This is a totally ugly hack. +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'CONFIG_USBBLASTER_SPI=1'") +FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") +PROGRAMMER_OBJS += usbblaster_spi.o +# We can't set NEED_USB here because that would transform libftdi auto-enabling +# into a hard requirement for libusb, defeating the purpose of auto-enabling. +endif + ifeq ($(CONFIG_DUMMY), yes) FEATURE_CFLAGS += -D'CONFIG_DUMMY=1' PROGRAMMER_OBJS += dummyflasher.o diff --git a/README b/README index 8e812be..7f24cca 100644 --- a/README +++ b/README @@ -45,8 +45,8 @@ Build Instructions To build flashrom you need to install the following software: * pciutils+libpci (if you want support for mainboard or PCI device flashing) - * libusb (if you want FT2232 or Dediprog support) - * libftdi (if you want FT2232 support) + * libusb (if you want FT2232, Dediprog or USB-Blaster support) + * libftdi (if you want FT2232 or USB-Blaster support) Linux et al: diff --git a/flashrom.8 b/flashrom.8 index c6c518e..feb70d6 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -220,6 +220,8 @@ bitbanging adapter) .sp .BR "* linux_spi" " (for SPI flash ROMs accessible via /dev/spidevX.Y on Linux)" .sp +.BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -837,7 +839,7 @@ needs TCP access to the network or userspace access to a serial port. .B buspirate_spi needs userspace access to a serial port. .sp -.BR dediprog " and " ft2232_spi +.BR dediprog ", " ft2232_spi " and " usbblaster_spi need access to the USB device via libusb. .sp .B dummy @@ -847,7 +849,7 @@ needs no access permissions at all. .BR gfxnvidia ", " drkaiser ", " satasii ", " satamv " and " atahpt have to be run as superuser/root, and need additional raw access permission. .sp -.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +.BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi " and " ft2232_spi can be run as normal user on most operating systems if appropriate device permissions are set. .sp diff --git a/flashrom.c b/flashrom.c index e1be398..e787197 100644 --- a/flashrom.c +++ b/flashrom.c @@ -308,6 +308,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_USBBLASTER_SPI == 1 + { + .name = "usbblaster_spi", + .type = USB, + .devs.dev = devs_usbblasterspi, + .init = usbblaster_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/programmer.h b/programmer.h index 51a8c80..dd2ba30 100644 --- a/programmer.h +++ b/programmer.h @@ -87,6 +87,9 @@ enum programmer { #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +#if CONFIG_USBBLASTER_SPI == 1 + PROGRAMMER_USBBLASTER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -431,6 +434,12 @@ int ft2232_spi_init(void); extern const struct dev_entry devs_ft2232spi[]; #endif +/* usbblaster_spi.c */ +#if CONFIG_USBBLASTER_SPI == 1 +int usbblaster_spi_init(void); +extern const struct dev_entry devs_usbblasterspi[]; +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -509,6 +518,9 @@ enum spi_controller { #if CONFIG_SERPROG == 1 SPI_CONTROLLER_SERPROG, #endif +#if CONFIG_USBBLASTER_SPI == 1 + SPI_CONTROLLER_USBBLASTER, +#endif }; #define MAX_DATA_UNSPECIFIED 0 diff --git a/usbblaster_spi.c b/usbblaster_spi.c new file mode 100644 index 0000000..53eb7d5 --- /dev/null +++ b/usbblaster_spi.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2012 James Laird <jhl(a)mafipulation.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Device should be connected as per "active serial" mode: + * + * +---------+------+-----------+ + * | SPI | Pin | Altera | + * +---------+------+-----------+ + * | SCLK | 1 | DCLK | + * | GND | 2,10 | GND | + * | VCC | 4 | VCC(TRGT) | + * | MISO | 7 | DATAOUT | + * | /CS | 8 | nCS | + * | MOSI | 9 | ASDI | + * +---------+------+-----------+ + * + * See also the USB-Blaster Download Cable User Guide: http://www.altera.com/literature/ug/ug_usb_blstr.pdf + */ + +#if CONFIG_USBBLASTER_SPI == 1 + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include <ftdi.h> +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +/* Please keep sorted by vendor ID, then device ID. */ +#define ALTERA_VID 0x09fb +#define ALTERA_USBBLASTER_PID 0x6001 + +const struct dev_entry devs_usbblasterspi[] = { + {ALTERA_VID, ALTERA_USBBLASTER_PID, OK, "Altera", "USB-Blaster"}, + + {} +}; + +static const struct spi_programmer spi_programmer_usbblaster; + +static struct ftdi_context ftdic; + +// command bytes +#define BIT_BYTE (1<<7) // byte mode (rather than bitbang) +#define BIT_READ (1<<6) // read request +#define BIT_LED (1<<5) +#define BIT_CS (1<<3) +#define BIT_TMS (1<<1) +#define BIT_CLK (1<<0) + +#define BUF_SIZE 64 + +/* The programmer shifts bits in the wrong order for SPI, so we use this method to reverse the bits when needed. + * http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith32Bits */ +uint8_t reverse(uint8_t b) +{ + return ((b * 0x0802LU & 0x22110LU) | (b * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16; +} + + +/* Returns 0 upon success, a negative number upon errors. */ +int usbblaster_spi_init(void) +{ + uint8_t buf[BUF_SIZE + 1]; + + if (ftdi_init(&ftdic) < 0) + return -1; + + if (ftdi_usb_open(&ftdic, ALTERA_VID, ALTERA_USBBLASTER_PID) < 0) { + msg_perr("Failed to open USB-Blaster: %s\n", ftdic.error_str); + return -1; + } + + if (ftdi_usb_reset(&ftdic) < 0) { + msg_perr("USB-Blaster reset failed\n"); + return -1; + } + + if (ftdi_set_latency_timer(&ftdic, 2) < 0) { + msg_perr("USB-Blaster set latency timer failed\n"); + return -1; + } + + if (ftdi_write_data_set_chunksize(&ftdic, 4096) < 0 || + ftdi_read_data_set_chunksize(&ftdic, BUF_SIZE) < 0) { + msg_perr("USB-Blaster set chunk size failed\n"); + return -1; + } + + memset(buf, 0, sizeof(buf)); + buf[sizeof(buf)-1] = BIT_LED | BIT_CS; + if (ftdi_write_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("USB-Blaster reset write failed\n"); + return -1; + } + if (ftdi_read_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("USB-Blaster reset read failed\n"); + return -1; + } + + register_spi_programmer(&spi_programmer_usbblaster); + return 0; +} + +static int send_write(unsigned int writecnt, const unsigned char *writearr) +{ + int i; + uint8_t buf[BUF_SIZE]; + + memset(buf, 0, sizeof(buf)); + while (writecnt) { + unsigned int n_write = min(writecnt, BUF_SIZE - 1); + msg_pspew("writing %d-byte packet\n", n_write); + + buf[0] = BIT_BYTE | (uint8_t)n_write; + for (i = 0; i < n_write; i++) { + buf[i+1] = reverse(writearr[i]); + } + if (ftdi_write_data(&ftdic, buf, n_write + 1) < 0) { + msg_perr("USB-Blaster write failed\n"); + return -1; + } + + writearr += n_write; + writecnt -= n_write; + } + return 0; +} + +static int send_read(unsigned int readcnt, unsigned char *readarr) +{ + int i; + unsigned int n_read; + uint8_t buf[BUF_SIZE]; + memset(buf, 0, sizeof(buf)); + + n_read = readcnt; + while (n_read) { + unsigned int payload_size = min(n_read, BUF_SIZE - 1); + msg_pspew("reading %d-byte packet\n", payload_size); + + buf[0] = BIT_BYTE | BIT_READ | (uint8_t)payload_size; + if (ftdi_write_data(&ftdic, buf, payload_size + 1) < 0) { + msg_perr("USB-Blaster write failed\n"); + return -1; + } + n_read -= payload_size; + }; + + n_read = readcnt; + while (n_read) { + int ret = ftdi_read_data(&ftdic, readarr, n_read); + if (ret < 0) { + msg_perr("USB-Blaster read failed\n"); + return -1; + } + for (i = 0; i < ret; i++) { + readarr[i] = reverse(readarr[i]); + } + n_read -= ret; + readarr += ret; + } + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int usbblaster_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + uint8_t cmd; + int ret = 0; + + cmd = BIT_LED; // asserts /CS + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("USB-Blaster enable chip select failed\n"); + ret = -1; + } + + if (!ret && writecnt) + ret = send_write(writecnt, writearr); + + if (!ret && readcnt) + ret = send_read(readcnt, readarr); + + cmd = BIT_CS; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("USB-Blaster disable chip select failed\n"); + ret = -1; + } + + return ret; +} + + +static const struct spi_programmer spi_programmer_usbblaster = { + .type = SPI_CONTROLLER_USBBLASTER, + .max_data_read = 256, + .max_data_write = 256, + .command = usbblaster_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +#endif -- 1.8.1.1

2 1

P5KPL-AM log
by blondquirk 18 Mar '13

18 Mar '13

2 2

Supermicro X9SCM-F - not supported yet?
by Alexander List 15 Mar '13

15 Mar '13

Hi, according to your website my board (Supermicro X9SCM-F) is not supported yet. http://www.supermicro.com/products/motherboard/xeon/c202_c204/x9scm-f.cfm I wonder what's faster - me figuring out how to get a PXE boot environment up and running here at home so I can boot a FreeDOS HDD image via the net, or me helping you support this type of board ;) output of flashrom -V attached, as well as dmidecode. cheers Alex PS: You can find me on freenode as #alexlist - around the ubuntu channels ... just ping me if I can help you support this board.

2 3

P8Z68-V LE log
by blondquirk 15 Mar '13

15 Mar '13

2 1

testing DELL Dimension 4100
by Bertho Grandpied 13 Mar '13

13 Mar '13

Testing Dell Dimension 4100 : Pentium III and Intel 815 (82815 + 82801BA, ICH2) based desktop machine from ca yr 2000. This chipset should be supported IIUC, but flash chip is not detected :( Flashrom was run under MS-DOS (log appended) - notice how I had to specify the "not-a-laptop" override because of insufficient DMI tables. Please notice also the "warning" about being unable to set Bios Control at 0x4e : thus the question arises, is that Intel chipset variant supported or is it not ? Additionally I ran 'Linux/sensors-detct' FWIW : "probing for Super-I/O at 0x2e/2f", "SMSC LPC47M10x/112/13x" fan sensors were found. Any further software probe I can try before opening up the box in the hope of finding what BIOS chip was used by visual inspection ? Regards... __________________________________________________________________ flashrom v0.9.6.1-r1624 on MS-DOS 7 (i686) flashrom was built with libpci 3.1.5, GCC 4.4.4, little endian Command line (7 args): c:/flashrom/flashrom.exe -p internal:laptop=this_is_not_a_laptop -V -r DELL.BIN -o READ.LOG Calibrating delay loop... OS timer resolution is 50000 usecs, 486M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 200000 myus = 270000 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Computer Corporation " DMI string system-product-name: "XPS-Z " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation " DMI string baseboard-product-name: "D815EEA " DMI string baseboard-version: "AAA10383-402 " DMI string chassis-type: "Unknown" DMI chassis-type is not specific enough. ======================================================================== WARNING! You may be running flashrom on an unsupported laptop.(....) You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "Intel ICH2" with PCI ID 8086:2440. Enabling flash write... BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled WARNING: Setting Bios Control at 0x4e from 0x02 to 0x03 on ICH2 failed. New value is 0x02. FAILED! The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xb2, id2 0xf1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x93, id2 0x26, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:1f:0 reg 0x4e _________________________________________________________________ -- Czerno

3 11

Re: [flashrom] Intel C602 support
by Stefan Tauner 13 Mar '13

13 Mar '13

On Mon, 6 Aug 2012 12:07:47 -0700 Greg Schardt <gschardt(a)ddn.com> wrote: > Can you explain why doing a read operation failed? I expected that reads would work and writes would fail. each region can have 4 different access states: read/write, read-only, write-only (never seen in practice), locked (neither read nor write allowed) (see FREG in the public datasheets for any newer intel southbridge >ICH8). flashrom disables writes by default if it detects locked or read-only regions as a safety measurement and still allows reads because they can not lead to the same severe damage. in case of locked regions reads of addresses inside those regions will of course fail. there are some patches available that are not merged yet that allow to specify the addresses to be read/written, which allow to read/write the readable/writable address ranges. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

[PATCH] Add version to manpage (plus other stuff)
by Joerg Mayer 09 Mar '13

09 Mar '13

Add version and description to manpage, make extension configurable. Remove some trailing whitespace from manpage. Note1: This requires sed during the build process. Is this acceptable? Note2: Apply patch, then rename flashrom.8 to flashrom.man.in Signed-off-by: Joerg Mayer <jmayer(a)loplof.de> Index: flashrom.8 =================================================================== --- flashrom.8 (revision 1633) +++ flashrom.8 (working copy) @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Dec, 2012" +.TH FLASHROM @MANEXT@ "@DATE@" "@VERSION@" "A flash programmer" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -128,7 +128,7 @@ .sp .B " flashrom \-p prog \-\-layout rom.layout \-\-image normal \-w some.rom" .sp -To update only the images named +To update only the images named .BR "normal " "and " "fallback" ", run:" .sp .B " flashrom \-p prog \-l rom.layout \-i normal -i fallback \-w some.rom" @@ -694,11 +694,11 @@ .BR "pony_spi " programmer The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is specified using the mandatory -.B dev +.B dev parameter. The adapter type is selectable between SI-Prog (used for SPI devices with PonyProg 2000) or a custom made serial bitbanging programmer named "serbang". The optional -.B type +.B type parameter accepts the values "si_prog" (default) or "serbang". .sp Information about the SI-Prog adapter can be found at @@ -724,7 +724,7 @@ .B cprom or .B s3 -for the configuration ROM and +for the configuration ROM and .B bprom or .B bios @@ -733,7 +733,7 @@ you want to use with the .B pci= parameter as explained in the -.B nic3com et al.\& +.B nic3com et al.\& section above. .sp More information about the hardware is available at Index: Makefile =================================================================== --- Makefile (revision 1633) +++ Makefile (working copy) @@ -35,6 +35,7 @@ DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man +MANEXT ?= 8 CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . AR ?= ar @@ -318,6 +319,7 @@ RELEASE := 0.9.6.1 VERSION := $(RELEASE)-r$(SVNVERSION) RELEASENAME ?= $(VERSION) +DATE := Dec 2012 SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' @@ -581,7 +583,7 @@ else ifeq ($(TARGET_OS), Darwin) # DirectHW framework can be found in the DirectHW library. -PCILIBS += -framework IOKit -framework DirectHW +PCILIBS += -framework IOKit -framework DirectHW else endif endif @@ -608,7 +610,7 @@ LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) -all: hwlibs features $(PROGRAM)$(EXEC_SUFFIX) +all: hwlibs features $(PROGRAM)$(EXEC_SUFFIX) $(PROGRAM).$(MANEXT) ifeq ($(ARCH), x86) @+$(MAKE) -C util/ich_descriptors_tool/ TARGET_OS=$(TARGET_OS) EXEC_SUFFIX=$(EXEC_SUFFIX) endif @@ -632,7 +634,7 @@ # This includes all frontends and libflashrom. # We don't use EXEC_SUFFIX here because we want to clean everything. clean: - rm -f $(PROGRAM) $(PROGRAM).exe libflashrom.a *.o *.d + rm -f $(PROGRAM) $(PROGRAM).exe libflashrom.a *.o *.d $(PROGRAM).$(MANEXT) @+$(MAKE) -C util/ich_descriptors_tool/ clean distclean: clean @@ -826,11 +828,14 @@ @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) +flashrom.$(MANEXT): flashrom.man.in + sed -e "s#@MANEXT@#$(MANEXT)#g" -e "s#@VERSION@#$(VERSION)#g" -e "s#@DATE@#$(DATE)#g" <$< >$@ + install: $(PROGRAM)$(EXEC_SUFFIX) mkdir -p $(DESTDIR)$(PREFIX)/sbin - mkdir -p $(DESTDIR)$(MANDIR)/man8 + mkdir -p $(DESTDIR)$(MANDIR)/man$(MANEXT) $(INSTALL) -m 0755 $(PROGRAM)$(EXEC_SUFFIX) $(DESTDIR)$(PREFIX)/sbin - $(INSTALL) -m 0644 $(PROGRAM).8 $(DESTDIR)$(MANDIR)/man8 + $(INSTALL) -m 0644 $(PROGRAM).$(MANEXT) $(DESTDIR)$(MANDIR)/man$(MANEXT) export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) -- Joerg Mayer <jmayer(a)loplof.de> We are stuck with technology when what we really want is just stuff that works. Some say that should read Microsoft instead of technology.

2 2

wiki patches 6.0?
by Stefan Tauner 07 Mar '13

07 Mar '13

This is actually not about the wiki, but about the programmers. now that we have combined usb and pci device entries and put them together in a union with a char *note, i wonder why we have the union at all. the note might be very handy for normal programmers too (e.g. nvidia does not support writing, but this is not documented prominently...). It would also get rid of the annoying non-anonymous union... :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[PATCH] Add pinout for ByteBlaster to rayer_spi.c.
by mmcx＠mail.ru 05 Mar '13

05 Mar '13

Add pinout for ByteBlaster to rayer_spi.c. Signed-off-by: Maksim Kuleshov <mmcx(a)mail.ru> --- rayer_spi.c | 91 +++++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 30 deletions(-) diff --git a/rayer_spi.c b/rayer_spi.c index b312610..488b555 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -35,13 +35,28 @@ #include <string.h> #include "flash.h" #include "programmer.h" #include "hwaccess.h" -enum rayer_type { - TYPE_RAYER, - TYPE_XILINX_DLC5, + +static void rayer_byteblaster_preinit(void *); +static int rayer_byteblaster_shutdown(void *); + +static struct s_rayer_pinout { + const char * name; + const char * description; + int cs_bit; + int sck_bit; + int mosi_bit; + int miso_bit; + void (*preinit)(void *); + int (*shutdown)(void *); +} rayer_pinouts [] = { + {"rayer","RayeR SPIPGM",5,6,7,6}, + {"xilinx","Xilinx Parallel Cable III (DLC 5)",2,1,0,4}, + {"byteblaster","Altera ByteBlaster",1,0,6,7,rayer_byteblaster_preinit,rayer_byteblaster_shutdown}, + {0}, }; /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. * Default settings are for the RayeR hardware. @@ -81,11 +96,11 @@ static void rayer_bitbang_set_mosi(int val) static int rayer_bitbang_get_miso(void) { uint8_t tmp; - tmp = INB(lpt_iobase + 1); + tmp = INB(lpt_iobase + 1) ^ 0x80;//bit.7 inverted tmp = (tmp >> rayer_miso_bit) & 0x1; return tmp; } static const struct bitbang_spi_master bitbang_spi_master_rayer = { @@ -95,14 +110,17 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = { .set_mosi = rayer_bitbang_set_mosi, .get_miso = rayer_bitbang_get_miso, .half_period = 0, }; + +static void (*rayer_preinit)(void*) =NULL; +static void * rayer_preinit_data=NULL; + int rayer_spi_init(void) { char *arg = NULL; - enum rayer_type rayer_type = TYPE_RAYER; /* Non-default port requested? */ arg = extract_programmer_param("iobase"); if (arg) { char *endptr = NULL; @@ -136,51 +154,64 @@ int rayer_spi_init(void) msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n", lpt_iobase); arg = extract_programmer_param("type"); if (arg) { - if (!strcasecmp(arg, "rayer")) { - rayer_type = TYPE_RAYER; - } else if (!strcasecmp(arg, "xilinx")) { - rayer_type = TYPE_XILINX_DLC5; - } else { + struct s_rayer_pinout *p = rayer_pinouts; + for (; p->name; ++p) { + if (! strcasecmp (arg, p->name)) { + break; + } + } + if(! p->name) { msg_perr("Error: Invalid device type specified.\n"); free(arg); return 1; } - } - free(arg); - switch (rayer_type) { - case TYPE_RAYER: - msg_pdbg("Using RayeR SPIPGM pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 5; - rayer_sck_bit = 6; - rayer_mosi_bit = 7; - /* Bits for slave->master direction */ - rayer_miso_bit = 6; - break; - case TYPE_XILINX_DLC5: - msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 2; - rayer_sck_bit = 1; - rayer_mosi_bit = 0; - /* Bits for slave->master direction */ - rayer_miso_bit = 4; + msg_pinfo("Using %s pinout.\n", p->description); + rayer_cs_bit = p->cs_bit; + rayer_sck_bit = p->sck_bit; + rayer_mosi_bit = p->mosi_bit; + rayer_miso_bit = p->miso_bit; + + if(p -> preinit){ + rayer_preinit = p -> preinit; + rayer_preinit_data = p; + } + + if(p -> shutdown){ + register_shutdown(p -> shutdown, (void*)p); + } + + free(arg); } if (rget_io_perms()) return 1; /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); + if(rayer_preinit){ + rayer_preinit(rayer_preinit_data); + } + if (bitbang_spi_init(&bitbang_spi_master_rayer)) return 1; return 0; } +static void rayer_byteblaster_preinit(void * data){ + msg_pdbg("byteblaster_init\n"); + OUTB(2, lpt_iobase + 2 );//clear #EN signal +} + +static int rayer_byteblaster_shutdown(void * data){ + msg_pdbg("byteblaster_shutdown\n"); + OUTB(0, lpt_iobase + 2 );//set #EN signal + return 0; +} + #else #error PCI port I/O access is not supported on this architecture yet. #endif -- 1.7.10.4

2 3

[PATCH] Add M25P20-old
by Kyösti Mälkki 04 Mar '13

04 Mar '13

This older revision (?) of M25P20 chip was not detected correctly. Similar case was with M25P40 detection. I have misplaced my narrow SOIC-8 adapter and cannot reproduce the test logs at the moment. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- flashchips.c | 27 +++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 28 insertions(+) diff --git a/flashchips.c b/flashchips.c index d4ab1be..7321e6c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8327,6 +8327,33 @@ const struct flashchip flashchips[] = { }, { + .vendor = "ST", + .name = "M25P20-old", + .bustype = BUS_SPI, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P20_RES, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_res1, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "ST", /* Numonyx */ .name = "M25P40", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 1a0696f..c4c72ba 100644 --- a/flashchips.h +++ b/flashchips.h @@ -572,6 +572,7 @@ #define ST_M25P10A 0x2011 #define ST_M25P10_RES 0x10 /* Same code as M25P05. */ #define ST_M25P20 0x2012 +#define ST_M25P20_RES 0x11 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 #define ST_M25P80 0x2014 -- 1.8.1.1

2 1

Re: [flashrom] patch Dynamic list Multiple chips
by Stefan Tauner 01 Mar '13

01 Mar '13

On Thu, 28 Feb 2013 16:21:56 +0400 Николай Николаев <evrinoma(a)gmail.com> wrote: > If we detected Multiple flash chips than > we can easy save all chips in dynamic list - pflashes. > and we will not have a restrictions with number chips > > TODO: > Sort Dynamic List by Volage. This chips has a equivalent the model_id > but can have a different parameters like a name voltage probe function > ... > Probing > ... > Resolving chips names Hi, thanks for the patch. Please do not leave the previous code as comments in the patch. This makes it very unreadable and not directly applicable. I have not looked at the changes in detail, but I did also not like the limitation, so in general I like the idea. I would like to continue to use "flashes" as the name of the collection though (why the change?). Eventually I would also like to see a general list implementation in flashrom, maybe similar to something in the Linux kernel, because it would really make life easier in some cases (like this one). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] main board in SuperMicro FatTwin
by Stefan Tauner 28 Feb '13

28 Feb '13

On Tue, 26 Feb 2013 20:01:47 -0800 Tucker <junk(a)gmail.com> wrote: > The main board of in the SuperMicro fatTwin is listed as an X9SCE. It's > not listed on your Wiki as being known yet. Attached you'll find the > verbose log from flashrom. > x9sce <https://docs.google.com/file/d/0By--6GXzLOzWZFc4WnF0SW5kNms/edit> While this one is ok, we (at least me, and there is no one else doing it :) will not process any logs stored on dubious webservers in the future. Also, please do not send mails via such honey pot mail addresses because it is quite likely that we reply and get "caught" in them by mistake. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

patch Dynamic list Multiple chips
by Николай Николаев 28 Feb '13

28 Feb '13

-- With best regards Nikolay Nikolaev С Уважением Николаев Николай

1 0

main board in SuperMicro FatTwin
by Tucker 27 Feb '13

27 Feb '13

The main board of in the SuperMicro fatTwin is listed as an X9SCE. It's not listed on your Wiki as being known yet. Attached you'll find the verbose log from flashrom. x9sce <https://docs.google.com/file/d/0By--6GXzLOzWZFc4WnF0SW5kNms/edit> -- --tucker

1 0

flashrom first use....
by Francisco Otero Martínez de Al 27 Feb '13

27 Feb '13

I didn't flash nothing yet. Please advise me if it is safe to load coreboot on this motherboard. Thank you. Francisco Otero

2 1

Report: Gigabyte B75M-D3H F12 read
by dpcimanager＠users.sourceforge.net 26 Feb '13

26 Feb '13

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r /var/folders/fc/5fxhqmg96b7b45dsct9r7vk80000gn/T/DPCIn6oFmq.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 420M loops per second, 10 myus = 9 us, 100 myus = 97 us, 1000 myus = 994 us, 10000 myus = 9589 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "B75M-D3H" DMI string baseboard-version: "x.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8728 on port 0x2e Found chipset "Intel B75" with PCI ID 8086:1e49. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x005367ac (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. 0x5C: 0x04ff0001 FREG2: Management Engine region (0x00001000-0x004fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0000 FLREG2 0x04ff0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00000000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x004fffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw SPI Read Configuration: prefetching enabled, caching enabled, OK. Super I/O ID 0x8728 is not on the list of flash capable controllers. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25F512, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512A, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25F1024(A), 128 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F2048, 256 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F4096, 512 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080(A), 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xc7, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xc7, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xc7, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xf9, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xa6, id2 0x45, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xc7, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xa6, id2 0x45, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xc7, id2 0x46, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xd8, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L6405" (8192 kB, SPI). Block protection is disabled. Reading flash... done. Restoring MMIO space at 0x10d65d8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

Report: BIOSTAR H61MH 4.6.4 read
by dpcimanager＠users.sourceforge.net 26 Feb '13

26 Feb '13

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): /var/folders/xj/73b1fsj16m71h44gl8gsh1f00000gn/T/wzQL.HV75QG/DPCIManager.app/Contents/MacOS/flashrom -VV -r /Volumes/Seagate Backup Plus Drive/BIOS/BIOSTAR H61MH 4.6.4.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 437M loops per second, 10 myus = 9 us, 100 myus = 110 us, 1000 myus = 1071 us, 10000 myus = 10738 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "BIOSTAR Group" DMI string system-product-name: "H61MH" DMI string system-version: "6.0" DMI string baseboard-manufacturer: "BIOSTAR Group" DMI string baseboard-product-name: "H61MH" DMI string baseboard-version: "6.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8728 on port 0x2e Found chipset "Intel H61" with PCI ID 8086:1c5c. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc04: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x0021a77a (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0200 FREG1: BIOS region (0x00200000-0x003fffff) is read-write. 0x5C: 0x01ff0001 FREG2: Warning: Management Engine region (0x00001000-0x001fffff) is locked. 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00000fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300023 FLILL 0x00000000 --- Details --- Component 1 density: 4 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x03ff0200 FLREG2 0x01ff0001 FLREG3 0x00000fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00200000 - 0x003fffff Region 2 (ME ) 0x00001000 - 0x001fffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw SPI Read Configuration: prefetching disabled, caching enabled, OK. Super I/O ID 0x8728 is not on the list of flash capable controllers. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25F512, 64 kB: program_opcodes: preop=5006 optype=460b opmenu=05150302c79f0190 on-the-fly OPCODE (0x15) re-programmed, op-pos=2 probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Found Eon flash chip "EN25Q32(A/B)" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Numonyx N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0x1c, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0x1c, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Unknown SFDP-capable chip, 0 kB: program_opcodes: preop=5006 optype=462b opmenu=055a0302c79f0190 on-the-fly OPCODE (0x5A) re-programmed, op-pos=2 Signature = 0xffffffff (should be 0x50444653) No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x1c, id2 0x15 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x19, id2 0xf7, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x19, id2 0xf7, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x19, id2 0xf7, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x19, id2 0xf7, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x19, id2 0xf7, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x56, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Found Eon flash chip "EN25Q32(A/B)" (4096 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). === This flash part has status UNTESTED for operations: READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Block protection is disabled. Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x10913b8a0 Restoring MMIO space at 0x10913b89c Restoring MMIO space at 0x10913b898 Restoring MMIO space at 0x10913b896 Restoring MMIO space at 0x10913b894 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

Rayer_SPI and xilinx buffered dlc5 cable
by Andrew Tarabaras 26 Feb '13

26 Feb '13

Hi, Just a heads up that the rayer_spi module wont work with a buffered xilinx DLC cable. There is a pull down buffer in the MISO ( Data In ) line which is enabled when pin 6 of the parallel port is pulled low. I dont have time to be submitting patches, fix it or not I dont mind. These are the changes I made. Global var static int rayer_pulldown_bit = 4; in rayer_spi_init() after rget_io_perms(); val = 1; lpt_outbyte &= ~(1 << rayer_pullup_bit); lpt_outbyte |= (val << rayer_pullup_bit); OUTB(lpt_outbyte, lpt_iobase); Cheers, hope it will help stop someone else spending hours debugging something that doesn't work.

1 0

ASUS C60M1-I Write Success
by Justin Chevrier 25 Feb '13

25 Feb '13

Hey Guys, Another report; this one successful going from BIOS 0205 to 0305. Executed an erase before writing the new BIOS. Original MAC address of the onboard LAN adapter was lost after upgrade. Justin

1 0

[PATCH 3/3] Allow physmap_common() to round address ranges to page boundaries.
by Stefan Tauner 23 Feb '13

23 Feb '13

Automatically round address ranges requested from rphysmap() to page boundaries. Other physmap() variants were not changed so this is safe regarding unmapping. I had also to shorten the readbility defines for the physmap_common parameters to make the calls fit a single line. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- physmap.c | 61 ++++++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/physmap.c b/physmap.c index 3811824..4f82d0f 100644 --- a/physmap.c +++ b/physmap.c @@ -218,12 +218,35 @@ void physunmap(void *virt_addr, size_t len) } #endif -#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 -#define PHYSMAP_RW 0 -#define PHYSMAP_RO 1 -#define PHYSMAP_NOCLEANUP 0 -#define PHYSMAP_CLEANUP 1 +#define PHYSM_NOFAIL 0 +#define PHYSM_MAYFAIL 1 +#define PHYSM_RW 0 +#define PHYSM_RO 1 +#define PHYSM_NOCLEANUP 0 +#define PHYSM_CLEANUP 1 +#define PHYSM_EXACT 0 +#define PHYSM_ROUND 1 + +/* Round start to nearest page boundary below and set len so that the resulting + * address range ends at the lowest possible page boundary where the original + * address range is still entirely contained. It returns the difference between + * the rounded start address and the original start address. */ +static uintptr_t round_to_page_boundaries(uintptr_t *start, size_t *len) +{ + uintptr_t page_size = getpagesize(); + uintptr_t page_mask = ~(page_size-1); + uintptr_t end = *start + *len; + uintptr_t old_start = *start; + msg_gspew("page_size=%" PRIxPTR "\n", page_size); + msg_gspew("pre-rounding: start=0x%0*" PRIxPTR ", len=0x%0zx, end=0x%0*" PRIxPTR "\n", + PRIxPTR_WIDTH, *start, *len, PRIxPTR_WIDTH, end); + *start = *start & page_mask; + end = (end + page_size - 1) & page_mask; + *len = end - *start; + msg_gspew("post-rounding: start=0x%0*" PRIxPTR ", len=0x%0zx, end=0x%0*" PRIxPTR "\n", + PRIxPTR_WIDTH, *start, *len, PRIxPTR_WIDTH, *start + *len); + return old_start - *start; +} struct undo_physmap_data { void *virt_addr; @@ -243,24 +266,18 @@ static int undo_physmap(void *data) } static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool mayfail, - bool readonly, bool autocleanup) + bool readonly, bool autocleanup, bool round) { void *virt_addr; + uintptr_t offset = 0; if (len == 0) { msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr); return ERROR_PTR; } - if ((getpagesize() - 1) & len) { - msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", - descr, phys_addr, (unsigned long)len); - } - - if ((getpagesize() - 1) & phys_addr) { - msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", - descr, (unsigned long)len, phys_addr); - } + if (round) + offset = round_to_page_boundaries(&phys_addr, &len); if (readonly) virt_addr = sys_physmap_ro_cached(phys_addr, len); @@ -286,7 +303,9 @@ static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, "and reboot, or reboot into\n" "single user mode.\n"); #endif - if (!mayfail) + if (mayfail) + return ERROR_PTR; + else exit(3); } @@ -305,7 +324,7 @@ static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, } } - return virt_addr; + return virt_addr + offset; unmap_out: physunmap(virt_addr, len); if (!mayfail) @@ -315,17 +334,17 @@ unmap_out: void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW, PHYSMAP_NOCLEANUP); + return physmap_common(descr, phys_addr, len, PHYSM_NOFAIL, PHYSM_RW, PHYSM_NOCLEANUP, PHYSM_EXACT); } void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW, PHYSMAP_CLEANUP); + return physmap_common(descr, phys_addr, len, PHYSM_NOFAIL, PHYSM_RW, PHYSM_CLEANUP, PHYSM_ROUND); } void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO, PHYSMAP_NOCLEANUP); + return physmap_common(descr, phys_addr, len, PHYSM_MAYFAIL, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } #if defined(__i386__) || defined(__x86_64__) -- Kind regards, Stefan Tauner

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[PATCH 2/3] uintptr_t-ify physmap.c.
by Stefan Tauner 23 Feb '13

23 Feb '13

unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in physmap.c where applicable. This should be done in a lot of other places in flashrom too, but that's a huge pile of work and we better start it with a small step than never (which is the forseeable alternative ;) This patch also changes the display width of all address values in physmap.c to 16/8 hex characters depending on the architecture. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- physmap.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/physmap.c b/physmap.c index 40dfa50..3811824 100644 --- a/physmap.c +++ b/physmap.c @@ -20,6 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <inttypes.h> #include <unistd.h> #include <stdbool.h> #include <stdio.h> @@ -35,6 +36,8 @@ #include <errno.h> #endif +#define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) + #ifdef __DJGPP__ #include <dpmi.h> #include <sys/nearptr.h> @@ -43,7 +46,7 @@ static void *realmem_map; -static void *map_first_meg(unsigned long phys_addr, size_t len) +static void *map_first_meg(uintptr_t phys_addr, size_t len) { if (realmem_map) return realmem_map + phys_addr; @@ -62,7 +65,7 @@ static void *map_first_meg(unsigned long phys_addr, size_t len) return realmem_map + phys_addr; } -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { int ret; __dpmi_meminfo mi; @@ -110,7 +113,7 @@ void physunmap(void *virt_addr, size_t len) #define MEM_DEV "" -void *sys_physmap(unsigned long phys_addr, size_t len) +void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } @@ -134,7 +137,7 @@ void cleanup_cpu_msr(void) #define MEM_DEV "DirectHW" -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { /* The short form of ?: is a GNU extension. * FIXME: map_physical returns NULL both for errors and for success @@ -166,7 +169,7 @@ static int fd_mem = -1; static int fd_mem_cached = -1; /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ -static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) +static void *sys_physmap_rw_uncached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -186,7 +189,7 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* For reading DMI/coreboot/whatever tables. We should never write, and we * do not care about caching. */ -static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +static void *sys_physmap_ro_cached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -239,14 +242,13 @@ static int undo_physmap(void *data) return 0; } -static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, +static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool mayfail, bool readonly, bool autocleanup) { void *virt_addr; if (len == 0) { - msg_pspew("Not mapping %s, zero size at 0x%08lx.\n", - descr, phys_addr); + msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr); return ERROR_PTR; } @@ -268,8 +270,8 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, size_t l if (ERROR_PTR == virt_addr) { if (NULL == descr) descr = "memory"; - msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, - (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%0zx bytes at 0x%0*" PRIxPTR "\n", + descr, len, PRIxPTR_WIDTH, phys_addr); perror(MEM_DEV " mmap failed"); #ifdef __linux__ if (EINVAL == errno) { @@ -311,17 +313,17 @@ unmap_out: return ERROR_PTR; } -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW, PHYSMAP_NOCLEANUP); } -void *rphysmap(const char *descr, unsigned long phys_addr, size_t len) +void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW, PHYSMAP_CLEANUP); } -void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO, PHYSMAP_NOCLEANUP); } -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH 3/5] Automatically unmap physmap()s.
by Carl-Daniel Hailfinger 23 Feb '13

23 Feb '13

Am 01.01.2013 18:29 schrieb Stefan Tauner: > Similarly to the previous PCI self-clean up patch this one allows to get rid > of a huge number of programmer shutdown functions and makes introducing > bugs harder. It adds a new function physmap_autocleanup() that takes > care of unmapping at shutdown. Callers are changed where it makes sense. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Good work! The individual driver conversions were checked thoroughly and seem to be OK. With the comments addressed, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Can you please change the name of physmap_autocleanup to rphysmap? That would be consistent with rmmio_write* and rpci_write* and be shorter as well (fixing some 112 columns limit issues). > diff --git a/it85spi.c b/it85spi.c > index 0b074eb..b778436 100644 > --- a/it85spi.c > +++ b/it85spi.c > @@ -262,6 +262,9 @@ static int it85xx_spi_common_init(struct superio s) > * Major TODO here, and it will be a lot of work. > */ > base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); > + if (base == ERROR_PTR) I somehow doubt that this really compiles. AFAICS you might not have noticed the type mismatch problem because of #if guards. > + return 1; > + > msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, > (unsigned int)base); > ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ > diff --git a/nicintel.c b/nicintel.c > index 8481915..5463af2 100644 > --- a/nicintel.c > +++ b/nicintel.c > @@ -81,19 +74,15 @@ int nicintel_init(void) > */ > addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); > > - nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); > + nicintel_bar = physmap_autocleanup("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); > if (nicintel_bar == ERROR_PTR) > - goto error_out_unmap; > + return 1; > > /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */ > addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0); > /* FIXME: This is not an aligned mapping. Use 4k? */ > - nicintel_control_bar = physmap("Intel NIC control/status reg", > - addr, NICINTEL_CONTROL_MEMMAP_SIZE); > + nicintel_control_bar = physmap_autocleanup("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); 112 column limit... not a problem with rphysmap. > if (nicintel_control_bar == ERROR_PTR) > - goto error_out; > - > - if (register_shutdown(nicintel_shutdown, NULL)) > return 1; > > /* FIXME: This register is pretty undocumented in all publicly available > diff --git a/physmap.c b/physmap.c > index 5aa9874..a9445d5 100644 > --- a/physmap.c > +++ b/physmap.c > @@ -21,6 +21,7 @@ > */ > > #include <unistd.h> > +#include <stdbool.h> Note: stdbool.h is only available in C99 compilers, which means this won't ever compile with MSVC. I don't really have a strong preference either way (and we use mingw/cygwin gcc for win* targets anyway). > #include <stdio.h> > #include <stdlib.h> > #include <string.h> > @@ -214,13 +215,25 @@ void physunmap(void *virt_addr, size_t len) > } > #endif > > -#define PHYSMAP_NOFAIL 0 > -#define PHYSMAP_MAYFAIL 1 > -#define PHYSMAP_RW 0 > -#define PHYSMAP_RO 1 IMHO those #defines really helped readability. You can replace 0 and 1 by false/true if you want, but please keep the #defines. > +struct physmap_stutdown_data { Maybe rename to undo_physmap_data for consistency with undo_pci_write_data. > + void *addr; Use virt_addr to make it obvious that this is not a physical address, but the address where this was mapped into the address space of the flashrom process? > + size_t len; > +}; > > -static void *physmap_common(const char *descr, unsigned long phys_addr, > - size_t len, int mayfail, int readonly) > +static int physmap_shutdown(void *data) Rename to undo_physmap for consistency with undo_pci_write? > +{ > + if (data == NULL) { > + msg_perr("%s: tried to shutdown without valid data!\n", __func__); > + return 1; > + } > + struct physmap_stutdown_data *d = data; Not all compilers support defining a new variable after code. Please move the line above to the head of the function. > + physunmap(d->addr, d->len); > + free(data); > + return 0; > +} > + > +static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, > + bool readonly, bool autocleanup) > { > void *virt_addr; > > @@ -268,19 +281,40 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, > exit(3); > } > > + if (autocleanup) { > + struct physmap_stutdown_data *d = malloc(sizeof(struct physmap_stutdown_data)); I wonder if that malloc should be moved to the start of physmap_common. It would detect OOM earlier, before we do any mapping. > + if (d == NULL) { > + msg_perr("%s: Out of memory!\n", __func__); > + goto unmap_out; > + } > + > + d->addr = virt_addr; > + d->len = len; > + if (register_shutdown(physmap_shutdown, d) != 0) { > + msg_perr("%s: Could not register shutdown function!\n", __func__); > + goto unmap_out; > + } > + } > + > return virt_addr; > +unmap_out: > + physunmap(virt_addr, len); > + return ERROR_PTR; > } > > void *physmap(const char *descr, unsigned long phys_addr, size_t len) > { > - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, > - PHYSMAP_RW); > + return physmap_common(descr, phys_addr, len, false, false, false); I really liked the #defines here because they increased readability. > +} > + > +void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len) > +{ > + return physmap_common(descr, phys_addr, len, false, false, true); > } > > void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) > { > - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, > - PHYSMAP_RO); > + return physmap_common(descr, phys_addr, len, true, true, false); > } > > #if defined(__i386__) || defined(__x86_64__) Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [TESTED] Eon flash chip "EN25Q64" (8192 kB, SPI) on rayer_spi.
by Stefan Tauner 22 Feb '13

22 Feb '13

On Fri, 22 Feb 2013 18:52:05 -0300 Anderson Vulczak <andi(a)andi.com.br> wrote: > Just tested this EPROM and it's writing, reading, erasing great. Thanks for your report, but it was already marked as tested after this: http://www.flashrom.org/pipermail/flashrom/2013-January/010466.html -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Compaq Evo D510 SFF - Erase Failed
by Justin Chevrier 22 Feb '13

22 Feb '13

Hi Guys, Attached are logs from a failed attempted erase of the flash rom on the system listed in the subject. I was able to verify the flash against the backup I had taken and the system was able to successfully reboot, so it appears no changes were made. It appears this system is using a nonstandard chassis type ("Space-saving") and the: "laptop=this_is_not_a_laptop" is required for Flashrom to interact with the system. HP doesn't specify any particular process (jumper, setting in BIOS) required to update the BIOS on this system (that I could find). Direct link to BIOS: ftp://ftp.hp.com/pub/softpaq/sp23001-23500/sp23350.exe Downloaded file can be extracted via 7zip, then the resulting ROM.CAB file can be extracted as well resulting in 'Rom.bin' that matches the size of the chip. 7z x sp23350.exe 7z x ROM.CAB Thanks, Justin

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[TESTED] Eon flash chip "EN25Q64" (8192 kB, SPI) on rayer_spi.
by Anderson Vulczak 22 Feb '13

22 Feb '13

Hello, Just tested this EPROM and it's writing, reading, erasing great. Thanks, and Best Regards, root@server:~# flashrom -p rayer_spi -w binary.bin flashrom v0.9.5.2-r1517 on Linux 3.2.0-37-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Eon flash chip "EN25Q64" (8192 kB, SPI) on rayer_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED.

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[PATCH] Add utility to print all chip names in flashchips.h that are not in flashchips.c.
by Stefan Tauner 22 Feb '13

22 Feb '13

This allows to list yet unsupported chips easily. First it tries to find the directory containing the files, then it uses sed to extract the macro names of chips from flashchips.h, greps for them in flashchips.c and prints it if it is not found. If verbose mode is activated by giving at least one additional parameter it prints the comment following the macro definition too. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- util/list_yet_unsupported_chips.sh | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100755 util/list_yet_unsupported_chips.sh diff --git a/util/list_yet_unsupported_chips.sh b/util/list_yet_unsupported_chips.sh new file mode 100755 index 0000000..2ed71e6 --- /dev/null +++ b/util/list_yet_unsupported_chips.sh @@ -0,0 +1,22 @@ +#!/bin/sh + +path="$(dirname $(readlink -f $0))/.." +if [ ! -e "$path/flashchips.c" -o ! -e "$path/flashchips.h" ]; then + echo "Warning: could not calculate flashchips.[ch]'s directory. Trying current..." + path="." + if [ ! -e "$path/flashchips.c" -o ! -e "$path/flashchips.h" ]; then + echo "Nope, sorry!" + exit 1 + fi +fi + +chips=`sed -re '/#define [A-Z]/ !d' -e '/_ID\s/d' -e 's/\s*#define\s+([[:alnum:]_]+)\s+.*/\1/' $path/flashchips.h` +for c in $chips ; do + if ! grep "$c" "$path/flashchips.c" >/dev/null ; then + if [ -n "$1" ]; then + grep -o "$c.*" "$path/flashchips.h" + else + echo "$c" + fi + fi +done -- Kind regards, Stefan Tauner

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[PATCH] Add W25Q....W series.
by Stefan Tauner 22 Feb '13

22 Feb '13

- Use ".V" (and "_V" in macros) for 3.3V Winbond 25Q chips. Rename the existing chips and add a .voltage entry where it was missing. - Use ".W" (and "_W" in macros) for 1.8V Winbond 25Q chips. - Add a feature flag for QPI-enabled chips: FEATURE_QPI. - Add W25Q20.W, W25Q40.W, W25Q80.W, W25Q16.W, W25Q32.W, W25Q64.W. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flash.h | 1 + flashchips.c | 274 ++++++++++++++++++++++++++++++++++++++++++++++++++++++---- flashchips.h | 20 +++-- print.c | 26 +++--- 4 files changed, 287 insertions(+), 34 deletions(-) diff --git a/flash.h b/flash.h index a479286..b035330 100644 --- a/flash.h +++ b/flash.h @@ -99,6 +99,7 @@ enum write_granularity { #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_OTP (1 << 8) +#define FEATURE_QPI (1 << 9) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) struct flashctx; diff --git a/flashchips.c b/flashchips.c index d4ab1be..0e0a1ff 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9405,13 +9405,14 @@ const struct flashchip flashchips[] = { { .vendor = "Winbond", - .name = "W25Q80", + .name = "W25Q80.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q80, + .model_id = WINBOND_NEX_W25Q80_V, .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -9444,13 +9445,14 @@ const struct flashchip flashchips[] = { { .vendor = "Winbond", - .name = "W25Q16", + .name = "W25Q16.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q16, + .model_id = WINBOND_NEX_W25Q16_V, .total_size = 2048, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -9483,13 +9485,14 @@ const struct flashchip flashchips[] = { { .vendor = "Winbond", - .name = "W25Q32", + .name = "W25Q32.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q32, + .model_id = WINBOND_NEX_W25Q32_V, .total_size = 4096, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -9522,13 +9525,14 @@ const struct flashchip flashchips[] = { { .vendor = "Winbond", - .name = "W25Q64", + .name = "W25Q64.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q64, + .model_id = WINBOND_NEX_W25Q64_V, .total_size = 8192, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -9556,17 +9560,19 @@ const struct flashchip flashchips[] = { .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { .vendor = "Winbond", - .name = "W25Q128", + .name = "W25Q128.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25Q128, + .model_id = WINBOND_NEX_W25Q128_V, .total_size = 16384, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, @@ -9594,6 +9600,244 @@ const struct flashchip flashchips[] = { .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", + .name = "W25Q20.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q20_W, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q40.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q40_W, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q80.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q80_W, + .total_size = 1024, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q16.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q16_W, + .total_size = 2048, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q32.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_W, + .total_size = 4096, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + }, + + { + .vendor = "Winbond", + .name = "W25Q64.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q64_W, + .total_size = 8192, + .page_size = 256, + /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ }, { diff --git a/flashchips.h b/flashchips.h index 1a0696f..d705c32 100644 --- a/flashchips.h +++ b/flashchips.h @@ -649,12 +649,20 @@ #define WINBOND_NEX_W25X16 0x3015 #define WINBOND_NEX_W25X32 0x3016 #define WINBOND_NEX_W25X64 0x3017 -#define WINBOND_NEX_W25Q40 0x4013 -#define WINBOND_NEX_W25Q80 0x4014 -#define WINBOND_NEX_W25Q16 0x4015 -#define WINBOND_NEX_W25Q32 0x4016 -#define WINBOND_NEX_W25Q64 0x4017 -#define WINBOND_NEX_W25Q128 0x4018 +#define WINBOND_NEX_W25Q40_V 0x4013 /* W25Q40BV; W25Q40BL (2.3-3.6V) */ +#define WINBOND_NEX_W25Q80_V 0x4014 /* W25Q80BV */ +#define WINBOND_NEX_W25Q16_V 0x4015 /* W25Q16CV; W25Q16DV */ +#define WINBOND_NEX_W25Q32_V 0x4016 /* W25Q32BV; W25Q32FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ +#define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV */ +#define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ +#define WINBOND_NEX_W25Q40_W 0x5013 /* W25Q40BW */ +#define WINBOND_NEX_W25Q80_W 0x5014 /* W25Q80BW */ +#define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ +#define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ +#define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ +#define WINBOND_NEX_W25Q128_W 0x6018 /* (No W version known) W25Q128FV in QPI mode */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 diff --git a/print.c b/print.c index ecde90f..7d2e5a0 100644 --- a/print.c +++ b/print.c @@ -544,7 +544,7 @@ const struct board_info boards_known[] = { B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL), B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "K7S41", OK, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7S41GX", OK, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL), B("ASRock", "K7VT4A+", BAD, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%2b", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), @@ -683,16 +683,16 @@ const struct board_info boards_known[] = { B("ASUS", "P6T Deluxe V2", OK, "http://www.asus.com/Motherboards/Intel_Socket_1366/P6T_Deluxe_V2/", NULL), B("ASUS", "P7H57D-V EVO", OK, "http://www.asus.com/Motherboards/Intel_Socket_1156/P7H57DV_EVO/", NULL), B("ASUS", "P7H55-M LX", BAD, NULL, "flashrom works correctly, but GbE LAN is nonworking (probably due to a missing/bogus MAC address; see http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html and http://ubuntuforums.org/showthread.php?t=1534389 for a possible workaround)"), - B("ASUS", "P8B-E/4L", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASUS", "P8B WS", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASUS", "P8H61 PRO", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASUS", "P8H61-M LE/USB3", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8B-E/4L", BAD, NULL, "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8B WS", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H61 PRO", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H61-M LE/USB3", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H67-M PRO", BAD, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8P67 (rev. 3.1)", BAD, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASUS", "P8P67 LE", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8P67 LE", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8P67 PRO (rev. 3.0)", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8P67_PRO/", NULL), B("ASUS", "P8Z68-V", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), - B("ASUS", "P8Z68-V PRO", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8Z68-V PRO", BAD, NULL, "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO/GEN3", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V_PROGEN3/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), B("ASUS", "SABERTOOTH 990FX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX/", NULL), B("ASUS", "SABERTOOTH 990FX R2.0", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX_R20/", NULL), @@ -895,8 +895,8 @@ const struct board_info boards_known[] = { B("MSI", "MS-7596 (785GM-E51)", OK, "http://www.msi.com/product/mb/785GM-E51.html", NULL), B("MSI", "MS-7597 (GF615M-P33)", BAD, NULL, "Missing board enable/SIO support (Fintek F71889), see http://www.flashrom.org/pipermail/flashrom/2012-March/008956.html"), B("MSI", "MS-7599 (870-C45)", OK, "http://www.msi.com/product/mb/870-C45.html", NULL), - B("MSI", "MS-7613 (Iona-GL8E)", BAD, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c02014355&lc=en&cc=dk&d…", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("MSI", "MS-7635 (H55M-ED55)", BAD, "http://www.msi.com/product/mb/H55M-ED55.html", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("MSI", "MS-7613 (Iona-GL8E)", BAD, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c02014355&lc=en&cc=dk&d…", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("MSI", "MS-7635 (H55M-ED55)", BAD, "http://www.msi.com/product/mb/H55M-ED55.html", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("MSI", "MS-7640 (890FXA-GD70)",OK, "http://www.msi.com/product/mb/890FXA-GD70.html", NULL), B("MSI", "MS-7642 (890GXM-G65)", OK, "http://www.msi.com/product/mb/890GXM-G65.html", NULL), B("MSI", "MS-7676 (H67MA-ED55(B3))", OK, "http://www.msi.com/product/mb/H67MA-ED55--B3-.html", "Seems to work fine basically, but user reported (hopefully unrelated) buggy behavior of the board after a firmware upgrade. See http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html"), @@ -956,8 +956,8 @@ const struct board_info boards_known[] = { B("Supermicro", "X9DRT-HF+", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), B("Supermicro", "X9DRW", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9QRi-F+", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C600/X9QRi-F_.cfm", "Probing works (Macronix MX25L12805, 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), - B("Supermicro", "X9SCA-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("Supermicro", "X9SCL", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9SCA-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9SCL", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64.V, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("T-Online", "S-100", OK, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", OK, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", OK, NULL, NULL), @@ -1010,8 +1010,8 @@ const struct board_info boards_known[] = { B("VIA", "VB700X", OK, "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL), B("ZOTAC", "Fusion-ITX WiFi (FUSION350-A-E)", OK, NULL, NULL), B("ZOTAC", "GeForce 8200", OK, NULL, NULL), - B("ZOTAC", "H61-ITX WiFi (H61ITX-A-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ZOTAC", "H67-ITX WiFi (H67ITX-C-E)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ZOTAC", "H61-ITX WiFi (H61ITX-A-E)", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ZOTAC", "H67-ITX WiFi (H67ITX-C-E)", BAD, NULL, "Probing works (Winbond W25Q32.V, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ZOTAC", "nForce 630i Supreme (N73U-Supreme)", OK, NULL, NULL), B("ZOTAC", "ZBOX AD02 (PLUS)", OK, NULL, NULL), B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL), -- Kind regards, Stefan Tauner

1 0

[commit] r1650 - trunk
by repository service 22 Feb '13

22 Feb '13

Author: stefanct Date: Fri Feb 22 16:58:45 2013 New Revision: 1650 URL: http://flashrom.org/trac/flashrom/changeset/1650 Log: Add a bunch of new/tested stuff and various small changes 17. Tested Mainboards: OK: - Acer V75-M (used in IBM Aptiva 2170-G) http://www.flashrom.org/pipermail/flashrom/2012-December/010300.html - Acorp 6M810C http://www.flashrom.org/pipermail/flashrom/2013-January/010433.html - ASRock G31M-S rev 2.0 http://www.flashrom.org/pipermail/flashrom/2013-February/010538.html - ASUS F1A75-V PRO http://paste.flashrom.org/view.php?id=1528 - ASUS M5A97 (rev. 1.0) http://www.flashrom.org/pipermail/flashrom/2013-February/010483.html - ASUS P5KPL-AM IN/GB http://www.flashrom.org/pipermail/flashrom/2013-January/010455.html - GABYTE GA-H77M-D3H http://www.flashrom.org/pipermail/flashrom/2013-February/010538.html NOT OK: - GIGABYTE GA-Z77MX-D3H http://paste.flashrom.org/view.php?id=1529 http://paste.flashrom.org/view.php?id=1530 Tested flash chips: - Winbond W25X10 to PREW (+PREW) Reported on IRC(?) - Eon EN25Q32(A/B) to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-February/010533.html - Eon EN25Q64 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-January/010466.html Miscellaneous: - Fix superflouos line breaks in wiki mainboard and laptop output. - Use the .nh (no hyphenation) command in the manpage to enforce single-line URLs where useful. - Reference the manpage (besides the Laptops wiki page) in the laptop warning. - Minor output and whitespace fixes. - Add Fidelix IDs. - Add ISSE clones of PMC chips. - Fix typo: EMST -> ESMT. - Add ID of ESMT F25D08QA. - Refine GigaDevice GD25Q series (missing voltages and comments). - Use underscore instead of lower-case x as wildcard in Sharp chip names. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8 trunk/internal.c trunk/it87spi.c trunk/print.c trunk/print_wiki.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/flashchips.c Fri Feb 22 16:58:45 2013 (r1650) @@ -2713,11 +2713,11 @@ }, { - .vendor = "EMST", + .vendor = "ESMT", .name = "F49B002UA", .bustype = BUS_PARALLEL, - .manufacture_id = EMST_ID, - .model_id = EMST_F49B002UA, + .manufacture_id = ESMT_ID, + .model_id = ESMT_F49B002UA, .total_size = 256, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, @@ -2745,11 +2745,11 @@ }, { - .vendor = "EMST", + .vendor = "ESMT", .name = "F25L008A", .bustype = BUS_SPI, - .manufacture_id = EMST_ID, - .model_id = EMST_F25L008A, + .manufacture_id = ESMT_ID, + .model_id = ESMT_F25L008A, .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_EITHER, @@ -3748,7 +3748,7 @@ .page_size = 256, /* OTP: 512B total; enter 0x3A */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3784,7 +3784,7 @@ .page_size = 256, /* OTP: 512B total; enter 0x3A */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4248,13 +4248,13 @@ { .vendor = "GigaDevice", - .name = "GD25Q80", + .name = "GD25Q80(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q80, .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -4293,7 +4293,7 @@ .model_id = GIGADEVICE_GD25Q16, .total_size = 2048, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -4326,13 +4326,13 @@ { .vendor = "GigaDevice", - .name = "GD25Q32", + .name = "GD25Q32(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q32, .total_size = 4096, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -4365,13 +4365,13 @@ { .vendor = "GigaDevice", - .name = "GD25Q64", + .name = "GD25Q64(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q64, .total_size = 8192, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -4399,17 +4399,18 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q128", + .name = "GD25Q128B", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q128, .total_size = 16384, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -4437,6 +4438,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -4447,7 +4449,8 @@ .model_id = GIGADEVICE_GD25LQ32, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6687,7 +6690,7 @@ .name = "LH28F008BJT-BTLZ1", .bustype = BUS_PARALLEL, .manufacture_id = SHARP_ID, - .model_id = SHARP_LH28F008BJxxPB, + .model_id = SHARP_LH28F008BJ__PB, .total_size = 1024, .page_size = 64 * 1024, .tested = TEST_OK_PREW, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/flashchips.h Fri Feb 22 16:58:45 2013 (r1650) @@ -201,9 +201,10 @@ #define CATALYST_ID 0x31 /* Catalyst */ #define CATALYST_CAT28F512 0xB8 -#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */ -#define EMST_F25L008A 0x2014 -#define EMST_F49B002UA 0x00 +#define ESMT_ID 0x8C /* Elite Semiconductor Memory Technology (ESMT) / EFST Elite Flash Storage */ +#define ESMT_F25L008A 0x2014 +#define ESMT_F25D08QA 0x2534 +#define ESMT_F49B002UA 0x00 /* * EN25 chips are SPI, first byte of device ID is memory type, @@ -265,6 +266,15 @@ #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */ +#define FIDELIX_ID 0xF8 /* Fidelix */ +#define FIDELIX_FM25M16 0x4215 +#define FIDELIX_FM25M32 0x4216 +#define FIDELIX_FM25M64 0x4217 +#define FIDELIX_FM25Q08 0x3214 +#define FIDELIX_FM25Q16 0x3215 /* Same as FM25S16 (which is apparently single I/O only) */ +#define FIDELIX_FM25Q32 0x3216 +#define FIDELIX_FM25Q64 0x3217 + #define FUJITSU_ID 0x04 /* Fujitsu */ #define FUJITSU_MBM29DL400BC 0x0F #define FUJITSU_MBM29DL400TC 0x0C @@ -299,11 +309,11 @@ #define GIGADEVICE_ID 0xC8 /* GigaDevice */ #define GIGADEVICE_GD25Q20 0x4012 #define GIGADEVICE_GD25Q40 0x4013 -#define GIGADEVICE_GD25Q80 0x4014 -#define GIGADEVICE_GD25Q16 0x4015 -#define GIGADEVICE_GD25Q32 0x4016 -#define GIGADEVICE_GD25Q64 0x4017 -#define GIGADEVICE_GD25Q128 0x4018 +#define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */ +#define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ +#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ +#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ +#define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B only? */ #define GIGADEVICE_GD25LQ32 0x6016 #define HYUNDAI_ID 0xAD /* Hyundai */ @@ -451,10 +461,10 @@ #define PMC_PM25LV016B 0x14 #define PMC_PM29F002T 0x1D #define PMC_PM29F002B 0x2D -#define PMC_PM39LV512 0x1B -#define PMC_PM39F010 0x1C /* Same as Pm39LV010 */ +#define PMC_PM39LV512 0x1B /* Same as IS39LV512 */ +#define PMC_PM39F010 0x1C /* Same as Pm39LV010, IS39LV010 */ #define PMC_PM39LV020 0x3D -#define PMC_PM39LV040 0x3E +#define PMC_PM39LV040 0x3E /* Same as IS39LV040 */ #define PMC_PM39F020 0x4D #define PMC_PM39F040 0x4E #define PMC_PM49FL002 0x6D @@ -469,11 +479,11 @@ #define SANYO_LE25FW203A 0x1600 #define SHARP_ID 0xB0 /* Sharp */ -#define SHARP_LH28F008BJxxPT 0xEC -#define SHARP_LH28F008BJxxPB 0xED -#define SHARP_LH28F800BVxxBTL 0x4B -#define SHARP_LH28F800BVxxBV 0x4D -#define SHARP_LH28F800BVxxTV 0x4C +#define SHARP_LH28F008BJ__PT 0xEC +#define SHARP_LH28F008BJ__PB 0xED +#define SHARP_LH28F800BV__BTL 0x4B +#define SHARP_LH28F800BV__BV 0x4D +#define SHARP_LH28F800BV__TV 0x4C #define SHARP_LHF00L02 0xC9 /* Same as LHF00L06/LHF00L07 */ #define SHARP_LHF00L04 0xCF /* Same as LHF00L03/LHF00L05 */ Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/flashrom.8 Fri Feb 22 16:58:45 2013 (r1650) @@ -161,6 +161,7 @@ .BR \-\-list\-supported , but outputs the supported hardware in MediaWiki syntax, so that it can be easily pasted into the wiki page at +.nh .BR http://www.flashrom.org/ . Please note that MediaWiki output is not compiled in by default. .TP @@ -390,6 +391,7 @@ .B BUGS section). The embedded controller (EC) in these machines often interacts badly with flashing. +.nh .B http://www.flashrom.org/Laptops has more information. For example the EC firmware sometimes resides on the same flash chip as the host firmware. While flashrom tries to change the contents of @@ -715,8 +717,10 @@ (DLC 5). .sp More information about the RayeR hardware is available at +.nh .BR "http://rayer.ic.cz/elektro/spipgm.htm " . The schematic of the Xilinx DLC 5 was published at +.nh .BR "http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html " . .SS .BR "pony_spi " programmer @@ -730,6 +734,7 @@ parameter accepts the values "si_prog" (default) or "serbang". .sp Information about the SI-Prog adapter can be found at +.nh .BR "http://www.lancos.com/siprogsch.html " . .sp An example call to flashrom is @@ -765,6 +770,7 @@ section above. .sp More information about the hardware is available at +.nh .BR http://wiki.opengraphics.org . .SS .BR "linux_spi " programmer @@ -869,6 +875,7 @@ too. Please provide a way to contact you later (e.g.\& a mail address) and be patient if there is no immediate reaction. Also, we provide a pastebin service at +.nh .B http://paste.flashrom.org that is very useful when you want to share logs etc.\& without spamming the channel. @@ -884,8 +891,8 @@ .B internal programmer subsection of the .B PROGRAMMER SPECIFIC INFO -section. -.B " http://www.flashrom.org/Laptops" +section and the information in our wiki at +.BR "http://www.flashrom.org/Laptops " . .SS One-time programmable (OTP) memory and unique IDs .sp Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/internal.c Fri Feb 22 16:58:45 2013 (r1650) @@ -299,7 +299,7 @@ msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n" "recommend to use the vendor flashing utility. The embedded controller\n" "(EC) in these machines often interacts badly with flashing.\n" - "See http://www.flashrom.org/Laptops for details.\n\n" + "See the manpage and http://www.flashrom.org/Laptops for details.\n\n" "If flash is shared with the EC, erase is guaranteed to brick your laptop\n" "and write may brick your laptop.\n" "Read and probe may irritate your EC and cause fan failure, backlight\n" Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/it87spi.c Fri Feb 22 16:58:45 2013 (r1650) @@ -87,15 +87,12 @@ case 0x86: case 0x87: /* FIXME: Print revision for all models? */ - msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port " - "0x%x\n", s.model, s.port); + msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port 0x%x\n", s.model, s.port); register_superio(s); break; case 0x85: - msg_pdbg("Found ITE EC, ID 0x%04hx," - "Rev 0x%02x on port 0x%x.\n", - s.model, sio_read(s.port, CHIP_VER_REG), - s.port); + msg_pdbg("Found ITE EC, ID 0x%04hx, Rev 0x%02x on port 0x%x.\n", + s.model, sio_read(s.port, CHIP_VER_REG), s.port); register_superio(s); break; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/print.c Fri Feb 22 16:58:45 2013 (r1650) @@ -519,6 +519,7 @@ B("abit", "VT6X4", OK, NULL, NULL), B("Acer", "V75-M", OK, NULL, "This is an OEM board used by IBM in e.g. Aptiva 2170-G"), B("Acorp", "6A815EPD", OK, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL), + B("Acorp", "6M810C", OK, NULL, NULL), B("Advantech", "PCM-5820", OK, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", OK, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", OK, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ @@ -540,6 +541,7 @@ B("ASRock", "ALiveNF6G-DVI", OK, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), B("ASRock", "AM2NF6G-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", NULL), + B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL), B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), @@ -577,6 +579,7 @@ B("ASUS", "Crosshair IV Extreme", OK, "http://www.asus.com/Motherboards/AMD_AM3/Crosshair_IV_Extreme/", NULL), B("ASUS", "DSAN-DX", NT, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL), B("ASUS", "E35M1-I DELUXE", OK, "http://www.asus.com/Motherboards/AMD_CPU_on_Board/E35M1I_DELUXE/", NULL), + B("ASUS", "F1A75-V PRO", OK, "http://www.asus.com/Motherboard/F1A75V_PRO/", NULL), B("ASUS", "K8N", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8N/", NULL), B("ASUS", "K8V", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V/", NULL), B("ASUS", "K8V SE Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V_SE_Deluxe/", NULL), @@ -611,6 +614,7 @@ B("ASUS", "M4N68T V2", OK, "http://www.asus.com/Motherboards/AMD_AM3/M4N68T_V2/", NULL), B("ASUS", "M4N78 PRO", OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_PRO/", NULL), B("ASUS", "M5A78L-M LX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A78LM_LX/", "The MAC address of the onboard LAN NIC is stored in flash, hence overwritten by flashrom; see http://www.flashrom.org/pipermail/flashrom/2012-May/009200.html"), + B("ASUS", "M5A97 (rev. 1.0)", OK, "http://www.asus.com/Motherboard/M5A97/", NULL), B("ASUS", "M5A99X EVO", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/", NULL), B("ASUS", "Maximus IV Extreme", BAD, "http://www.asus.com/Motherboards/Intel_Socket_1155/Maximus_IV_Extreme/", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "MEW-AM", BAD, NULL, "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -656,6 +660,7 @@ B("ASUS", "P5K-V", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KV/", NULL), B("ASUS", "P5K-VM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KVM/", NULL), B("ASUS", "P5KC", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KC/", NULL), + B("ASUS", "P5KPL-AM IN/GB", OK, "http://support.asus.com/download.aspx?SLanguage=en&m=P5KPL-AM+IN%2fGB&os=29", NULL), B("ASUS", "P5KPL-CM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL), B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), @@ -777,6 +782,7 @@ B("GIGABYTE", "GA-H61M-D2-B3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3773", NULL), B("GIGABYTE", "GA-H61M-D2H-USB3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4004", NULL), B("GIGABYTE", "GA-H77-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4141", "Does only work with -p internal:ich_spi_mode=hwseq due to an evil twin of MX25L6405 and ICH SPI lockdown."), + B("GIGABYTE", "GA-H77M-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4388", NULL), B("GIGABYTE", "GA-EX58-UD4P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), B("GIGABYTE", "GA-K8N51GMF", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), @@ -804,6 +810,7 @@ B("GIGABYTE", "GA-X79-UD5", OK, NULL, NULL), B("GIGABYTE", "GA-Z68MX-UD2H-B (rev. 1.3)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3854", NULL), B("GIGABYTE", "GA-Z68XP-UD3 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3892", NULL), + B("GIGABYTE", "GA-Z77MX-D3H", BAD, "http://www.gigabyte.com/products/product-page.aspx?pid=4145", "Uses MX25L6436E and requires a small patch (but works flawlessly with that)."), B("HP", "8100 Elite CMT PC (304Bh)", BAD, NULL, "SPI lock down, PR, read-only descriptor, locked ME region."), B("HP", "e-Vectra P2706T", OK, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", OK, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Feb 20 19:03:36 2013 (r1649) +++ trunk/print_wiki.c Fri Feb 22 16:58:45 2013 (r1650) @@ -209,7 +209,7 @@ /* end inner table if it did not fill the last column fully */ if (((i % lines_per_col)) > 0) printf("\n|}\n\n"); - printf("\n\n|}\n"); + printf("|}\n"); if (num_notes > 0) printf("\n<small>\n%s</small>\n", notes);

1 0

Re: [flashrom] Added chipsets
by Stefan Tauner 22 Feb '13

22 Feb '13

On Fri, 22 Feb 2013 08:58:54 +0400 Николай Николаев <evrinoma(a)gmail.com> wrote: >> these look like typos? > This is not typos. I'm verified again all documentation. > The chip S25FL128S has a Device Identification like a 2018 (table 11.2 page > 133) > The chip S25FL256S has a Device Identification like a 0219 (table 11.2 page > 133) > The chip S25FL256S has a Device Identification like a 0220 (table 11.4 page > 123) >> +#define SPANSION_S25FL128 0x2018 >> +#define SPANSION_S25FL256 0x0219 >> +#define SPANSION_S25FL512 0x0220 hm... still looks like a typo, but maybe not your typo (well, you added a typo now in the last line but that's not what I am talking about ;) It would not be the first time that a datasheet has wrong IDs. It just happens too easily. In general it would be best to verify that with actual hardware and/or to contact the manufacturer. I have no time to look into this now in detail. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Added chipsets
by Stefan Tauner 22 Feb '13

22 Feb '13

On Fri, 22 Feb 2013 08:07:33 +0300 Peter Lemenkov <lemenkov(a)gmail.com> wrote: > Hello! > > 2013/2/22 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > > It would also make sense to split your huge patch into smaller pieces > > (e.g. one patch per manufacturer) so that we can review it easier. > > Maybe it's time to consider switching to Git entirely? Git is much > more better suited for this kind of task. You need to convince Carl-Daniel not me :) I have never checked out flashrom with subversion directly, only with git-svn and that works very nicely and there is no reason why submitting patches would be easier due to a switch to git alone (i.e. when we still demand patches to be sent to the mailing list instead of pull requests on github or something similar). As said, I use it all the time and there has been no problems with the patches generated by me or anybody else using git AFAIK. Also, Carl-Daniel repeatedly said there is no way he will switch to git and since there is no immediate need to do so this will not happen in the near future. If anybody has major problems with the git-svn/git send-email workflow he can also send me pull requests on github https://github.com/stefanct/flashrom But I don't make any promises that I will merge them in a timely manner *or at all* and this should be regarded as the last resort. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] dediprog: Use asynchronous bulk transfers for reading
by Nico Huber 22 Feb '13

22 Feb '13

This utilizes libusb-1.0's interface for asynchronous transfers. A read is split into 512 byte chunks as required by the dediprog hardware. Up to eight chunks are scheduled for asynchronous transfer which results in a viable speed-up. First tests have shown a three times speed increase. Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- dediprog.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 83 insertions(+), 9 deletions(-) diff --git a/dediprog.c b/dediprog.c index 93c4072..3cd7b01 100644 --- a/dediprog.c +++ b/dediprog.c @@ -31,6 +31,7 @@ #define FIRMWARE_VERSION(x,y,z) ((x << 16) | (y << 8) | z) #define DEFAULT_TIMEOUT 3000 +#define DEDIPROG_ASYNC_TRANSFERS 8 /* at most 8 asynchronous transfers */ static libusb_context *usb_ctx; static libusb_device_handle *dediprog_handle; static int dediprog_firmwareversion; @@ -235,6 +236,38 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) return 0; } +struct dediprog_transfer_status { + int error; /* OK if 0, ERROR else */ + unsigned int queued_idx; + unsigned int finished_idx; +}; + +static void dediprog_bulk_read_cb(struct libusb_transfer *const transfer) +{ + struct dediprog_transfer_status *const status = (struct dediprog_transfer_status *)transfer->user_data; + if (transfer->status != LIBUSB_TRANSFER_COMPLETED) { + status->error = 1; + msg_perr("SPI bulk read failed!\n"); + } + ++status->finished_idx; +} + +static int dediprog_bulk_read_poll(const struct dediprog_transfer_status *const status, const int finish) +{ + if (status->finished_idx >= status->queued_idx) + return 0; + + do { + struct timeval timeout = { 10, 0 }; + const int ret = libusb_handle_events_timeout_completed(usb_ctx, &timeout, NULL); + if (ret < 0) { + msg_perr("Polling read events failed: %i %s!\n", ret, libusb_error_name(ret)); + return 1; + } + } while (finish && (status->finished_idx < status->queued_idx)); + return 0; +} + /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. * @start start address * @len length @@ -243,7 +276,7 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int ret, transferred; + int ret, err = 1; unsigned int i; /* chunksize must be 512, other sizes will NOT work at all. */ const unsigned int chunksize = 0x200; @@ -253,6 +286,10 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, chunksize & 0xff, (chunksize >> 8) & 0xff }; + struct dediprog_transfer_status status = { 0, 0, 0 }; + struct libusb_transfer *transfers[DEDIPROG_ASYNC_TRANSFERS] = { NULL, }; + struct libusb_transfer *transfer; + if ((start % chunksize) || (len % chunksize)) { msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " "at flashrom(a)flashrom.org\n", __func__, start, len); @@ -273,17 +310,54 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, return 1; } - for (i = 0; i < count; i++) { - ret = libusb_bulk_transfer(dediprog_handle, 0x80 | dediprog_endpoint, - buf + i * chunksize, chunksize, &transferred, DEFAULT_TIMEOUT); - if ((ret < 0) || (transferred != chunksize)) { - msg_perr("SPI bulk read %i failed, expected %i, got %i %s!\n", - i, chunksize, ret, libusb_error_name(ret)); - return 1; + /* + * Ring buffer of bulk transfers. + * Poll until at least one transfer is ready, + * schedule next transfers until buffer is full. + */ + + /* Allocate bulk transfers. */ + for (i = 0; i < min(DEDIPROG_ASYNC_TRANSFERS, count); ++i) { + transfers[i] = libusb_alloc_transfer(0); + if (!transfers[i]) { + msg_perr("Allocating libusb transfer %i failed: %s!\n", i, libusb_error_name(ret)); + goto _err_free; } } - return 0; + /* Now transfer requested chunks using libusb's asynchronous interface. */ + while (!status.error && (status.queued_idx < count)) { + while ((status.queued_idx - status.finished_idx) < DEDIPROG_ASYNC_TRANSFERS) { + transfer = transfers[status.queued_idx % DEDIPROG_ASYNC_TRANSFERS]; + libusb_fill_bulk_transfer(transfer, dediprog_handle, 0x80 | dediprog_endpoint, + (unsigned char *)buf + status.queued_idx * chunksize, chunksize, + dediprog_bulk_read_cb, &status, DEFAULT_TIMEOUT); + transfer->flags |= LIBUSB_TRANSFER_SHORT_NOT_OK; + ret = libusb_submit_transfer(transfer); + if (ret < 0) { + msg_perr("Submitting SPI bulk read %i failed: %i %s!\n", + status.queued_idx, ret, libusb_error_name(ret)); + goto _err_free; + } + ++status.queued_idx; + } + if (dediprog_bulk_read_poll(&status, 0)) + goto _err_free; + } + /* Wait for transfers to finish. */ + if (dediprog_bulk_read_poll(&status, 1)) + goto _err_free; + /* Check if everything has been transmitted. */ + if ((status.finished_idx < count) || status.error) + goto _err_free; + + err = 0; + +_err_free: + dediprog_bulk_read_poll(&status, 1); + for (i = 0; i < DEDIPROG_ASYNC_TRANSFERS; ++i) + if (transfers[i]) libusb_free_transfer(transfers[i]); + return err; } static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, -- 1.7.9.5

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Re: [flashrom] Added chipsets
by Stefan Tauner 22 Feb '13

22 Feb '13

Hello Николай, that's quite some work you have done, thank you. There is one very important bit missing though: the signed-off-by line that certifies that you are legally allowed to release these changes under a free license. Please see http://flashrom.org/Development_Guidelines and http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for details. We can not commit your changes without this. It would also make sense to split your huge patch into smaller pieces (e.g. one patch per manufacturer) so that we can review it easier. I have not looked at the patch in detail, but some naming will have to change probably. > +#define SPANSION_S25FL128 0x2018 > +#define SPANSION_S25FL256 0x0219 > +#define SPANSION_S25FL512 0x0220 these look like typos? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 3

EN25Q32(A/B) fully tested
by Lucian Langa 22 Feb '13

22 Feb '13

Hi, I just tested EN25Q32 chip on a raspberry spi programmer. The memory chip comes from a TP-LINK router (mr3220v2) that contains this chips. I used flashrom+rpi(spi) to reflash router firmware, as I previously bricked the router beyond the recovery. I have desoldered the chip from the router and connected it directly to the raspberry headers. All in all it went fine I managed to reflash the chip and router works fine now. See attached logs from all operation I used (READ/ERASE/WRITE) Cheers, --lucian

2 1

Logs for ASRock G31M-S rev 2.0, Gigabyte GA-H77M-D3H rev. 1.1
by Александр Владимирович 22 Feb '13

22 Feb '13

Logs for ASRock G31M-S rev 2.0, Gigabyte GA-H77M-D3H rev. 1.1

2 1

[commit] r1649 - trunk
by repository service 20 Feb '13

20 Feb '13

Author: hailfinger Date: Wed Feb 20 19:03:36 2013 New Revision: 1649 URL: http://flashrom.org/trac/flashrom/changeset/1649 Log: Adds a programmer parameter 'spispeed' to the dediprog driver to control the transfer rate on the spi bus. The following rates are available (in Hz): 375k, 750k, 1.5M, 2.18M, 3M, 8M, 12M and 24M The original driver reinitializes the programmer after setting the speed, so the initialization calls have moved into a new function dediprog_setup() which is called twice. Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/dediprog.c trunk/flashrom.8 Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Mon Feb 4 05:38:42 2013 (r1648) +++ trunk/dediprog.c Wed Feb 20 19:03:36 2013 (r1649) @@ -158,7 +158,23 @@ return 0; } -#if 0 +struct dediprog_spispeeds { + const char *const name; + const int speed; +}; + +static const struct dediprog_spispeeds spispeeds[] = { + { "24M", 0x0 }, + { "12M", 0x2 }, + { "8M", 0x1 }, + { "3M", 0x3 }, + { "2.18M", 0x4 }, + { "1.5M", 0x5 }, + { "750k", 0x6 }, + { "375k", 0x7 }, + { NULL, 0x0 }, +}; + /* After dediprog_set_spi_speed, the original app always calls * dediprog_set_spi_voltage(0) and then * dediprog_check_devicestring() four times in a row. @@ -166,56 +182,20 @@ * This looks suspiciously like the microprocessor in the SF100 has to be * restarted/reinitialized in case the speed changes. */ -static int dediprog_set_spi_speed(uint16_t speed) +static int dediprog_set_spi_speed(unsigned int spispeed_idx) { int ret; - unsigned int khz; - /* Case 1 and 2 are in weird order. Probably an organically "grown" - * interface. - * Base frequency is 24000 kHz, divisors are (in order) - * 1, 3, 2, 8, 11, 16, 32, 64. - */ - switch (speed) { - case 0x0: - khz = 24000; - break; - case 0x1: - khz = 8000; - break; - case 0x2: - khz = 12000; - break; - case 0x3: - khz = 3000; - break; - case 0x4: - khz = 2180; - break; - case 0x5: - khz = 1500; - break; - case 0x6: - khz = 750; - break; - case 0x7: - khz = 375; - break; - default: - msg_perr("Unknown frequency selector 0x%x! Aborting.\n", speed); - return 1; - } - msg_pdbg("Setting SPI speed to %u kHz\n", khz); + msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, speed, 0xff, NULL, - 0x0, DEFAULT_TIMEOUT); + ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command Set SPI Speed 0x%x failed!\n", speed); + msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; } return 0; } -#endif /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. * @start start address @@ -742,6 +722,28 @@ return millivolt; } +static int dediprog_setup(void) +{ + /* URB 6. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 7. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 8. Command Prepare Receive Device String. */ + /* URB 9. Command Receive Device String. */ + if (dediprog_check_devicestring()) { + return 1; + } + /* URB 10. Command C. */ + if (dediprog_command_c()) { + return 1; + } + return 0; +} + static const struct spi_programmer spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, @@ -783,13 +785,29 @@ int dediprog_init(void) { struct usb_device *dev; - char *voltage, *device; + char *voltage, *device, *spispeed; + int spispeed_idx = 2; int millivolt = 3500; long usedevice = 0; - int ret; + int i, ret; msg_pspew("%s\n", __func__); + spispeed = extract_programmer_param("spispeed"); + if (spispeed) { + for (i = 0; spispeeds[i].name; ++i) { + if (!strcasecmp(spispeeds[i].name, spispeed)) { + spispeed_idx = i; + break; + } + } + if (!spispeeds[i].name) { + msg_perr("Error: Invalid 'spispeed' value.\n"); + free(spispeed); + return 1; + } + free(spispeed); + } voltage = extract_programmer_param("voltage"); if (voltage) { millivolt = parse_voltage(voltage); @@ -852,33 +870,24 @@ return 1; } dediprog_endpoint = 2; - + if (register_shutdown(dediprog_shutdown, NULL)) return 1; dediprog_set_leds(PASS_ON|BUSY_ON|ERROR_ON); - /* URB 6. Command A. */ - if (dediprog_command_a()) { + /* Perform basic setup. */ + if (dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } - /* URB 7. Command A. */ - if (dediprog_command_a()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 8. Command Prepare Receive Device String. */ - /* URB 9. Command Receive Device String. */ - if (dediprog_check_devicestring()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 10. Command C. */ - if (dediprog_command_c()) { + + /* After setting voltage and speed, perform setup again. */ + if (dediprog_set_spi_voltage(0) || dediprog_set_spi_speed(spispeed_idx) || dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } + /* URB 11. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(millivolt)) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon Feb 4 05:38:42 2013 (r1648) +++ trunk/flashrom.8 Wed Feb 20 19:03:36 2013 (r1649) @@ -676,6 +676,18 @@ Usage example to select the second device: .sp .B " flashrom \-p dediprog:device=1" +.sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus. Syntax is +.sp +.B " flashrom \-p dediprog:spispeed=frequency" +.sp +where +.B frequency +can be +.BR 375k ", " 750k ", " 1.5M ", " 2.18M ", " 3M ", " 8M ", " 12M " or " 24M +(in Hz). The default is a frequency of 12 MHz. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use

1 0

flashrom can never write if the flash chip isn't found automatically
by 123 123 19 Feb '13

19 Feb '13

1 0

W836xx: 03RG89 Ver FAB1: flashrom -V
by Don Alexander 19 Feb '13

19 Feb '13

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 flashrom -V flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 3013M loops per second, 10 myus = 10 us, 100 myus = 115 us, 1000 myus = 991 us, 10000 myus = 10179 us, 4 myus = 12 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc. " DMI string system-product-name: "Dell System XPS L702X" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc. " DMI string baseboard-product-name: "03RG89" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Portable" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. - -- == Don Alexander It's a tough job, but some mug has to do it... RooSoft Ltd -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlEi94cACgkQuipFNInZ6evyAACfWpcUW59YjP9xWE8uAttNQvw/ HP0AnRo5JGXUL4+mCVBRea2W861GexUh =H5wR -----END PGP SIGNATURE-----

1 0

Re: [flashrom] Please send a verbose log
by Eric 18 Feb '13

18 Feb '13

Hi, Here is a verbose log for this : http://fr.asus.com/Motherboards/Intel_Socket_1155/P8P67M_PRO -- Si tu as une pomme, que j'ai une pomme, et que l'on échange nos pommes, nous aurons chacun une pomme. Mais si tu as une idée, que j'ai une idée, et que l'on échange nos idées, nous aurons chacun deux idées. La différence entre Linux et Windows ,c'est que Linux c'est comme une belle fille , il faut l'apprivoiser , la comprendre , la séduire tandis que Windows , c'est comme une prostitué , il faut payer et surtout bien se protéger. Pour remédier à ce problème, la solution c'est Ubuntu ! C'est une distribution GNU/Linux qui remplace avantageusement Ouinedoze. Vous êtes libre d'en obtenir une copie pour installation et utilisation en la téléchargeant gratuitement et légalement sur le lien ci-dessous. http://www.ubuntu-fr.org/telechargement

1 0

Re: [flashrom] Bypassing the size check
by Stefan Tauner 15 Feb '13

15 Feb '13

On Thu, 14 Feb 2013 21:55:50 -0800 Jason Craik <jason.c7(a)gmail.com> wrote: > Hello, > > I'm trying to downgrade the bios on my Asus P8Z77-v LK motherboard and am > using a dos version of your program to try and do it. When I try and > reflash with the old .rom file it gives me an error about having two > different size files. I'm wondering if theres a way to just bypass that > check and force write the old .rom file onto the chip. Hello Jason, there is no command line switch to do this and there is no reason to do this in any sane use case either. How did you obtain the "old .rom file"? Obviously not by reading it with flashrom because then it would have the correct size. Also, P8Z77 sounds like a locked down board... please send a verbose log. I assume you have obtained an image of *the BIOS region only* by other means and want to write it to *the BIOS region only*... if you really know what you are doing, please take a look at the documentation of the layout file in the manpage and think about how you want to recover if something goes wrong. ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Bypassing the size check
by Jason Craik 15 Feb '13

15 Feb '13

Hello, I'm trying to downgrade the bios on my Asus P8Z77-v LK motherboard and am using a dos version of your program to try and do it. When I try and reflash with the old .rom file it gives me an error about having two different size files. I'm wondering if theres a way to just bypass that check and force write the old .rom file onto the chip. Thanks, Jason

1 0

flashrom for msi windpad 110w
by Seryi Kuznecov 13 Feb '13

13 Feb '13

Hello! Need help knowing people. I have a tablet msi windpad 110w. For the Russian version of the producers put the trimmed version of the BIOS 207 http://paste.flashrom.org/view.php?id=1546 Roll back the standard means to version http://paste.flashrom.org/view.php?id=1547 by means ami msi and fails. The manufacturer says this to the fact that Russia banned TPM and therefore prohibited rollback bios and opening functions TPM (how unknown function in the BIOS to unlock the rollback not). The only way this is just the firmware programmer. It remains the last hope of flashrom. Here is a screen chip: http://paste.flashrom.org/view.php?id=1548. Datasheet: http://paste.flashrom.org/view.php?id=1549 Our version looks like 8-pin SOP (200mil, 150mil). Please help. Thank you.

1 0

Windpad 110w and flashrom
by Seryi Kuznecov 13 Feb '13

13 Feb '13

Здравствуйте! Нужна помощь знающих людей. У меня планшет msi windpad 110w. Для российской версии производители поставили обрезанную версию биоса 207 http://paste.flashrom.org/view.php?id=1546 Откатить стандартными средствами на версию http://paste.flashrom.org/view.php?id=1547 с помощью средств ami и msi не получается. Производитель комментирует это тем, что в России запрещен TPM и поэтому запрещен откат биоса и открытие функций TPM (каким образом неизвестно, функции разлочки отката в биосе нет) . Единственный способ прошивки это только программатор. Остается последняя надежда на flashrom. Вот скрин чипа: http://paste.flashrom.org/view.php?id=1548. Даташит: http://paste.flashrom.org/view.php?id=1549 Наша версия похоже 8-pin SOP (200mil, 150mil). Прошу помощи. Спасибо.

1 0

[PATCH] total Makefile rewrite
by Carl-Daniel Hailfinger 13 Feb '13

13 Feb '13

I almost lost my sanity trying to beat the Makefile into submission without using features only available in new GNU make versions. Some functions are now outsourced to a shell script. In theory, things should still work (except a few hardcoded dependencies which will be changed into autodetections in the future). At least now we have a framework to handle autodetection. It's not really hooked up yet, but it will allow stuff like make config CONFIG_WHATEVER=auto CONFIG_FOO=yes CONFIG_BAR=no The new (TM) way to compile flashrom is: make config make Please run "make distclean" the first time you test this patch. Not for merge yet, but this mechanism at least will allow clean handling of FTDI autodetect, libusb 1.x requirements and all that other pending fun stuff. Comments about the shell script are very appreciated, I tried to write in POSIX sh. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-Makefile_harddependencies_soft/hwaccess.h =================================================================== --- flashrom-Makefile_harddependencies_soft/hwaccess.h (Revision 1645) +++ flashrom-Makefile_harddependencies_soft/hwaccess.h (Arbeitskopie) @@ -167,7 +167,7 @@ #define le_to_cpu32 cpu_to_le32 #define le_to_cpu64 cpu_to_le64 -#if NEED_PCI == 1 +#if (NEED_PCI == 1) || (NEED_IOPORT_ACCESS == 1) #if defined (__i386__) || defined (__x86_64__) #define __FLASHROM_HAVE_OUTB__ 1 Index: flashrom-Makefile_harddependencies_soft/Makefile =================================================================== --- flashrom-Makefile_harddependencies_soft/Makefile (Revision 1645) +++ flashrom-Makefile_harddependencies_soft/Makefile (Arbeitskopie) @@ -103,28 +103,28 @@ LIBS += ../libgetopt/libgetopt.a # Bus Pirate, Serprog and PonyProg are not supported under DOS (missing serial support). ifeq ($(CONFIG_BUSPIRATE_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_BUSPIRATE_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_BUSPIRATE_SPI else override CONFIG_BUSPIRATE_SPI = no endif ifeq ($(CONFIG_SERPROG), yes) -UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SERPROG else override CONFIG_SERPROG = no endif ifeq ($(CONFIG_PONY_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_PONY_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_PONY_SPI else override CONFIG_PONY_SPI = no endif # Dediprog and FT2232 are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) -UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_DEDIPROG else override CONFIG_DEDIPROG = no endif ifeq ($(CONFIG_FT2232_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_FT2232_SPI else override CONFIG_FT2232_SPI = no endif @@ -140,73 +140,73 @@ LDFLAGS += -L/usr/local/lib # Serprog is not supported under Windows/MinGW (missing sockets support). ifeq ($(CONFIG_SERPROG), yes) -UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SERPROG else override CONFIG_SERPROG = no endif # For now we disable all PCI-based programmers on Windows/MinGW (no libpci). ifeq ($(CONFIG_INTERNAL), yes) -UNSUPPORTED_FEATURES += CONFIG_INTERNAL=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_INTERNAL else override CONFIG_INTERNAL = no endif ifeq ($(CONFIG_RAYER_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_RAYER_SPI else override CONFIG_RAYER_SPI = no endif ifeq ($(CONFIG_NIC3COM), yes) -UNSUPPORTED_FEATURES += CONFIG_NIC3COM=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NIC3COM else override CONFIG_NIC3COM = no endif ifeq ($(CONFIG_GFXNVIDIA), yes) -UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_GFXNVIDIA else override CONFIG_GFXNVIDIA = no endif ifeq ($(CONFIG_SATASII), yes) -UNSUPPORTED_FEATURES += CONFIG_SATASII=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SATASII else override CONFIG_SATASII = no endif ifeq ($(CONFIG_ATAHPT), yes) -UNSUPPORTED_FEATURES += CONFIG_ATAHPT=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_ATAHPT else override CONFIG_ATAHPT = no endif ifeq ($(CONFIG_DRKAISER), yes) -UNSUPPORTED_FEATURES += CONFIG_DRKAISER=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_DRKAISER else override CONFIG_DRKAISER = no endif ifeq ($(CONFIG_NICREALTEK), yes) -UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICREALTEK else override CONFIG_NICREALTEK = no endif ifeq ($(CONFIG_NICNATSEMI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICNATSEMI else override CONFIG_NICNATSEMI = no endif ifeq ($(CONFIG_NICINTEL), yes) -UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICINTEL else override CONFIG_NICINTEL = no endif ifeq ($(CONFIG_NICINTEL_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICINTEL_SPI else override CONFIG_NICINTEL_SPI = no endif ifeq ($(CONFIG_OGP_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_OGP_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_OGP_SPI else override CONFIG_OGP_SPI = no endif ifeq ($(CONFIG_SATAMV), yes) -UNSUPPORTED_FEATURES += CONFIG_SATAMV=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SATAMV else override CONFIG_SATAMV = no endif @@ -215,28 +215,28 @@ ifeq ($(TARGET_OS), libpayload) FLASHROM_CFLAGS += -DSTANDALONE ifeq ($(CONFIG_DUMMY), yes) -UNSUPPORTED_FEATURES += CONFIG_DUMMY=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_DUMMY else override CONFIG_DUMMY = no endif ifeq ($(CONFIG_BUSPIRATE_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_BUSPIRATE_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_BUSPIRATE_SPI else override CONFIG_BUSPIRATE_SPI = no endif ifeq ($(CONFIG_SERPROG), yes) -UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SERPROG else override CONFIG_SERPROG = no endif # Dediprog and FT2232 are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) -UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_DEDIPROG else override CONFIG_DEDIPROG = no endif ifeq ($(CONFIG_FT2232_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_FT2232_SPI else override CONFIG_FT2232_SPI = no endif @@ -244,7 +244,7 @@ ifneq ($(TARGET_OS), Linux) ifeq ($(CONFIG_LINUX_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_LINUX_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_LINUX_SPI else override CONFIG_LINUX_SPI = no endif @@ -260,32 +260,32 @@ # Right now this means the drivers below only work on x86. ifneq ($(ARCH), x86) ifeq ($(CONFIG_NIC3COM), yes) -UNSUPPORTED_FEATURES += CONFIG_NIC3COM=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NIC3COM else override CONFIG_NIC3COM = no endif ifeq ($(CONFIG_NICREALTEK), yes) -UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICREALTEK else override CONFIG_NICREALTEK = no endif ifeq ($(CONFIG_NICNATSEMI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_NICNATSEMI else override CONFIG_NICNATSEMI = no endif ifeq ($(CONFIG_RAYER_SPI), yes) -UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_RAYER_SPI else override CONFIG_RAYER_SPI = no endif ifeq ($(CONFIG_ATAHPT), yes) -UNSUPPORTED_FEATURES += CONFIG_ATAHPT=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_ATAHPT else override CONFIG_ATAHPT = no endif ifeq ($(CONFIG_SATAMV), yes) -UNSUPPORTED_FEATURES += CONFIG_SATAMV=yes +UNSUPPORTED_TARGET_FEATURES += CONFIG_SATAMV else override CONFIG_SATAMV = no endif @@ -411,6 +411,128 @@ ############################################################################### # Programmer drivers and programmer support infrastructure. +ifeq ($(CONFIG_INTERNAL), yes) +NEED_PCI += CONFIG_INTERNAL +endif + +ifeq ($(CONFIG_SERPROG), yes) +NEED_SERIAL += CONFIG_SERPROG +NEED_NET += CONFIG_SERPROG +endif + +ifeq ($(CONFIG_RAYER_SPI), yes) +NEED_IOPORT_ACCESS += CONFIG_RAYER_SPI +endif + +ifeq ($(CONFIG_PONY_SPI), yes) +NEED_SERIAL += CONFIG_PONY_SPI +endif + +ifeq ($(CONFIG_BITBANG_SPI), yes) +endif + +ifeq ($(CONFIG_NIC3COM), yes) +NEED_PCI += CONFIG_NIC3COM +endif + +ifeq ($(CONFIG_GFXNVIDIA), yes) +NEED_PCI += CONFIG_GFXNVIDIA +endif + +ifeq ($(CONFIG_SATASII), yes) +NEED_PCI += CONFIG_SATASII +endif + +ifeq ($(CONFIG_ATAHPT), yes) +NEED_PCI += CONFIG_ATAHPT +endif + +ifeq ($(CONFIG_FT2232_SPI), yes) +NEED_FTDI += CONFIG_FT2232_SPI +endif + +ifeq ($(CONFIG_DUMMY), yes) +endif + +ifeq ($(CONFIG_DRKAISER), yes) +NEED_PCI += CONFIG_DRKAISER +endif + +ifeq ($(CONFIG_NICREALTEK), yes) +NEED_PCI += CONFIG_NICREALTEK +endif + +ifeq ($(CONFIG_NICNATSEMI), yes) +NEED_PCI += CONFIG_NICNATSEMI +endif + +ifeq ($(CONFIG_NICINTEL), yes) +NEED_PCI += CONFIG_NICINTEL +endif + +ifeq ($(CONFIG_NICINTEL_SPI), yes) +NEED_PCI += CONFIG_NICINTEL_SPI +endif + +ifeq ($(CONFIG_OGP_SPI), yes) +NEED_PCI += CONFIG_OGP_SPI +endif + +ifeq ($(CONFIG_BUSPIRATE_SPI), yes) +NEED_SERIAL += CONFIG_BUSPIRATE_SPI +endif + +ifeq ($(CONFIG_DEDIPROG), yes) +NEED_USB += CONFIG_DEDIPROG +endif + +ifeq ($(CONFIG_SATAMV), yes) +NEED_PCI += CONFIG_SATAMV +endif + +ifeq ($(CONFIG_LINUX_SPI), yes) +endif + +ifneq ($(NEED_SERIAL), ) +endif + +ifneq ($(NEED_NET), ) +endif + +ifneq ($(NEED_PCI), ) +CHECK_LIBPCI = yes +endif + +ifneq ($(NEED_USB), ) +CHECK_LIBUSB0 = yes +endif + +ifneq ($(NEED_FTDI), ) +CHECK_LIBFTDI = yes +endif + +############################################################################################################################################################################# + +defaulttarget: all + +config: compiler + @printf "" > .availablefeatures + @./config.sh utsname +ifneq ($(CHECK_LIBPCI), ) + @./config.sh libpci +endif +ifneq ($(CHECK_LIBUSB0), ) + @./config.sh libusb0 +endif +ifeq ($(CHECK_LIBFTDI), yes) + @./config.sh libftdi +endif +ifeq ($(CONFIG_LINUX_SPI), yes) + @./config.sh linuxspi +endif + +-include .availablefeatures + FEATURE_CFLAGS += -D'CONFIG_DEFAULT_PROGRAMMER=$(CONFIG_DEFAULT_PROGRAMMER)' ifeq ($(CONFIG_INTERNAL), yes) @@ -421,27 +543,21 @@ PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif -NEED_PCI := yes endif ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'CONFIG_SERPROG=1' PROGRAMMER_OBJS += serprog.o -NEED_SERIAL := yes -NEED_NET := yes endif ifeq ($(CONFIG_RAYER_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_RAYER_SPI=1' PROGRAMMER_OBJS += rayer_spi.o -# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct. -NEED_PCI := yes endif ifeq ($(CONFIG_PONY_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_PONY_SPI=1' PROGRAMMER_OBJS += pony_spi.o -NEED_SERIAL := yes endif ifeq ($(CONFIG_BITBANG_SPI), yes) @@ -452,36 +568,29 @@ ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'CONFIG_NIC3COM=1' PROGRAMMER_OBJS += nic3com.o -NEED_PCI := yes endif ifeq ($(CONFIG_GFXNVIDIA), yes) FEATURE_CFLAGS += -D'CONFIG_GFXNVIDIA=1' PROGRAMMER_OBJS += gfxnvidia.o -NEED_PCI := yes endif ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'CONFIG_SATASII=1' PROGRAMMER_OBJS += satasii.o -NEED_PCI := yes endif ifeq ($(CONFIG_ATAHPT), yes) FEATURE_CFLAGS += -D'CONFIG_ATAHPT=1' PROGRAMMER_OBJS += atahpt.o -NEED_PCI := yes endif ifeq ($(CONFIG_FT2232_SPI), yes) -FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") -# This is a totally ugly hack. -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'CONFIG_FT2232_SPI=1'") -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") -FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") +FEATURE_CFLAGS += -D'CONFIG_FT2232_SPI=1' +ifeq ($(FT232H), yes) +FEATURE_CFLAGS += -D'HAVE_FT232H=1' +endif PROGRAMMER_OBJS += ft2232_spi.o -# We can't set NEED_USB here because that would transform libftdi auto-enabling -# into a hard requirement for libusb, defeating the purpose of auto-enabling. endif ifeq ($(CONFIG_DUMMY), yes) @@ -492,75 +601,64 @@ ifeq ($(CONFIG_DRKAISER), yes) FEATURE_CFLAGS += -D'CONFIG_DRKAISER=1' PROGRAMMER_OBJS += drkaiser.o -NEED_PCI := yes endif ifeq ($(CONFIG_NICREALTEK), yes) FEATURE_CFLAGS += -D'CONFIG_NICREALTEK=1' PROGRAMMER_OBJS += nicrealtek.o -NEED_PCI := yes endif ifeq ($(CONFIG_NICNATSEMI), yes) FEATURE_CFLAGS += -D'CONFIG_NICNATSEMI=1' PROGRAMMER_OBJS += nicnatsemi.o -NEED_PCI := yes endif ifeq ($(CONFIG_NICINTEL), yes) FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1' PROGRAMMER_OBJS += nicintel.o -NEED_PCI := yes endif ifeq ($(CONFIG_NICINTEL_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_NICINTEL_SPI=1' PROGRAMMER_OBJS += nicintel_spi.o -NEED_PCI := yes endif ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o -NEED_PCI := yes endif ifeq ($(CONFIG_BUSPIRATE_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BUSPIRATE_SPI=1' PROGRAMMER_OBJS += buspirate_spi.o -NEED_SERIAL := yes endif ifeq ($(CONFIG_DEDIPROG), yes) FEATURE_CFLAGS += -D'CONFIG_DEDIPROG=1' PROGRAMMER_OBJS += dediprog.o -NEED_USB := yes endif ifeq ($(CONFIG_SATAMV), yes) FEATURE_CFLAGS += -D'CONFIG_SATAMV=1' PROGRAMMER_OBJS += satamv.o -NEED_PCI := yes endif ifeq ($(CONFIG_LINUX_SPI), yes) -# This is a totally ugly hack. -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "LINUX_SPI_SUPPORT := yes" .features && printf "%s" "-D'CONFIG_LINUX_SPI=1'") +FEATURE_CFLAGS += -D'CONFIG_LINUX_SPI=1' PROGRAMMER_OBJS += linux_spi.o endif -ifeq ($(NEED_SERIAL), yes) +ifneq ($(NEED_SERIAL), ) LIB_OBJS += serial.o endif -ifeq ($(NEED_NET), yes) +ifneq ($(NEED_NET), ) ifeq ($(TARGET_OS), SunOS) LIBS += -lsocket endif endif -ifeq ($(NEED_PCI), yes) -CHECK_LIBPCI = yes +ifneq ($(NEED_PCI), ) FEATURE_CFLAGS += -D'NEED_PCI=1' PROGRAMMER_OBJS += pcidev.o physmap.o hwaccess.o ifeq ($(TARGET_OS), NetBSD) @@ -589,32 +687,45 @@ endif endif -ifeq ($(NEED_USB), yes) -CHECK_LIBUSB0 = yes +ifneq ($(NEED_USB), ) FEATURE_CFLAGS += -D'NEED_USB=1' USBLIBS := $(shell pkg-config --libs libusb 2>/dev/null || printf "%s" "-lusb") endif +ifneq ($(NEED_FTDI), ) +FEATURE_CFLAGS += -D'NEED_FTDI=1' +FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || libftdi-config --libs 2>/dev/null || printf "%s" "-lftdi") +endif + +ifneq ($(NEED_IOPORT_ACCESS), ) +FEATURE_CFLAGS += -D'NEED_IOPORT_ACCESS=1' +PROGRAMMER_OBJS += hwaccess.o +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' CLI_OBJS += print_wiki.o endif -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "UTSNAME := yes" .features && printf "%s" "-D'HAVE_UTSNAME=1'") +ifeq ($(UTSNAME), yes) +FEATURE_CFLAGS += -D'HAVE_UTSNAME=1' +endif # We could use PULLED_IN_LIBS, but that would be ugly. -FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") +ifeq ($(NEEDLIBZ), yes) +FEATURE_LIBS += -lz +endif -LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +LIBFLASHROM_OBJS = $(CHIP_OBJS) $(sort $(PROGRAMMER_OBJS)) $(LIB_OBJS) OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) -all: hwlibs features $(PROGRAM)$(EXEC_SUFFIX) +all: $(PROGRAM)$(EXEC_SUFFIX) ifeq ($(ARCH), x86) @+$(MAKE) -C util/ich_descriptors_tool/ TARGET_OS=$(TARGET_OS) EXEC_SUFFIX=$(EXEC_SUFFIX) endif $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) - $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(FEATURE_LIBS) $(LIBS) $(PCILIBS) $(USBLIBS) + $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(FTDILIBS) $(USBLIBS) $(PCILIBS) $(FEATURE_LIBS) $(LIBS) libflashrom.a: $(LIBFLASHROM_OBJS) $(AR) rcs $@ $^ @@ -625,7 +736,11 @@ # stored files, they can be handled here as well. TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") -%.o: %.c .features +%.o: %.c +ifeq ($(wildcard .availablefeatures), ) + @echo 'You have to run "make config" first' + @false +endif $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FLASHROM_CFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. @@ -636,7 +751,7 @@ @+$(MAKE) -C util/ich_descriptors_tool/ clean distclean: clean - rm -f .features .libdeps + rm -f .availablefeatures strip: $(PROGRAM)$(EXEC_SUFFIX) $(STRIP) $(STRIP_ARGS) $(PROGRAM)$(EXEC_SUFFIX) @@ -699,60 +814,6 @@ endef export LIBUSB0_TEST -hwlibs: compiler - @printf "" > .libdeps -ifeq ($(CHECK_LIBPCI), yes) - @printf "Checking for libpci headers... " - @echo "$$LIBPCI_TEST" > .test.c - @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install libpci headers (package pciutils-devel)."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o; exit 1) - @printf "Checking if libpci is present and sufficient... " - @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) >/dev/null && \ - echo "yes." || ( echo "no."; \ - printf "Checking if libz+libpci are present and sufficient..."; \ - $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) -lz >/dev/null && \ - ( echo "yes."; echo "NEEDLIBZ := yes" > .libdeps ) || ( echo "no."; echo; \ - echo "Please install libpci (package pciutils) and/or libz."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) ) - @rm -f .test.c .test.o .test$(EXEC_SUFFIX) -endif -ifeq ($(CHECK_LIBUSB0), yes) - @printf "Checking for libusb-0.1/libusb-compat headers... " - @echo "$$LIBUSB0_TEST" > .test.c - @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install libusb-0.1 headers or libusb-compat headers."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o; exit 1) - @printf "Checking if libusb-0.1 is usable... " - @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS) >/dev/null && \ - echo "yes." || ( echo "no."; \ - echo "Please install libusb-0.1 or libusb-compat."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) - @rm -f .test.c .test.o .test$(EXEC_SUFFIX) -endif - -.features: features - -# If a user does not explicitly request a non-working feature, we should -# silently disable it. However, if a non-working (does not compile) feature -# is explicitly requested, we should bail out with a descriptive error message. -# We also have to check that at least one programmer driver is enabled. -featuresavailable: -ifeq ($(PROGRAMMER_OBJS),) - @echo "You have to enable at least one programmer driver!" - @false -endif -ifneq ($(UNSUPPORTED_FEATURES), ) - @echo "The following features are unavailable on your machine: $(UNSUPPORTED_FEATURES)" - @false -endif - define FTDI_TEST #include <ftdi.h> struct ftdi_context *ftdic = NULL; @@ -771,60 +832,47 @@ endef export FTDI_232H_TEST -define UTSNAME_TEST -#include <sys/utsname.h> -struct utsname osinfo; +define LINUX_SPI_TEST +#include <linux/types.h> +#include <linux/spi/spidev.h> + int main(int argc, char **argv) { (void) argc; (void) argv; - uname (&osinfo); return 0; } endef -export UTSNAME_TEST +export LINUX_SPI_TEST -define LINUX_SPI_TEST -#include <linux/types.h> -#include <linux/spi/spidev.h> - +define UTSNAME_TEST +#include <sys/utsname.h> +struct utsname osinfo; int main(int argc, char **argv) { (void) argc; (void) argv; + uname (&osinfo); return 0; } endef -export LINUX_SPI_TEST +export UTSNAME_TEST -features: compiler - @echo "FEATURES := yes" > .features.tmp -ifeq ($(CONFIG_FT2232_SPI), yes) - @printf "Checking for FTDI support... " - @echo "$$FTDI_TEST" > .featuretest.c - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ - ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) - @printf "Checking for FT232H support in libftdi... " - @echo "$$FTDI_232H_TEST" >> .featuretest.c - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ - ( echo "found."; echo "FT232H := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "FT232H := no" >> .features.tmp ) +export CC + +# If a user does not explicitly request a non-working feature, we should +# silently disable it. However, if a non-working (does not compile) feature +# is explicitly requested, we should bail out with a descriptive error message. +# We also have to check that at least one programmer driver is enabled. +featuresavailable: +ifeq ($(PROGRAMMER_OBJS),) + @echo "You have to enable at least one programmer driver!" + @false endif -ifeq ($(CONFIG_LINUX_SPI), yes) - @printf "Checking if Linux SPI headers are present... " - @echo "$$LINUX_SPI_TEST" > .featuretest.c - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ - ( echo "yes."; echo "LINUX_SPI_SUPPORT := yes" >> .features.tmp ) || \ - ( echo "no."; echo "LINUX_SPI_SUPPORT := no" >> .features.tmp ) +ifneq ($(UNSUPPORTED_TARGET_FEATURES), ) + @echo "The following features are unavailable on the target machine: $(UNSUPPORTED_TARGET_FEATURES)" + @false endif - @printf "Checking for utsname support... " - @echo "$$UTSNAME_TEST" > .featuretest.c - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ - ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) - @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features - @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) install: $(PROGRAM)$(EXEC_SUFFIX) mkdir -p $(DESTDIR)$(PREFIX)/sbin @@ -849,6 +897,10 @@ libpayload: clean make CC="CC=i386-elf-gcc lpgcc" AR=i386-elf-ar RANLIB=i386-elf-ranlib -.PHONY: all clean distclean compiler hwlibs features export tarball dos featuresavailable +.PHONY: all clean distclean compiler config export tarball dos featuresavailable +.EXPORT_ALL_VARIABLES: + +-include .availablefeatures + -include $(OBJS:.o=.d) Index: flashrom-Makefile_harddependencies_soft/config.sh =================================================================== --- flashrom-Makefile_harddependencies_soft/config.sh (Revision 0) +++ flashrom-Makefile_harddependencies_soft/config.sh (Revision 0) @@ -0,0 +1,199 @@ +#!/bin/sh +libpci() { + printf "Checking for libpci headers... " + echo "$LIBPCI_TEST" > .test.c + ${CC} -c ${CPPFLAGS} ${CFLAGS} .test.c -o .test.o >.testresult 2>&1 && { + echo "found." + } || { + echo "not found." + if [ ${CHECK_LIBPCI} = yes ]; then + echo + echo "Please install libpci headers (package pciutils-devel)" + echo "or disable the following features: ${NEED_PCI}" + echo "See README for more information." + echo + rm -f .test.o + exit 1 + else + for a in ${NEED_PCI}; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: ${NEED_PCI}" + echo "See README for more information." + echo + rm -f .test.c .test.o + return 0 + fi + } + printf "Checking if libpci is present and sufficient... " + ${CC} ${LDFLAGS} .test.o -o .test${EXEC_SUFFIX} ${PCILIBS} ${LIBS} >.testresult 2>&1 && { + echo "yes." + } || { + echo "no." + printf "Checking if libz+libpci are present and sufficient..." + ${CC} ${LDFLAGS} .test.o -o .test${EXEC_SUFFIX} ${PCILIBS} -lz ${LIBS} >.testresult 2>&1 && { + echo "yes." + echo "NEEDLIBZ := yes" > .availablefeatures + } || { + echo "no." + if [ ${CHECK_LIBPCI} = yes ]; then + echo + echo "Please install libpci (package pciutils) and/or libz" + echo "or disable the following features: ${NEED_PCI}" + echo "See README for more information." + echo + rm -f test.o .test${EXEC_SUFFIX} + exit 1 + else + for a in ${NEED_PCI}; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: ${NEED_PCI}" + echo "See README for more information." + echo + rm -f .test.c .test.o; .test${EXEC_SUFFIX} + return 0 + fi + } + } + rm -f .test.c .test.o .test${EXEC_SUFFIX} .testresult +} + +libusb0() { + printf "Checking for libusb-0.1/libusb-compat headers... " + echo "$LIBUSB0_TEST" > .test.c + ${CC} -c ${CPPFLAGS} ${CFLAGS} .test.c -o .test.o >.testresult 2>&1 && { + echo "found." + } || { + echo "not found." + if [ ${CHECK_LIBUSB0} = yes ]; then + echo + echo "Please install libusb-0.1 headers or libusb-compat headers" + echo "or disable the following features: ${NEED_USB}" + echo "See README for more information." + echo + rm -f .test.o + exit 1 + else + for a in ${NEED_USB}; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: ${NEED_USB}" + echo "See README for more information." + echo + rm -f .test.c .test.o + return 0 + fi + } + printf "Checking if libusb-0.1/libusb-compat is usable... " + ${CC} ${LDFLAGS} .test.o -o .test${EXEC_SUFFIX} ${USBLIBS} ${LIBS} >.testresult 2>&1 && { + echo "yes." + } || { + echo "no." + if [ ${CHECK_LIBUSB0} = yes ]; then + echo + echo "Please install libusb-0.1 or libusb-compat" + echo "or disable the following features: ${NEED_USB}" + echo "See README for more information." + echo + rm -f .test.o .test${EXEC_SUFFIX} + exit 1 + else + for a in ${NEED_USB}; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: ${NEED_USB}" + echo "See README for more information." + echo + rm -f .test.c .test.o + return 0 + fi + } + rm -f .test.c .test.o .test${EXEC_SUFFIX} .testresult +} + +libftdi() { + printf "Checking for libftdi support... " + echo "$FTDI_TEST" > .test.c + ${CC} ${CPPFLAGS} ${CFLAGS} ${LDFLAGS} .test.c -o .test${EXEC_SUFFIX} ${FTDILIBS} ${LIBS} >.testresult 2>&1 && { + echo "found." + } || { + echo "not found." + if [ ${CHECK_LIBFTDI} = yes ]; then + echo + echo "Please install libftdi headers" + echo "or disable the following features: ${NEED_FTDI}" + echo "See README for more information." + echo + rm -f .test${EXEC_SUFFIX} + exit 1 + else + for a in ${NEED_FTDI}; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: ${NEED_FTDI}" + echo "See README for more information." + echo + rm -f .test.c .test${EXEC_SUFFIX} + return 0 + fi + } + printf "Checking for FT232H support in libftdi... " + echo "$FTDI_232H_TEST" >> .test.c + ${CC} ${CPPFLAGS} ${CFLAGS} ${LDFLAGS} .test.c -o .test${EXEC_SUFFIX} ${FTDILIBS} ${LIBS} >.testresult 2>&1 && { + echo "found." + echo "FT232H := yes" >> .availablefeatures + } || { + echo "not found." + } + rm -f .test.c .test${EXEC_SUFFIX} .testresult +} + +linuxspi() { + printf "Checking for Linux kernel SPI headers... " + echo "$LINUX_SPI_TEST" > .test.c + ${CC} ${CPPFLAGS} ${CFLAGS} ${LDFLAGS} .test.c -o .test${EXEC_SUFFIX} >.testresult 2>&1 && { + echo "found." + } || { + echo "not found." + if [ ${CONFIG_LINUX_SPI} = yes ]; then + echo + echo "Please install Linux kernel SPI headers (linux/spi/spidev.h, part of recent glibc)" + echo "or disable the following features: CONFIG_LINUX_SPI" + echo "See README for more information." + echo + rm -f .test${EXEC_SUFFIX} + exit 1 + else + for a in CONFIG_LINUX_SPI; do + echo "${a} := no" >> .availablefeatures + done + echo + echo "The following features have been automatically disabled: CONFIG_LINUX_SPI" + echo "See README for more information." + echo + rm -f .test.c .test${EXEC_SUFFIX} + return 0 + fi + } + rm -f .test.c .test${EXEC_SUFFIX} .testresult +} + +utsname() { + printf "Checking for utsname support... " + echo "$UTSNAME_TEST" > .test.c + ${CC} ${CPPFLAGS} ${CFLAGS} ${LDFLAGS} .test.c -o .test${EXEC_SUFFIX} >/dev/null 2>&1 && { + echo "found." + echo "UTSNAME := yes" >> .availablefeatures + } || { + echo "not found." + } + rm -f .test.c .test${EXEC_SUFFIX} .testresult +} + +eval $1 Eigenschaftsänderungen: flashrom-Makefile_harddependencies_soft/config.sh ___________________________________________________________________ Hinzugefügt: svn:executable + * -- http://www.hailfinger.org/

1 1

Report: Intel DQ77KB KBQ7710H.86A.0049.2013.0130.1732 write
by dpcimanager＠users.sourceforge.net 12 Feb '13

12 Feb '13

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): /Volumes/USB/[Megafileupload]DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -w /var/folders/0g/vk1bx8k94r7_3_p_tllzvqvm0000gn/T/DPCIcw3meF.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 459M loops per second, 10 myus = 12 us, 100 myus = 102 us, 1000 myus = 1028 us, 10000 myus = 10668 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ77KB" DMI string baseboard-version: "AAG40294-401" DMI string chassis-type: "Desktop" Found chipset "Intel Q77" with PCI ID 8086:1e47. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x2a: BIOS Lock Enable: enabled, BIOS Write Enable: disabled Warning: BIOS region SMM protection is enabled! Warning: Setting Bios Control at 0xdc from 0x2a to 0x0b on Q77 failed. New value is 0x2a. Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0bff05c0 FREG1: BIOS region (0x005c0000-0x00bfffff) is read-write. 0x5C: 0x05bf0003 FREG2: Warning: Management Engine region (0x00003000-0x005bffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x03040103 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 4 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 2 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x0930001c FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 density: 4 MB Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x0bff05c0 FLREG2 0x05bf0003 FLREG3 0x00020001 FLREG4 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x005c0000 - 0x00bfffff Region 2 (ME ) 0x00003000 - 0x005bffff Region 3 (GbE ) 0x00001000 - 0x00002fff Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing due to multiple flash chips detected. SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 12288 kB. There is only one partition containing the whole address space (0x000000 - 0xbfffff). There are 3072 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific). Write/erase is not working yet on your programmer in its current configuration. Aborting. Restoring MMIO space at 0x10ef718a0 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

Re: [flashrom] Fwd: BIOS Write Enable bit problem.
by Andrew Goodbody 11 Feb '13

11 Feb '13

On 10/02/13 00:45, Rich Futyma wrote: > Would happen to know which linux driver handles this interrupt? SMM code is loaded into SMRAM during BIOS POST. Then the access to SMRAM is locked so that SMRAM is only visible when an SMI is active. The CPU cannot access SMRAM when no SMI is active. The CPU immediately starts to execute code from SMRAM once it receives the SMI. There is no Linux code involved, this is all initialised before any OS code is loaded. > Also, do you know where is this "correct handshake" described? It seems > that once bit 1 is set it can only be cleared by the reset. No. This handshake is not public knowledge AFAIK. It would not be much of a protection mechanism if everyone, including the virus writers, knew how to bypass it. I would expect the handshake to involve cryptography as well. Andrew

2 1

Re: [flashrom] a serious problem to solve
by Idwer Vollering 10 Feb '13

10 Feb '13

2013/2/10 Henry Blanco Lores <hblanco2009(a)gmail.com>: > Hi Idwer, do you finally have any idea if the problem could be solved? > Henry Pleasse read, and reply to, the mailinglist for questions, don't reply to me or others without adding flashrom(a)flashrom.org to To: or Cc:. Thanks :) http://www.coreboot.org/pipermail/flashrom/2013-February/thread.html#10519 >>> > _______________________________________________ >>> > flashrom mailing list >>> > flashrom(a)flashrom.org >>> > http://www.flashrom.org/mailman/listinfo/flashrom >> >> >

1 0

Re: [flashrom] Fwd: BIOS Write Enable bit problem.
by Andrew Goodbody 10 Feb '13

10 Feb '13

On 08/02/13 23:47, Rich Futyma wrote: > Does anyone know why bit 0 in the BIOS Control register cannot be set using > Intel® X79 Express Chipset. This is what I get when running: > flashrom -r /tmp/bios.rom -p internal or flashrom -w xx.rom -p internal > > *Warning: Setting Bios Control at 0xdc from 0x2a to 0x0b on X79 failed.* > *New value is 0x2a.* You can see that bit 1 is already set. This will generate an SMI when you attempt to set bit 0. There will be SMM code that will reset bit 0 if you have not performed the correct handshake beforehand. This is a protection mechanism to prevent unauthorised modification of the BIOS. Andrew

2 1

chipset "NVIDIA MCP78S"
by Алексей Кардапольцев 09 Feb '13

09 Feb '13

You're asking for email a report to flashrom(a)flashrom.org including a verbose (-V) log. Here it is: ┌─[~] └─[alexey@home]: sudo flashrom -V -w 1402.BIN flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (3 args): flashrom -V -w 1402.BIN Calibrating delay loop... OS timer resolution is 1 usecs, 402M loops per second, delay more than 10% too short (got 37% of expected delay), recalculating... 324M loops per second, delay more than 10% too short (got 29% of expected delay), recalculating... 327M loops per second, delay more than 10% too short (got 30% of expected delay), recalculating... 327M loops per second, delay more than 10% too short (got 30% of expected delay), recalculating... 328M loops per second, delay loop is unreliable, trying to continue 10 myus = 3 us, 100 myus = 30 us, 1000 myus = 298 us, 10000 myus = 9494 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M3N78 PRO" DMI string baseboard-version: "1.XX" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8716 on port 0x2e Found chipset "NVIDIA MCP78S" with PCI ID 10de:075c. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:0752 at 00:01:1 MCP SPI BAR is at 0xfdf80000 Mapping NVIDIA MCP6x SPI at 0xfdf80000, unaligned size 0x544. SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. No IT87* serial flash segment enabled. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Chip status register is 00 Found Eon flash chip "EN25F80" (1024 kB, SPI) at physical address 0xfff00000. Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0x1c, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0x1c, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3114 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x1c, id2 0x13 Found Eon flash chip "EN25F80" (1024 kB, SPI). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EW, 0x001000-0x001fff:E, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:E, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:EW, 0x021000-0x021fff:EW, 0x022000-0x022fff:EW, 0x023000-0x023fff:EW, 0x024000-0x024fff:EW, 0x025000-0x025fff:EW, 0x026000-0x026fff:EW, 0x027000-0x027fff:EW, 0x028000-0x028fff:EW, 0x029000-0x029fff:EW, 0x02a000-0x02afff:EW, 0x02b000-0x02bfff:EW, 0x02c000-0x02cfff:EW, 0x02d000-0x02dfff:EW, 0x02e000-0x02efff:EW, 0x02f000-0x02ffff:EW, 0x030000-0x030fff:EW, 0x031000-0x031fff:EW, 0x032000-0x032fff:EW, 0x033000-0x033fff:EW, 0x034000-0x034fff:EW, 0x035000-0x035fff:EW, 0x036000-0x036fff:EW, 0x037000-0x037fff:EW, 0x038000-0x038fff:EW, 0x039000-0x039fff:EW, 0x03a000-0x03afff:EW, 0x03b000-0x03bfff:EW, 0x03c000-0x03cfff:EW, 0x03d000-0x03dfff:EW, 0x03e000-0x03efff:EW, 0x03f000-0x03ffff:EW, 0x040000-0x040fff:EW, 0x041000-0x041fff:EW, 0x042000-0x042fff:EW, 0x043000-0x043fff:EW, 0x044000-0x044fff:EW, 0x045000-0x045fff:EW, 0x046000-0x046fff:EW, 0x047000-0x047fff:EW, 0x048000-0x048fff:EW, 0x049000-0x049fff:EW, 0x04a000-0x04afff:EW, 0x04b000-0x04bfff:EW, 0x04c000-0x04cfff:EW, 0x04d000-0x04dfff:EW, 0x04e000-0x04efff:EW, 0x04f000-0x04ffff:EW, 0x050000-0x050fff:EW, 0x051000-0x051fff:EW, 0x052000-0x052fff:EW, 0x053000-0x053fff:EW, 0x054000-0x054fff:EW, 0x055000-0x055fff:EW, 0x056000-0x056fff:EW, 0x057000-0x057fff:EW, 0x058000-0x058fff:EW, 0x059000-0x059fff:EW, 0x05a000-0x05afff:EW, 0x05b000-0x05bfff:EW, 0x05c000-0x05cfff:EW, 0x05d000-0x05dfff:EW, 0x05e000-0x05efff:EW, 0x05f000-0x05ffff:EW, 0x060000-0x060fff:EW, 0x061000-0x061fff:EW, 0x062000-0x062fff:EW, 0x063000-0x063fff:EW, 0x064000-0x064fff:EW, 0x065000-0x065fff:EW, 0x066000-0x066fff:EW, 0x067000-0x067fff:EW, 0x068000-0x068fff:EW, 0x069000-0x069fff:EW, 0x06a000-0x06afff:EW, 0x06b000-0x06bfff:EW, 0x06c000-0x06cfff:EW, 0x06d000-0x06dfff:EW, 0x06e000-0x06efff:EW, 0x06f000-0x06ffff:EW, 0x070000-0x070fff:EW, 0x071000-0x071fff:EW, 0x072000-0x072fff:EW, 0x073000-0x073fff:EW, 0x074000-0x074fff:EW, 0x075000-0x075fff:EW, 0x076000-0x076fff:EW, 0x077000-0x077fff:EW, 0x078000-0x078fff:EW, 0x079000-0x079fff:EW, 0x07a000-0x07afff:EW, 0x07b000-0x07bfff:EW, 0x07c000-0x07cfff:EW, 0x07d000-0x07dfff:EW, 0x07e000-0x07efff:EW, 0x07f000-0x07ffff:EW, 0x080000-0x080fff:EW, 0x081000-0x081fff:EW, 0x082000-0x082fff:EW, 0x083000-0x083fff:EW, 0x084000-0x084fff:EW, 0x085000-0x085fff:EW, 0x086000-0x086fff:EW, 0x087000-0x087fff:EW, 0x088000-0x088fff:EW, 0x089000-0x089fff:EW, 0x08a000-0x08afff:EW, 0x08b000-0x08bfff:EW, 0x08c000-0x08cfff:EW, 0x08d000-0x08dfff:EW, 0x08e000-0x08efff:EW, 0x08f000-0x08ffff:EW, 0x090000-0x090fff:EW, 0x091000-0x091fff:EW, 0x092000-0x092fff:EW, 0x093000-0x093fff:EW, 0x094000-0x094fff:EW, 0x095000-0x095fff:EW, 0x096000-0x096fff:EW, 0x097000-0x097fff:EW, 0x098000-0x098fff:EW, 0x099000-0x099fff:EW, 0x09a000-0x09afff:EW, 0x09b000-0x09bfff:EW, 0x09c000-0x09cfff:EW, 0x09d000-0x09dfff:EW, 0x09e000-0x09efff:EW, 0x09f000-0x09ffff:EW, 0x0a0000-0x0a0fff:EW, 0x0a1000-0x0a1fff:EW, 0x0a2000-0x0a2fff:E, 0x0a3000-0x0a3fff:E, 0x0a4000-0x0a4fff:E, 0x0a5000-0x0a5fff:E, 0x0a6000-0x0a6fff:E, 0x0a7000-0x0a7fff:S, 0x0a8000-0x0a8fff:S, 0x0a9000-0x0a9fff:S, 0x0aa000-0x0aafff:S, 0x0ab000-0x0abfff:S, 0x0ac000-0x0acfff:S, 0x0ad000-0x0adfff:S, 0x0ae000-0x0aefff:S, 0x0af000-0x0affff:S, 0x0b0000-0x0b0fff:S, 0x0b1000-0x0b1fff:S, 0x0b2000-0x0b2fff:S, 0x0b3000-0x0b3fff:S, 0x0b4000-0x0b4fff:S, 0x0b5000-0x0b5fff:S, 0x0b6000-0x0b6fff:S, 0x0b7000-0x0b7fff:S, 0x0b8000-0x0b8fff:S, 0x0b9000-0x0b9fff:S, 0x0ba000-0x0bafff:S, 0x0bb000-0x0bbfff:S, 0x0bc000-0x0bcfff:S, 0x0bd000-0x0bdfff:S, 0x0be000-0x0befff:S, 0x0bf000-0x0bffff:S, 0x0c0000-0x0c0fff:S, 0x0c1000-0x0c1fff:S, 0x0c2000-0x0c2fff:S, 0x0c3000-0x0c3fff:S, 0x0c4000-0x0c4fff:S, 0x0c5000-0x0c5fff:S, 0x0c6000-0x0c6fff:S, 0x0c7000-0x0c7fff:S, 0x0c8000-0x0c8fff:S, 0x0c9000-0x0c9fff:S, 0x0ca000-0x0cafff:S, 0x0cb000-0x0cbfff:S, 0x0cc000-0x0ccfff:S, 0x0cd000-0x0cdfff:S, 0x0ce000-0x0cefff:S, 0x0cf000-0x0cffff:S, 0x0d0000-0x0d0fff:S, 0x0d1000-0x0d1fff:S, 0x0d2000-0x0d2fff:S, 0x0d3000-0x0d3fff:S, 0x0d4000-0x0d4fff:S, 0x0d5000-0x0d5fff:S, 0x0d6000-0x0d6fff:S, 0x0d7000-0x0d7fff:S, 0x0d8000-0x0d8fff:S, 0x0d9000-0x0d9fff:S, 0x0da000-0x0dafff:W, 0x0db000-0x0dbfff:W, 0x0dc000-0x0dcfff:W, 0x0dd000-0x0ddfff:W, 0x0de000-0x0defff:W, 0x0df000-0x0dffff:W, 0x0e0000-0x0e0fff:EW, 0x0e1000-0x0e1fff:EW, 0x0e2000-0x0e2fff:EW, 0x0e3000-0x0e3fff:EW, 0x0e4000-0x0e4fff:EW, 0x0e5000-0x0e5fff:EW, 0x0e6000-0x0e6fff:EW, 0x0e7000-0x0e7fff:EW, 0x0e8000-0x0e8fff:EW, 0x0e9000-0x0e9fff:EW, 0x0ea000-0x0eafff:EW, 0x0eb000-0x0ebfff:EW, 0x0ec000-0x0ecfff:EW, 0x0ed000-0x0edfff:EW, 0x0ee000-0x0eefff:EW, 0x0ef000-0x0effff:EW, 0x0f0000-0x0f0fff:EW, 0x0f1000-0x0f1fff:EW, 0x0f2000-0x0f2fff:EW, 0x0f3000-0x0f3fff:EW, 0x0f4000-0x0f4fff:EW, 0x0f5000-0x0f5fff:EW, 0x0f6000-0x0f6fff:EW, 0x0f7000-0x0f7fff:EW, 0x0f8000-0x0f8fff:EW, 0x0f9000-0x0f9fff:EW, 0x0fa000-0x0fafff:EW, 0x0fb000-0x0fbfff:EW, 0x0fc000-0x0fcfff:S, 0x0fd000-0x0fdfff:S, 0x0fe000-0x0fefff:EW, 0x0ff000-0x0fffff:EW Erase/write done. Verifying flash... VERIFIED. -- Sincerely yours, Alexey Kardapoltsev. +7 (917) 777-10-60

1 0

Fwd: BIOS Write Enable bit problem.
by Rich Futyma 09 Feb '13

09 Feb '13

Guys, Does anyone know why bit 0 in the BIOS Control register cannot be set using Intel® X79 Express Chipset. This is what I get when running: flashrom -r /tmp/bios.rom -p internal or flashrom -w xx.rom -p internal *Warning: Setting Bios Control at 0xdc from 0x2a to 0x0b on X79 failed.* *New value is 0x2a.* The read command completes and I get the correct data, but subsequently when I try to erase and program my flash (./flashrom -w xx.rom -p internal:ich_spi_force=yes) I get FCERR (on the first sector erase) which implies that the BIOS is write protected. Thank you in advance for any advice. ---- Rich Futyma ** [image: Inline image 1] CONFIDENTIALITY This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity.

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Re: [flashrom] ASUS P5GC: BIOS erased after after `flashrom -r`f (was: a serious problem to solve)
by Paul Menzel 08 Feb '13

08 Feb '13

Dear Henry, Am Freitag, den 08.02.2013, 21:41 +0100 schrieb Henry Blanco Lores: > Hello guys, I have subscribed to this mailing list looking for some help > about the use of the flashrom tool. > The problem is this: > > A friend of mine who has just started using Linux, was testing some tools > and not reading carefully their corresponding manuals, he executed this > command: flashrom -r normally that should not cause any problems as it just tries to read the flash chip content. flashrom is very careful to not break anything, so it is very unlikely that the problem was caused by this command. > and this seems to have erased the BIOS of his PC. This is my guess because > he just told me by phone that not even the video signal was working. You have to be very specific. 1. What Linux distribution did your friend use? What version of flashrom? The packaged one? 2. What did your friend exactly do? Did he see any error messages from flashrom. I guess he just shut the system down? > His motherboard is an ASUS P5GC. A similar board seems to be supported [1]. So the problem is even stranger. > Is it possible to recover the BIOS back to the previous state?? If it was really deleted/erased or a bad image was flashed, then you have to reprogram the chip either with a flash chip programmer. One way is to find a motherboard where the chip fits and reprogram it there by hot swapping it. If that is not possible ask around in your local hacker community or find a shop which does it. > Please, I will be looking forward for your comments. I wish you good luck with recovery! You should also join the #flashrom IRC channel on irc.freenode.net. Thanks, Paul [1] http://flashrom.org/Supported_hardware

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Re: [flashrom] a serious problem to solve
by Idwer Vollering 08 Feb '13

08 Feb '13

2013/2/8 Henry Blanco Lores <hblanco2009(a)gmail.com>: > Hello guys, I have subscribed to this mailing list looking for some help > about the use of the flashrom tool. > The problem is this: > > A friend of mine who has just started using Linux, was testing some tools > and not reading carefully their corresponding manuals, he executed this > command: flashrom -r > > and this seems to have erased the BIOS of his PC. This is my guess because > he just told me by phone that not even the video signal was working. His > motherboard is an ASUS P5GC. Is it possible to recover the BIOS back to the > previous state?? The above command, 'flashrom -r', will not erase a flash chip. Have your friend either power cycle his machine or remove the mainboard battery (CMOS reset) with mains disconnected. Given the fact that the parameter '-p internal' was not used, he was using an old version of flashrom, version 0.9.3 or older. > > Please, I will be looking forward for your comments. > Thanks in advance. > > H. > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

1 0

a serious problem to solve
by Henry Blanco Lores 08 Feb '13

08 Feb '13

Hello guys, I have subscribed to this mailing list looking for some help about the use of the flashrom tool. The problem is this: A friend of mine who has just started using Linux, was testing some tools and not reading carefully their corresponding manuals, he executed this command: flashrom -r and this seems to have erased the BIOS of his PC. This is my guess because he just told me by phone that not even the video signal was working. His motherboard is an ASUS P5GC. Is it possible to recover the BIOS back to the previous state?? Please, I will be looking forward for your comments. Thanks in advance. H.

1 0

Re: [flashrom] flashrom ignoring ROM layout region
by Stefan Tauner 08 Feb '13

08 Feb '13

On Thu, 7 Feb 2013 16:09:45 -0800 John Gainsborough <jgindc1(a)gmail.com> wrote: > Hi Stefan. > > I am now attempting to write to a flashrom using the layout/region > approach. I need to write a region from a 4MB ROM to the beginning of an > 8MB ROM. > The region image from the 4MB ROM is 4,128,768 bytes == 0x3f0000 long and > this file is called image1. > I have defined the 8MB ROM layout in file called romlayout_8MB to be: > > 000000:3effff main > 3f0000:7fffff remainder > > i.e I want to place the contents of file image1 in to the 8MB ROM region > defined as main. > > I invoked flashrom as follows: > > flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=250k -l romlayout_8MB > -i main -w image1 > > The flash ROM is detected correctly, delay calculated, but then flashrom > immediately returns the error: > "image size doesn't match". > > As always, guidance/suggestions gratefully received. That's one of the other things my patches fix :) The image you supply with -v/-r/-w is always used to present a mapping of the whole chip. The layout information is only used to select the address range inside that mapping. So for vanilla flashrom you have to create an 8MB file and fill the first 4MB with the content you want and continue as you have done. With my patches one can add an image name to any -i parameter (e.g. -i main:main.img) which is then mapped to the corresponding offset. IIRC one has still to supply a whole image with the correct size, but if the needed ranges are also present as "-i images" then it would not be used at all. Similar for the read operations: it would create a whole image with a lot of 0xFFs outside the selected regions and smaller/exact files for the "-i images". Maybe I have some time at the weekend to integrate the patches. I think there is consensus that we want them in and they have been tested by a number of people, so i think it should not break too much :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 2

operation details and future changes (was: flashrom ignoring ROM layout region)
by Stefan Tauner 08 Feb '13

08 Feb '13

On Fri, 8 Feb 2013 11:08:21 +0100 Mark Marshall <markmarshall14(a)gmail.com> wrote: Hi Mark, > I too would love for these changes to go in. I'm currently working with a > 64MB flash, and > I've got a number of problems, one of which is that flashrom tries to read > the entire flash > before doing anything (which will never be what I want...). It does so to be able to skip blocks that have the wanted content already and to be able to tell you if anything has changed in the case of an error (not so important on external programmes, but very interesting for people writing their live BIOSes and seeing errors). Usually reading does take way less time than erasing/writing or might even speed up the whole process. ATM there is no way to disable this behavior but we plan to do so and IIRC a part of the mentioned patch set is a first step into that direction. > The other problems are: > - That most of flashrom seems to be limited to 2^24 address bits. > (this is relatively easy to fix) We will see about that :) We are of course aware that this is needed quite soon. Do you want to help us with this (mostly testing, but if you like you can also try to create the needed patch)? > - That flashrom thinks a page is always 256 byes (I think I've found > most cases of this, but I'm not sure. What's the granularity flag > for? The flag is there to fix exactly this :) See also http://patchwork.coreboot.org/patch/3757/ Not many chips need this and so we never moved into this direction... do you really need it? > I've also found that flashrom doesn't always do what I expect, and I'm not > sure if this is > by design or not. for instance, if I want to erase my entire flash chip, > it ends up calling > the sector erase on each sector, not by doing a chip-erase? Are these > types of things > written down anywhere? We try to erase the smallest possible blocks first (in order of the eraser array of the chip definition(s) in flashchips.c. This potentially allows to skip writing of block as explained above. It is of course rather useless for the -E/--erase operation, but the code is shared and no one complained yet IIRC (or sent a patch). Most of these details are not documented I think, but some are (in the manpage). Patches for the manpage are welcomed. Everyone is invited to edit the wiki too :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Added chipsets
by Николай Николаев 08 Feb '13

08 Feb '13

Added chipsets: AMIC A25LQ16 Eon EN25S64 Eon EN25S10 Eon EN25S20 Eon EN25S40 Eon EN25S80 Eon EN25QH256 Eon EN25QH128 Eon EN25S32 Eon EN25S16 GigaDevice GD25Q10 GigaDevice GD25Q512 GigaDevice GD25Q128B Numonyx (Micron) N25Q128A13 Numonyx (Micron) N25Q128A11 Numonyx (Micron) N25Q256A11 Numonyx (Micron) N25Q256A13 Numonyx (Micron) N25Q512A11 Numonyx (Micron) N25Q512A13 Numonyx (Micron) N25Q00AA13 Numonyx (Micron) M25PX80 Numonyx (Micron) M45PE16 Numonyx (Micron) M45PE80 Numonyx (Micron) M45PE40 Numonyx (Micron) M45PE10 Numonyx (Micron) M45PE20 Sanyo LE25FW403A Sanyo LE25FW418A Sanyo LE25FW806 Sanyo LE25FW808 Spansion S25FL204K Spansion S25FL128S Spansion S25FL256S Spansion S25FL512S Spansion S25FL208K Spansion S25FL116K Fixed wrong description for Sanyo LE25FW203A -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Re: [flashrom] flashrom OPCODES for SPI
by Николай Николаев 08 Feb '13

08 Feb '13

The SST25VF040B was added before the new naming scheme was implemented. We > did not want to break any existing software which depends on certain > strings. > Ok i support your fears. it is old chip and has a small capacity. { .vendor = "SST", .name = "SST25VF032B", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF032B, .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 128} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, }, .printlock = spi_prettyprint_status_register_sst25, /* TODO: check */ .unlock = spi_disable_blockprotect, .write = spi_aai_write, /* what do i see? - this is a fetch */ .read = spi_chip_read, .voltage = {2700, 3600}, }, for example: if i used chip MX25L3205 and i want to change it on SST25VF032B, that i can't reprogram chip because this chip didn't have a AAI OPcodes 0xAD (i can't change opcodes in SPI controller). But i know my controller has a standard codes for reading and page programming. Voltage can be important for external programmer usage. It's not much > effort to add it, anyway. > How will you choose voltage for external program if you want to program MX25L6439E and MX25U6435F? What value we will write to field voltage? > Some SST25VF040B chips identify using the REMS opcode, others use RDID. > Complain to the manufacturer :-) > Sorry but i can't found REMS code in documentation on this chip. Mayby you give me link on pdf and i will be study on my free time. 8) Support for this chip came before the new naming scheme. In the future, > part names like this will be written as "EN25Q80...P" where the dot '.' is > a wildcard for each letter which does not affect programming capabilities. > Ok how will you mark next chips MX25L6439E and MX25U6435F? That chips has a identical chip ID = 0x2537. if if will be MX25.64...(F) that i think it's don't readable. -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

1 0

Report: ASUSTeK P8H61-I 0504 read
by dpcimanager＠users.sourceforge.net 08 Feb '13

08 Feb '13

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Desktop/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r /var/folders/m0/d54vw1ks3yzg_05_5kvwdqgm0000gn/T/DPCIXKhC8I.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 470M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 10014 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P8H61-I" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8771 on port 0x2e Found chipset "Intel H61" with PCI ID 8086:1c5c. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc00: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. FREG2: Warning: Management Engine region (0x00001000-0x0017ffff) is locked. SME=0 0x08: 0x00182b77 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 0x58: 0x03ff0180 FREG1: BIOS region (0x00180000-0x003fffff) is read-write. 0x5C: 0x017f0001 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00000fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00002005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300023 FLILL 0x00000000 --- Details --- Component 1 density: 4 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x03ff0180 FLREG2 0x017f0001 FLREG3 0x00000fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00180000 - 0x003fffff Region 2 (ME ) 0x00001000 - 0x0017ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw SPI Read Configuration: prefetching disabled, caching enabled, OK. Super I/O ID 0x8771 is not on the list of flash capable controllers. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512, 64 kB: program_opcodes: preop=5006 optype=460b opmenu=05150302c79f0190 on-the-fly OPCODE (0x15) re-programmed, op-pos=2 probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Unknown SFDP-capable chip, 0 kB: program_opcodes: preop=5006 optype=462b opmenu=055a0302c79f0190 on-the-fly OPCODE (0x5A) re-programmed, op-pos=2 SFDP revision = 1.0 SFDP number of parameter headers is 1 (NPH = 0). SFDP parameter table header 0/0: ID 0x00, version 1.0 Length 36 B, Parameter Table Pointer 0x000080 Parsing JEDEC flash parameter table... 3-Byte only addressing. Status register is non-volatile and the standard does not allow vendors to tell us whether EWSR/WREN is needed for status register writes - assuming EWSR. Write chunk size is at least 64 B. Flash chip size is 4096 kB. Block eraser 0: 1024 x 4096 B with opcode 0x20 Tried to add a duplicate block eraser: 1024 x 4096 B with opcode 0x20. Block eraser 1: 128 x 32768 B with opcode 0x52 Block eraser 2: 64 x 65536 B with opcode 0xd8 done. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x3d, id2 0x5f, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0xd7, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0xd7, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x39, id2 0x31, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q32" (4096 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: Read operation failed! SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). FAILED. Restoring MMIO space at 0x1031be8a0 Restoring MMIO space at 0x1031be89c Restoring MMIO space at 0x1031be898 Restoring MMIO space at 0x1031be896 Restoring MMIO space at 0x1031be894 Restoring PCI config space for 00:1f:0 reg 0xdc

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Report: Dell 01HXXJ A05 read
by dpcimanager＠users.sourceforge.net 08 Feb '13

08 Feb '13

flashrom v0.9.6.1-r1646 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): /Volumes/Files/kurtn/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r /var/folders/g8/4hgssf795732rg73l8sdz0d40000gn/T/DPCIzCK01v.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 355M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1028 us, 10000 myus = 10081 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Inspiron N5050" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "01HXXJ" DMI string baseboard-version: "A05" DMI string chassis-type: "Portable" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: fc. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed.

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Report: Intel HM67 #2 read
by dpcimanager＠users.sourceforge.net 08 Feb '13

08 Feb '13

flashrom v0.9.6.1-r1622 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r ~/Desktop/Kexts/bios.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 329M loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 1016 us, 10000 myus = 10062 us, 4 myus = 5 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. Found chipset "Intel HM67" with PCI ID 8086:1c4b. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x0 0xffd00000/0xff900000 FWH IDSEL: 0x0 0xffc80000/0xff880000 FWH IDSEL: 0x0 0xffc00000/0xff800000 FWH IDSEL: 0xf 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x380000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc20: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x00, read w/o addr, none op[1]: 0x00, read w/o addr, none op[2]: 0x00, read w/o addr, none op[3]: 0x00, read w/o addr, none op[4]: 0x00, read w/o addr, none op[5]: 0x00, read w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x00, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0180 FREG1: BIOS region (0x00180000-0x003fffff) is read-write. 0x5C: 0x017f0001 FREG2: WARNING: Management Engine region (0x00001000-0x0017ffff) is locked. 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00000fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0x0000 (OPTYPE) 0x98: 0x00000000 (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300023 FLILL 0x00000000 --- Details --- Component 1 density: 4 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x03ff0180 FLREG2 0x017f0001 FLREG3 0x00000fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00180000 - 0x003fffff Region 2 (ME ) 0x00001000 - 0x0017ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, OK. Super I/O ID 0x8518 is not on the list of flash capable controllers. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 4096 kB. There is only one partition containing the whole address space (0x000000 - 0x3fffff). There are 1024 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (4096 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0x75, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xcc, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xcc, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (4096 kB, Programmer-specific). Reading flash... Reading 4194304 bytes starting at 0x000000. Transaction error between offset 0x00001000 and 0x0000103f (= 0x00001000 + 63)! Read operation failed! HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 FAILED. Restoring MMIO space at 0x1078358a0 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

Report: Intel HM67 read
by dpcimanager＠users.sourceforge.net 08 Feb '13

08 Feb '13

flashrom v0.9.6.1-r1622 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r ~/Desktop/Kexts/bios.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 329M loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 1016 us, 10000 myus = 10062 us, 4 myus = 5 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. Found chipset "Intel HM67" with PCI ID 8086:1c4b. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x0 0xffd00000/0xff900000 FWH IDSEL: 0x0 0xffc80000/0xff880000 FWH IDSEL: 0x0 0xffc00000/0xff800000 FWH IDSEL: 0xf 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x380000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc20: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x00, read w/o addr, none op[1]: 0x00, read w/o addr, none op[2]: 0x00, read w/o addr, none op[3]: 0x00, read w/o addr, none op[4]: 0x00, read w/o addr, none op[5]: 0x00, read w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x00, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0180 FREG1: BIOS region (0x00180000-0x003fffff) is read-write. 0x5C: 0x017f0001 FREG2: WARNING: Management Engine region (0x00001000-0x0017ffff) is locked. 0x60: 0x00000fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00000fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0x0000 (OPTYPE) 0x98: 0x00000000 (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300023 FLILL 0x00000000 --- Details --- Component 1 density: 4 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x03ff0180 FLREG2 0x017f0001 FLREG3 0x00000fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00180000 - 0x003fffff Region 2 (ME ) 0x00001000 - 0x0017ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, OK. Super I/O ID 0x8518 is not on the list of flash capable controllers. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 4096 kB. There is only one partition containing the whole address space (0x000000 - 0x3fffff). There are 1024 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (4096 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0x75, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xcc, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xcc, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xfc, id2 0x51, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xc7, id2 0x1a, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (4096 kB, Programmer-specific). Reading flash... Reading 4194304 bytes starting at 0x000000. Transaction error between offset 0x00001000 and 0x0000103f (= 0x00001000 + 63)! Read operation failed! HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 FAILED. Restoring MMIO space at 0x1078358a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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Re: [flashrom] flashrom ignoring ROM layout region
by Stefan Tauner 08 Feb '13

08 Feb '13

On Tue, 5 Feb 2013 14:06:21 -0800 John Gainsborough <jgindc1(a)gmail.com> wrote: > With BusPirate (v3a, firmware 5.10) and flashrom (v0.9.5.2, little endian) > I am attempting to read a region of the flash ROM defined by a ROM layout > file as in: > > flashrom -p buspirate_spi:dev=/dev/ > ttyUSB0,spispeed=200k -l romlayout -i region1 -r read file > > Where file romlayout contains: > > 003f0000:003fffff region1 > > The flash ROM IC is correctly identified, and region1 is listed as being > used, however flashrom then proceeds to read all ROM memory, not just the > area defined by region1. > > I have run this procedure with flash ROMs: > Eon EN25Q32 and EN25Q64. also Micronix MX25L6445 > > Eventually I plan to use this procedure for writing to a defined region. > > Any help/suggestions gratefully received. Hello John, sorry for the confusion. What you see is perfectly ok and expected (at least to us, understandably not so much to the everyday user). The reason is this: the layout and image options are only taken into account for write operations(!) at the moment. I have created patches to use them for all other operations too but they were not merged yet (we really suck at merging stuff, sorry). If you can not or do not want to extract the required data from the complete image you can take a look at those patches: http://patchwork.coreboot.org/user/bundle/37/ They certainly won't apply to the current HEAD, but you can either use the old source or I can rebase them to the current one if you prefer it. Writing only a part should work though. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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ASUS M4N68T-M LE: flashrom -V
by Valery Kasaev 07 Feb '13

07 Feb '13

flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 430M loops per second, delay more than 10% too short (got 30% of expected delay), recalculating... 441M loops per second, delay more than 10% too short (got 31% of expected delay), recalculating... 451M loops per second, delay more than 10% too short (got 31% of expected delay), recalculating... 432M loops per second, delay more than 10% too short (got 30% of expected delay), recalculating... 453M loops per second, 10 myus = 4 us, 100 myus = 31 us, 1000 myus = 311 us, 10000 myus = 5559 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4N68T-M LE" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8721 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e1. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. WARNING: unexpected second chipset match: "NVIDIA MCP61" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Super I/O ID 0x8721 is not on the list of flash capable controllers. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Chip status register is 00 Found Winbond flash chip "W25Q80" (1024 kB, SPI) at physical address 0xfff00000. Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x13 Found Winbond flash chip "W25Q80" (1024 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified.

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Re: [flashrom] flashrom OPCODES for SPI
by Николай Николаев 07 Feb '13

07 Feb '13

Hi David thank for answer 2013/2/7 David Hendricks <dhendrix(a)google.com> > We usually use the .feature_bits member to distinguish these capabilities. > The feature you describe uses "FEATURE_ADDR_AAA" and corresponds to > spi_aai_write(). > I think adding an array of structs struct inside of the flashchip struct > would be more effort than it is worth. It would make working with the > flashchip data structure more complicated, and we'd need to add nested > loops whenever we iterate over the flashchip array. It would also require > flexible arrays which may cause problems with certain compilers. > Sorry but i don't see this "usually" in this code strings for example: { .vendor = "SST", .name = "SST25VF040B", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF040B, .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 16} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, }, }, .printlock = spi_prettyprint_status_register_sst25vf040b, .unlock = spi_disable_blockprotect, .write = spi_aai_write, /* "FEATURE_ADDR_AAA" ? */ this is a fetch The software must will use spi_chip_write_256 function. .read = spi_chip_read, .voltage = {2700, 3600}, }, and i thinking that this struct is a little complicated because: 1. this struct has not used field like a voltage and this field can't uniquely define chip voltage because different chips can have a equivalent ID 2. this struct has a not informative field like a name for example that is that - SST25VF040B.REMS. Sorry but i can't understanding different SST25VF040B and that is REMS - is this a comment or other? and i can't found documentation on SST25VF040B.REMS chip. Next example EN25Q80(A) Is this a two chips EN25Q80 and EN25Q80A or other? Is this chip EN25Q80 real? I think adding an array of structs struct inside of the flashchip struct > would be more effort than it is worth. > I think adding an array of struct will be not effort, but testing a software will be effort. > It would make working with the flashchip data structure more complicated, > and we'd need to add nested loops whenever we iterate over the flashchip > array. It would also require flexible arrays which may cause problems with > certain compilers. > If we know chip ID that we can easy searching any chip parameters in other structure. And i think we can easy exclude this parameters from structure The MX25L25835E actually should look the same as MX25L12805D from a > software perspective. The difference is that MX25L25835E is stacked (two > 128Mbit flash memories). Each bank is selected by a different chip-select > line (referred to as CS#1 and CS#2 in the data sheet). > thanks. I'm understanding this is a simple stack but we have a one ID on two different chips..... Will user use flashrom software for program MX25L25835E if software didn't support this chip in list on wiki page, but support MX25L12805D? How will you distinguish chip MX25L25835E from MX25L12805D that chips have a equivalent chip ID. What do you think about link on chip Documentation on wiki page? -- With best regards Nikolay Nikolaev

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Re: [flashrom] flashrom OPCODES for SPI
by David Hendricks 06 Feb '13

06 Feb '13

On Wed, Feb 6, 2013 at 4:35 AM, Николай Николаев <evrinoma(a)gmail.com> wrote: > Hi Stefan > > Sorry but i don't want disprove you, i just have a many free time and i > want to improve this project. But the dispute burning truth. 8) > All time from my last mail i'm searching spi flash chips documentation and > I found about 445 chips different brand and sorted them. > May be it will be useful for all community. We will made host with > SPI(Parallel and other) flash chips documentations and add link on wiki > page. > for example > Eon EN25Q64(link to pdf) 8192 SPI ? ? ? ? 2.700 3.600 > > Studied documentation i regularity see that all chips has a support > standard OPcodes like this > WR DATA 0X02 > READ DATA 0X03 > WR DIS 0X04 > READ STATUS 0X05 > WR ENA 0X06 > ... > exclude 10 Atmel chips from amount 445 and for him we will must write > special driver > > and special OPcodes like a > Fast Dual read 0x3B > Auto Address increment 0xAD > and others - that codes is a different fetches spi flash chips > > What does this mean. This mean that a spi controller has a standard > OPcodes for all flash chips and special OPcodes for each one flash chip. > But if we will change flash chip on other flash chip with different special > OPcodes that we will must replace special OPcodes. If we will not do it > that we can't use special OPcodes, but we can use standard OPcodes. > So, for more compatibility we will must verify - Does flash chip support > special OPcodes?. And if chip will support them that we will use them, but > if chip will not support them that we will use a standard OPcodes. > for example: > MX25L6405 > The function write chip used standard OPcodes flash chip called function > spi_chip_write_256 > SST25VF016B > The function write chip used fetches OPcodes flash chip called function > spi_aai_write > If we can't change OPcodes in registers our SPI controller that we will > not write data to chip if we replace them. > But we will make a program check supporting OPcodes and switch a function > from spi_aai_write on spi_chip_write_256 > After that we can easy write to flash > or fast - our SPI controller has supporting fetches OPcodes > or slow - our SPI controller hasn't supporting fetches OPcodes > We usually use the .feature_bits member to distinguish these capabilities. The feature you describe uses "FEATURE_ADDR_AAA" and corresponds to spi_aai_write(). > Also i want to suggest exclude from struct flashchip {} parameters > voltage, name and add array of struct like a chipdata. > The struct chipdata contains information about all possible chip names and > various parameters > Because looked chips documents i see chips that have a one model_id but > have a various chips name, various voltage and various capacity > for example > MX25U6435F and MX25L6439E MX25L12805D and MX25L25835E > You're correct about the naming of similar chips. We introduced a schema to work with this last year to try and deal with the naming: http://www.flashrom.org/pipermail/flashrom/2012-July/009598.html I think adding an array of structs struct inside of the flashchip struct would be more effort than it is worth. It would make working with the flashchip data structure more complicated, and we'd need to add nested loops whenever we iterate over the flashchip array. It would also require flexible arrays which may cause problems with certain compilers. The MX25L25835E actually should look the same as MX25L12805D from a software perspective. The difference is that MX25L25835E is stacked (two 128Mbit flash memories). Each bank is selected by a different chip-select line (referred to as CS#1 and CS#2 in the datasheet). HTH! -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Fwd: msi windpad 110w
by Seryi Kuznecov 06 Feb '13

06 Feb '13

Hello I want to flash the bios in msi windpad 110w. Russia stands for version 2.07. Around the world 1.06. How do I change the version to 1.06? Standard methods does not work, is an error "error: bios cannot be updated" (most likely defense costs). Protection to remove Bios can not. This option is not present. Help put the bios 1.06. chip MX25L1606E Thank you for your project A non-text attachment has been stripped: EN0E1AMS.106 It is available at http://paste.flashrom.org/view.php?id=1543 A non-text attachment has been stripped: EN0E1AMS.207 It is available at http://paste.flashrom.org/view.php?id=1544

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Re: [flashrom] flashrom OPCODES for SPI
by Николай Николаев 06 Feb '13

06 Feb '13

Hi Stefan Sorry but i don't want disprove you, i just have a many free time and i want to improve this project. But the dispute burning truth. 8) All time from my last mail i'm searching spi flash chips documentation and I found about 445 chips different brand and sorted them. May be it will be useful for all community. We will made host with SPI(Parallel and other) flash chips documentations and add link on wiki page. for example Eon EN25Q64(link to pdf) 8192 SPI ? ? ? ? 2.700 3.600 Studied documentation i regularity see that all chips has a support standard OPcodes like this WR DATA 0X02 READ DATA 0X03 WR DIS 0X04 READ STATUS 0X05 WR ENA 0X06 ... exclude 10 Atmel chips from amount 445 and for him we will must write special driver and special OPcodes like a Fast Dual read 0x3B Auto Address increment 0xAD and others - that codes is a different fetches spi flash chips What does this mean. This mean that a spi controller has a standard OPcodes for all flash chips and special OPcodes for each one flash chip. But if we will change flash chip on other flash chip with different special OPcodes that we will must replace special OPcodes. If we will not do it that we can't use special OPcodes, but we can use standard OPcodes. So, for more compatibility we will must verify - Does flash chip support special OPcodes?. And if chip will support them that we will use them, but if chip will not support them that we will use a standard OPcodes. for example: MX25L6405 The function write chip used standard OPcodes flash chip called function spi_chip_write_256 SST25VF016B The function write chip used fetches OPcodes flash chip called function spi_aai_write If we can't change OPcodes in registers our SPI controller that we will not write data to chip if we replace them. But we will make a program check supporting OPcodes and switch a function from spi_aai_write on spi_chip_write_256 After that we can easy write to flash or fast - our SPI controller has supporting fetches OPcodes or slow - our SPI controller hasn't supporting fetches OPcodes Also i want to suggest exclude from struct flashchip {} parameters voltage, name and add array of struct like a chipdata. The struct chipdata contains information about all possible chip names and various parameters Because looked chips documents i see chips that have a one model_id but have a various chips name, various voltage and various capacity for example MX25U6435F and MX25L6439E MX25L12805D and MX25L25835E

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flashrom ignoring ROM layout region
by John Gainsborough 05 Feb '13

05 Feb '13

With BusPirate (v3a, firmware 5.10) and flashrom (v0.9.5.2, little endian) I am attempting to read a region of the flash ROM defined by a ROM layout file as in: flashrom -p buspirate_spi:dev=/dev/ ttyUSB0,spispeed=200k -l romlayout -i region1 -r read file Where file romlayout contains: 003f0000:003fffff region1 The flash ROM IC is correctly identified, and region1 is listed as being used, however flashrom then proceeds to read all ROM memory, not just the area defined by region1. I have run this procedure with flash ROMs: Eon EN25Q32 and EN25Q64. also Micronix MX25L6445 Eventually I plan to use this procedure for writing to a defined region. Any help/suggestions gratefully received. John G

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flashrom OPCODES for SPI
by Николай Николаев 05 Feb '13

05 Feb '13

Hi Stefan Sorry but i don't want disprove you, i just have a many free time and i want to improve this project. But the dispute burning truth. 8) All time from my last mail i'm searching spi flash chips documentation and I found about 445 chips different brand and sorted them. May be it will be useful for all community. We will made host with SPI(Parallel and other) flash chips documentations and add link on wiki page. for example Eon EN25Q64(link to pdf) 8192 SPI ? ? ? ? 2.700 3.600 Studied documentation i regularity see that all chips has a support standard OPcodes like this WR DATA 0X02 READ DATA 0X03 WR DIS 0X04 READ STATUS 0X05 WR ENA 0X06 ... exclude 10 Atmel chips from amount 445 and for him we will must write special driver and special OPcodes like a Fast Dual read 0x3B Auto Address increment 0xAD and others - that codes is a different fetches spi flash chips What does this mean. This mean that a spi controller has a standard OPcodes for all flash chips and special OPcodes for each one flash chip. But if we will change flash chip on other flash chip with different special OPcodes that we will must replace special OPcodes. If we will not do it that we can't use special OPcodes, but we can use standard OPcodes. So, for more compatibility we will must verify - Does flash chip support special OPcodes?. And if chip will support them that we will use them, but if chip will not support them that we will use a standard OPcodes. for example: MX25L6405 The function write chip used standard OPcodes flash chip called function spi_chip_write_256 SST25VF016B The function write chip used fetches OPcodes flash chip called function spi_aai_write If we can't change OPcodes in registers our SPI controller that we will not write data to chip if we replace them. But we will make a program check supporting OPcodes and switch a function from spi_aai_write on spi_chip_write_256 After that we can easy write to flash or fast - our SPI controller has supporting fetches OPcodes or slow - our SPI controller hasn't supporting fetches OPcodes Also i want to suggest exclude from struct flashchip {} parameters voltage, name and add array of struct like a chipdata. The struct chipdata contains information about all possible chip names and various parameters Because looked chips documents i see chips that have a one model_id but have a various chips name, various voltage and various capacity for example MX25U6435F and MX25L6439E MX25L12805D and MX25L25835E .... -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Simple diagram for modern laptop booting flow
by Антон Кочков 04 Feb '13

04 Feb '13

Hello! Here is simple diagram for booting flow of modern Intel laptops. Feel free to ask questions, request for improvements, giving hints. Why Intel? Just because it is more complex than modern AMD systems. Why laptop? Same reason - more complex than desktop. If you have an idea howto merge laptop and desktop booting in one diagram - please share. Attaching both png result and MS Visio 2010 source. Best regards, Anton Kochkov.

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[commit] r1648 - trunk
by repository service 04 Feb '13

04 Feb '13

Author: stefanct Date: Mon Feb 4 05:38:42 2013 New Revision: 1648 URL: http://flashrom.org/trac/flashrom/changeset/1648 Log: Fix building for MacOSX. - Add a new macro named IS_MACOSX to hwaccess.c and use it to enable iopl(). This was broken since r1638. This fix does *not* restore the very permissive concept where iopl() was activated in an #else branch that was inplace before r1638. - Make printing the image file's size in flashrom.c platform independent. Bonus: remove definitions of off64_t and lseek64 which are not necessary anymore for about 1000 commits. Thanks to SJ for reporting the issue and testing the solution. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.c trunk/hwaccess.c trunk/hwaccess.h Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/flashrom.c Mon Feb 4 05:38:42 2013 (r1648) @@ -1121,8 +1121,8 @@ return 1; } if (image_stat.st_size != size) { - msg_gerr("Error: Image size (%ld B) doesn't match the flash chip's size (%ld B)!\n", - image_stat.st_size, size); + msg_gerr("Error: Image size (%jd B) doesn't match the flash chip's size (%ld B)!\n", + (intmax_t)image_stat.st_size, size); fclose(image); return 1; } Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/hwaccess.c Mon Feb 4 05:38:42 2013 (r1648) @@ -28,7 +28,8 @@ #define IS_BSD (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__OpenBSD__)) #define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) -#if !(IS_BSD || IS_LINUX || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) +#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) +#if !(IS_BSD || IS_LINUX || IS_MACOSX || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) #error "Unknown operating system" #endif @@ -72,7 +73,7 @@ sysi86(SI86V86, V86SC_IOPL, 0); #elif IS_BSD close(io_fd); -#elif IS_LINUX +#elif IS_LINUX || IS_MACOSX iopl(0); #endif return 0; @@ -87,7 +88,7 @@ if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif IS_BSD if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif IS_LINUX +#elif IS_LINUX || IS_MACOSX if (iopl(3) != 0) { #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/hwaccess.h Mon Feb 4 05:38:42 2013 (r1648) @@ -189,8 +189,6 @@ * versions. Use machine/cpufunc.h only for plain FreeBSD/DragonFlyBSD. */ #include <machine/cpufunc.h> - #define off64_t off_t - #define lseek64 lseek #define OUTB(x, y) do { u_int outb_tmp = (y); outb(outb_tmp, (x)); } while (0) #define OUTW(x, y) do { u_int outw_tmp = (y); outw(outw_tmp, (x)); } while (0) #define OUTL(x, y) do { u_int outl_tmp = (y); outl(outl_tmp, (x)); } while (0) @@ -201,8 +199,6 @@ #if defined(__MACH__) && defined(__APPLE__) /* Header is part of the DirectHW library. */ #include <DirectHW/DirectHW.h> - #define off64_t off_t - #define lseek64 lseek #endif #if defined (__sun) && (defined(__i386) || defined(__amd64)) /* Note different order for outb */ @@ -241,8 +237,6 @@ #endif #if defined(__NetBSD__) || defined (__OpenBSD__) - #define off64_t off_t - #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h>

1 0

Flashrom ignoring ROM layout regions
by John Gainsborough 04 Feb '13

04 Feb '13

With BusPirate (v3a, firmware 5.10) and flashrom (v0.9.5.2, little endian) I am attempting to read a region of the flash ROM defined by a ROM layout file as in: flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=200k -l romlayout -i region1 -r read file Where file romlayout contains: 003f0000:003fffff region1 The flash ROM IC is correctly identified, and region1 is listed as being used, however flashrom then proceeds to read all ROM memory, not just the area defined by region1. I have run this procedure with flash ROMs: Eon EN25Q32 and EN25Q64. also Micronix MX25L6445 Eventually I plan to use this procedure for writing to a defined region. Any help/suggestions gratefully received. John G

1 0

chip W25Q80 chipset NVIDIA MCP61 motherboard Asrock N68C-S UCC
by Александр Трубицын 03 Feb '13

03 Feb '13

Hello! i try to use flashrom with motherboard Asrock N68C-S UCC http://www.asrock.com/mb/manual.asp?Model=N68C-S%20UCC http://www.asrock.com/mb/overview.ru.asp?cat=Manual&Model=N68C-S%20UCC with NVIDIA MCP61 chipset and W25Q80 chip. It is a part of russian manufacture'r computer Depo Ego 9730 http://www.depo.ru/download/drivers/2010/User_Manual/DEPO_Ego_manual_2010.p… I don't find any switches to enabe/disable flash writing on motherboard and in the bios menu. i use OpenSuse 12.2 with this script #!/bin/bash # get information about flash chip & BIOS name="W25Q80_chipset_NVIDIA_MCP61_on_Asrock_N68C-S_UCC" sudo /usr/sbin/flashrom -V > $name.V.txt sudo /usr/sbin/flashrom -VVVr $name.flash > $name.Vr.txt sudo /usr/sbin/flashrom -VVVE > $name.VE.txt sudo /usr/sbin/lspci -nnvvxxx > $name.lspci_nnvvxxx.txt sudo /usr/sbin/superiotool -deV > $name.superiotool.txt and get some warnings from flashrom. There are script's output files in attachment.

2 1

ASUS M5A97: success
by Melchior FRANZ 03 Feb '13

03 Feb '13

Hey, a few days ago I successfully flashed an ASUS M5A97 bios (version 0705 to 1605). No problems whatsoever, whereas the BIOS-builtin "AZ Flash 2" turned out to be useless: it didn't even recognize my FAT usb stick. $ sudo /usr/local/sbin/flashrom --programmer internal -w M5A97-ASUS-1605.ROM flashrom v0.9.6.1-r1646 on Linux 3.7.5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Output from "flashrom -V --programmer=internal" attached. W25Q32 ... chip already listed as supported AMD SB7x0/SB8x0/SB9x0 ... chipset already listed as supported -> ASUS M5A97 ... mainboard *NOT* listed yet Thanks for flashrom! m.

2 7

[PATCH] Fix evil twins of Macronix MX25L1605, MX25L3205, MX25L6405.
by Stefan Tauner 03 Feb '13

03 Feb '13

Similarly to the previous patch this one updates the chips identified as above with references to and data about their respective twins. Unlike previously this one deals with the more evil details. Helge Wagner from GE discovered some problems with chips sharing IDs and proposed a patch to tackle (some of) them, see: http://patchwork.coreboot.org/patch/3709/ That patch was bitrotting in our mailboxes for a long time and it is still not ready for merge, but we increasingly get reports about problems (e.g. http://paste.flashrom.org/view.php?id=1525) regarding these chips and hence must act to ensure users' safety. This patch splits the chip definitions of evil twins into separate ones which correctly declare the respective attributes (the main problems are the erase block sizes for the 0x20 opcode and hence my changes combine different chips with partly different attributes apart from their names as long as the erasers layout it the same). This forces the user to select the (right) chip definition with the -c/--chip parameter and hence will break a number of previously perfectly working environments. 0x2015 is used by and split to - MX25L1605 (64kB sectors in 0x20 erases) - MX25L1605A (4kB in 0x20 erases and an additional 0x52 opcode with 64kB blocks) - MX25L1605D/MX25L1608D (4k sectors in 0x20 erases) 0x2016 is used by and split to - MX25L3205, MX25L3205A (64kB 0x20) - MX25L3205D/MX25L3208D (4kB 0x20) - MX25L3206E (4k 0x20, 64k 0x52) 0x2017 is used by and split to - MX25L6405 MX25L6405D (64k 0x20) - MX25L6406E/MX25L6436E (4k 0x20) - MX25L6445E (4k 0x20, 64k 0x52) Bonus: add some minor details to MX25L1635D, MX25L1635E, MX25L3235D, MX25L12805D. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- TODO after merging this: - implement probing methods that are able to distinguish at least some of the evil twins. - where this is not possible discuss alternatives like the somewhat fail-safe spi_block_erase_20_4or64k() by Helge - find and spank the ones reponsible for this whole mess. --- flashchips.c | 270 +++++++++++++++++++++++++++++++++++++++++++++++++++++----- flashchips.h | 8 +- 2 files changed, 252 insertions(+), 26 deletions(-) diff --git a/flashchips.c b/flashchips.c index b976ee6..1783fe7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5270,10 +5270,45 @@ const struct flashchip flashchips[] = { .block_erasers = { { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605A", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ + .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 32} }, @@ -5286,10 +5321,45 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605D/MX25L1608D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: CP mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5301,7 +5371,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L1635D, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5321,10 +5392,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -5336,7 +5407,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L1635E, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5356,16 +5428,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L3205", + .name = "MX25L3205(A)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L3205, @@ -5378,12 +5450,87 @@ const struct flashchip flashchips[] = { .block_erasers = { { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3205D/MX25L3208D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: CP mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3206E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { @@ -5391,10 +5538,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5406,7 +5553,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L3235D, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 256B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5426,7 +5574,7 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5435,13 +5583,14 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX25L6405", + .name = "MX25L6405(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L6405, .total_size = 8192, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L6405D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5461,7 +5610,7 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 has different meanings */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5470,13 +5619,90 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX25L12805", + .name = "MX25L6406E/MX25L6436E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* OTP: 06E 64B/36E 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 for 36E is quad enable */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L6445E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L12805(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L12805, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5496,10 +5722,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* MX25L12805D: Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, diff --git a/flashchips.h b/flashchips.h index d123ab0..22af0e3 100644 --- a/flashchips.h +++ b/flashchips.h @@ -387,10 +387,10 @@ #define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ #define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ -#define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ -#define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D}, MX25L6406E, MX25L6436E */ -#define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ +#define MACRONIX_MX25L1605 0x2015 /* MX25L1605 (64k 0x20); MX25L1605A (4k 0x20, 64k 0x52); MX25L1605D/MX25L1608D (4k 0x20) */ +#define MACRONIX_MX25L3205 0x2016 /* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L12805 0x2018 /* Same as MX25L12805D */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX25U1635E 0x2535 -- Kind regards, Stefan Tauner

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[commit] r1647 - trunk
by repository service 02 Feb '13

02 Feb '13

Author: stefanct Date: Sat Feb 2 16:35:44 2013 New Revision: 1647 URL: http://flashrom.org/trac/flashrom/changeset/1647 Log: Update Macronix MX25L512, MX25L1005, MX25L2005, MX25L4005, MX25L8005. Update MX25L512 with references to and data about MX25L512E, MX25V512, MX25V512C. Update MX25L1005 with references to and data about MX25L1005C, MX25L1006E. Update MX25L2005 with references to and data about MX25L2005C. Update MX25L4005 with references to and data about MX25L4005A, MX25L4005C. Update MX25L8005 with references to and data about MX25V8005. Bonus: add chip IDs of MX25U1635E, MX25U3235E/F, MX25U6435E/F. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Jan 15 18:37:48 2013 (r1646) +++ trunk/flashchips.c Sat Feb 2 16:35:44 2013 (r1647) @@ -5068,12 +5068,13 @@ { .vendor = "Macronix", - .name = "MX25L512", + .name = "MX25L512(E)/MX25V512(C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L512, .total_size = 64, .page_size = 256, + /* MX25L512E supports SFDP */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -5097,21 +5098,22 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp1, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B) supported, MX25L512E supports dual I/O */ + .voltage = {2700, 3600}, /* 2.35-3.6V for MX25V512(C) */ }, { .vendor = "Macronix", - .name = "MX25L1005", + .name = "MX25L1005(C)/MX25L1006E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L1005, .total_size = 128, .page_size = 256, + /* MX25L1006E supports SFDP */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -5132,16 +5134,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported, MX25L1006E supports dual I/O */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L2005", + .name = "MX25L2005(C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L2005, @@ -5170,16 +5172,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L4005", + .name = "MX25L4005(A/C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L4005, @@ -5208,16 +5210,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L8005", + .name = "MX25L8005/MX25V8005", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L8005, @@ -5246,11 +5248,11 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, /* 2.35-3.6V for MX25V8005 */ }, { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Jan 15 18:37:48 2013 (r1646) +++ trunk/flashchips.h Sat Feb 2 16:35:44 2013 (r1647) @@ -382,10 +382,10 @@ * and use the same set of IDs. */ #define MACRONIX_ID 0xC2 /* Macronix (MX) */ -#define MACRONIX_MX25L512 0x2010 /* Same as MX25V512 */ -#define MACRONIX_MX25L1005 0x2011 -#define MACRONIX_MX25L2005 0x2012 -#define MACRONIX_MX25L4005 0x2013 /* MX25L4005{,A} */ +#define MACRONIX_MX25L512 0x2010 /* Same as MX25L512E, MX25V512, MX25V512C */ +#define MACRONIX_MX25L1005 0x2011 /* Same as MX25L1005C, MX25L1006E */ +#define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ +#define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ @@ -393,6 +393,9 @@ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ +#define MACRONIX_MX25U1635E 0x2535 +#define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ +#define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18

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Re: [flashrom] Fw: Appreciate for developing HM65 BIOS R\W tool SW
by zhuzhihui 01 Feb '13

01 Feb '13

Dear Stefan Nice to hear from you,we follow your kindly suggestion to upgrade Flashrom from 0.9.4 to 0.9.6, and run command #flashrom -p internal –VV in mentioned Topstar TEB-H8100 manboard,but below the outputt information: flashrom v0.9.6.1-r1564 on Linux 2.6.35.6-45.fc14.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.5.1 20100924 (Red Hat 4.5.1-4), little endian Command line (3 args): flashrom -p internal -VV Calibrating delay loop... OS timer resolution is 6 usecs, 1096M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 24 myus = 24 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Topstar Corporation" DMI string system-product-name: "TEB-H8100" DMI string system-version: "0.1" DMI string baseboard-manufacturer: "Topstar Corp." DMI string baseboard-product-name: "TEB-H8100" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Laptop" Laptop detected via DMI. Found ITE Super I/O, ID 0x8782 on port 0x2e Would you pls help analyze above info and give us more indication on restrictions? Thanks. Have a nice weekend! Brs\Jake zhu & David Du From: 杜新雷 Date: 2013-02-01 11:04 To: zhuzhihui Subject: Fw: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW 杜新雷 From: 杜新雷 Date: 2013-01-23 09:44 To: flashrom CC: 缪总; zhuzhihui Subject: Re: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW Hello Stefan , I am very pleased to receive your letter，depending on your tips flashrom version upgrade from 0.9.4 to 0.9.6 OS: FC14 Core Ver.2.6.35.6--45.fc14.i686 (i686) and used following command #flashrom -p internal –VV Following is the output information: flashrom v0.9.6.1-r1564 on Linux 2.6.35.6-45.fc14.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.5.1 20100924 (Red Hat 4.5.1-4), little endian Command line (3 args): flashrom -p internal -VV Calibrating delay loop... OS timer resolution is 6 usecs, 1096M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 24 myus = 24 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Topstar Corporation" DMI string system-product-name: "TEB-H8100" DMI string system-version: "0.1" DMI string baseboard-manufacturer: "Topstar Corp." DMI string baseboard-product-name: "TEB-H8100" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Laptop" Laptop detected via DMI. Found ITE Super I/O, ID 0x8782 on port 0x2e we do appreciate for your great help to develop the mentioned tools SW within next week，thank you! Kind regards/David From: Stefan Tauner Date: 2013-01-19 10:03 To: 朱智会 CC: flashrom; 'duxinlei' Subject: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW On Thu, 17 Jan 2013 17:28:53 +0800 朱智会 <zhuzhihui(a)chinalotsynergy.com> wrote: > Dear Sir/Madam > > > > This is Jake zhu and David Du from China Lotsynergy, our company is an IPC > based system integrated provider located in Guangzhou, China. To meet our > customer’s requirement of providing a BIOS R\W tool (OS: FC14 Core Ver. 2. > 6.35.6--45.fc14.i686 (i686)), we tried to seek proper tool in internet and > found FlashRom at the first time. > > We downloaded FlashRom Ver L: v0.9.4-r1455 and used following command > #flashrom -r sysbios.bin, but fail with below error info: > > > > After double check the supported chipset list in website, we found the South > Bridge Chipset HM65 is not supported; however BIOS Flash Chip (W25Q32) is > supported (see below). > > > > So write to you for help to develop a BIOS R\W tools SW (/OS: FC14 Core Ver. > 2.6.35.6--45.fc14.i686 (i686), and below the necessary info for your > reference, due to tight schedule of project, we do appreciate for your great > help to develop the mentioned tools SW within next week. Hello David, in general the chipset as well as the flash chip are well supported by flashrom. The Intel chipsets can however be configured to restrict flash access very firmly. There are various ways to restrict it (forbidden opcodes, write- and read-protected addresses ranges of different kinds etc.). If the board does not set up too many restrictions, flashrom will work for you without problems. The "error" (it is a warning actually, and you can and should read about the details in the man page how to force flashrom to continue) is because the SMBIOS/DMI table in the firmware indicates that it is a mobile device and those sometimes behave in dangerous ways. This is especially the case if the flash chip is not attached to the southbridge but and EC which is sitting between the southbridge and the flash chip. You should also update to a newer version, 0.9.4 is pretty old and I have done quite some work on the intel-related code. When you found out how to tell flashrom to continue even though it thinks it is running on a laptop please send us the output of flashrom -p internal -VV I can then tell you some details about the restrictions set up in the current firmware. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom February 2013