October 2013 - flashrom - mail.coreboot.org

Re: [flashrom] [PATCH] Ensure DMI strings used in dmi_compare() are not NULL.

by Stefan Tauner

On Tue, 29 Oct 2013 00:12:50 +0100 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Previously the external DMI decoder did not allow this to happen because > all possible pointers were initialized at startup by the output of > 'dmidecode -s ...' which has default values for all supported types. > > The now active internal DMI decoder does work differently: it scans the > complete DMI table once and copies the available strings. Therefore, strings > that are not set by the firmware are left at their default value of NULL. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Idwer reproduced the problem and was able to verify the correctness of this patch (see new, extended commit log), hence Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> and committed in r1763. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

6 years, 7 months

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[commit] r1763 - trunk

by repository service

Author: stefanct Date: Tue Oct 29 02:38:45 2013 New Revision: 1763 URL: http://flashrom.org/trac/flashrom/changeset/1763 Log: Ensure DMI strings used in dmi_compare() are not NULL. Previously the external DMI decoder did not allow this to happen because all possible pointers were initialized at startup by the output of 'dmidecode -s ...' which has default values for all supported types. The now active internal DMI decoder does work differently: it scans the complete DMI table once and copies the available strings. Therefore, strings that are not set by the firmware are left at their default value of NULL. A segfault would arise if the following conditions are all true: - the firmware sets up a DMI/SMBIOS table which has at least a correct checksum, and - that table does *not* define at least one of the DMI strings we use for matching (as defined by dmi_strings[] in dmi.c), and - there exists a board enable whose PCI IDs are matched by the board, and which has a DMI string set that ends with a $ anchor, and - the user calls the internal programmer of flashrom without the optional mainboard parameter. This was first observed by Gelip on an abit BF6 using the coreboot port for the abit BE6-II V2.0. The segfault was reproduced by Idwer Vollering on an ASUS F2A85-M with the default DMI values of CONFIG_MAINBOARD_SMBIOS_MANUFACTURER etc. overwritten and a forged board enable matching his board. Idwer also verified that this patch fixes the problem, thanks a lot! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/dmi.c Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Sat Oct 26 19:02:03 2013 (r1762) +++ trunk/dmi.c Tue Oct 29 02:38:45 2013 (r1763) @@ -406,8 +406,8 @@ * at the beginning and '$' at the end. So you can look for "^prefix", * "suffix$", "substring" or "^complete string$". * - * @param value The string to check. - * @param pattern The pattern. + * @param value The non-NULL string to check. + * @param pattern The non-NULL pattern. * @return Nonzero if pattern matches. */ static int dmi_compare(const char *value, const char *pattern) @@ -454,9 +454,13 @@ if (!has_dmi_support) return 0; - for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) + for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) { + if (dmi_strings[i].value == NULL) + continue; + if (dmi_compare(dmi_strings[i].value, pattern)) return 1; + } return 0; }

6 years, 7 months

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[PATCH] Ensure DMI strings used in dmi_compare() are not NULL.

by Stefan Tauner

Previously the external DMI decoder did not allow this to happen because all possible pointers were initialized at startup by the output of 'dmidecode -s ...' which has default values for all supported types. The now active internal DMI decoder does work differently: it scans the complete DMI table once and copies the available strings. Therefore, strings that are not set by the firmware are left at their default value of NULL. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- dmi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/dmi.c b/dmi.c index 14f3871..ef7ae2c 100644 --- a/dmi.c +++ b/dmi.c @@ -406,8 +406,8 @@ void dmi_init(void) * at the beginning and '$' at the end. So you can look for "^prefix", * "suffix$", "substring" or "^complete string$". * - * @param value The string to check. - * @param pattern The pattern. + * @param value The non-NULL string to check. + * @param pattern The non-NULL pattern. * @return Nonzero if pattern matches. */ static int dmi_compare(const char *value, const char *pattern) @@ -454,9 +454,13 @@ int dmi_match(const char *pattern) if (!has_dmi_support) return 0; - for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) + for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) { + if (dmi_strings[i].value == NULL) + continue; + if (dmi_compare(dmi_strings[i].value, pattern)) return 1; + } return 0; } -- Kind regards, Stefan Tauner

6 years, 7 months

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[PATCH] Add util/pad_image.sh.

by Stefan Tauner

A convenient POSIX shell script to pad images by prepending or appending constant data to prepare them for flashrom digestion. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Preparing images for iPXE was a pain without this (I had to build it many times for debugging), and it is probably useful for other use cases too. The only thing missing is a mode that repeats the file every 2^N bytes where 2^N is the nearest larger power of two to the length of the image to be padded, e.g. if you want to write a 256 kB chip in a 3Com NIC that does only support up to 128 kB/is one address line short. And maybe a SI-prefix parser... but first flashrom should get one ;) util/pad_image.sh | 222 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 222 insertions(+) create mode 100755 util/pad_image.sh diff --git a/util/pad_image.sh b/util/pad_image.sh new file mode 100755 index 0000000..30813f4 --- /dev/null +++ b/util/pad_image.sh @@ -0,0 +1,222 @@ +#!/bin/sh +# +# This file is part of the flashrom project. +# +# Copyright (C) 2013 Stefan Tauner +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +assert_cmds_avail () { + while [ $# -gt 0 ]; + do + command -v $1 >/dev/null 2>&1 || { + echo "$1 is required." + exit 1 + } + shift + done +} + +assert_cmds_avail "cat" "cp" "dd" "mv" "printf" "tr" "wc" + +show_help() { + echo "Usage: + $0 [-a|-p] [-h] [-f] -i <infile> [-o <outfile>] -s <size> [-v <val>] + + Copies infile into outfile and fills up the remaining space to size with val. +Options + -h or --help + this message + -a or --append + append the padding (default) + -p or --prepend + prepend the padding + -f or --force + force to overwrite existing output file + -i or --infile <infile> + the input file + -o or --outfile <outfile> + the output file (\"<infile>-padded\" on default) + -s or --size <size> + the wanted size of the output file in bytes + -v or --value <value> + the value in common hexadecimal format to be used for padding (0xFF on default) +" +} + +check_action() { + if [ -n "$action" ]; then + echo "Error: Multiple actions given.">&2 + exit 1 + fi +} + +check_arg() { + if [ -z "$2" ]; then + echo "Error: $1 requires an argument.">&2 + exit 1 + fi +} + + +prepend () { + { tr '\0' $(printf "\\\\%o" "$val") < /dev/zero | dd bs=1 count=$padsize of="$outfile".tmp && \ + cat "$infile" >> "$outfile".tmp && \ + mv -f "$outfile".tmp "$outfile" ; } >/dev/null 2>&1 || \ + return 1 +} + +append () { + { cp "$infile" "$outfile".tmp && tr '\0' $(printf "\\\\%o" "$val") < /dev/zero | \ + dd bs=1 count=$padsize of="$outfile".tmp conv=notrunc seek=$filesize && \ + mv -f "$outfile".tmp "$outfile" ; } >/dev/null 2>&1 || \ + return 1; +} + +main () { + local action= + local outfile= + local infile= + local size= + local val= + local force= + + # The is the main loop + while [ $# -gt 0 ]; + do + case ${1} in + -h|--help) + action=show_help; + shift;; + -a|--append) + check_action $1 + action=append + shift;; + -p|--prepend) + check_action $1 + action=prepend + shift;; + -f|--force) + force=1 + shift;; + -i|--infile) + if [ -z "$infile" ] ; then + check_arg $1 $2 + infile=$2 + else + echo "Error: More than one input file given.">&2; + exit 1 + fi + shift 2;; + -o|--outfile) + if [ -z "$outfile" ] ; then + check_arg $1 $2 + outfile=$2 + else + echo "Error: More than one output file given.">&2; + exit 1 + fi + shift 2;; + -v|--value) + if [ -z "$val" ] ; then + check_arg $1 $2 + val=$2 + else + echo "Error: More than one value given.">&2; + exit 1 + fi + shift 2;; + -s|--size) + if [ -z "$size" ] ; then + check_arg $1 $2 + size=$2 + case $size in + ''|[!0-9]*) echo "Error: Could not parse size $size.">&2; exit 1;; + *) ;; + esac + else + echo "Error: More than one size given.">&2; + exit 1 + fi + shift 2;; + -*) + show_help; + echo "Error: Invalid option: ${1}">&2 + exit 1;; + *) + echo "Error: Overabundant parameter: \"${1}\"">&2 + shift;; + esac; + done + + if [ -z "$infile" ] ; then + show_help + echo "Error: No input file specified">&2 + exit 1 + fi + + if [ ! -e "$infile" -o ! -r "$infile" -o ! -w "$infile" ]; then + echo "Error: ${infile} is not accessible">&2 + exit 1 + fi + + if [ -z "$outfile" ] ; then + outfile="${infile}-padded" + fi + + if [ -z "$force" -a -e "$outfile" ]; then + echo "Error: ${outfile} exists already.">&2 + exit 1 + fi + + if [ -z "$size" ] ; then + show_help + echo "Error: No target size specified.">&2 + exit 1 + fi + + filesize=$(wc -c < "$infile") || exit 1 + if [ $size -le $filesize ]; then + echo "File is already as large as or even larger than requested.">&2 + exit 1 + fi + + # default action is to append + if [ -z "$action" ] ; then + action=append + fi + + # default value is all ones + if [ -z "$val" ] ; then + val="0xff" + fi + case $val in + ''|[!a-fA-F0-9]*) echo "Could not parse value $val.">&2; exit 1;; + *) ;; + esac + + padsize=$(($size-$filesize)) + printf "Copy data from file \"%s\" to \"%s\" and pad it from %d B to %d B by %sing 0x%x %d times... " \ + $infile $outfile $filesize $size $action $val $padsize + if $action ; then + echo "done." + else + echo "failed." + return 1 + fi +} + +main $@ -- Kind regards, Stefan Tauner

6 years, 7 months

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Add confirmed board to wiki

by Kyle Bentley

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I can confirm that the Suprmicro X7SPA-H board can be safely flashed using flashrom. A similar board is listed in the wiki, but for the sake of completeness add this one as well. The full verbose flash and verify can be found here if interested: http://kbentley.dyndns.org/data/flashrom-output The flash chip MX25L3205, the chipset is an Intel ICH9. Kyle Bentley - ---------------------- Kyle Bentley kwbent(a)uab.edu UAB Dept of Physics 1300 University Blvd Birmingham, AL - ---------------------- -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) Comment: Using GnuPG with Icedove - http://www.enigmail.net/ iQEcBAEBAgAGBQJSbYEoAAoJEKZ75usGhR84MhYH/0owEQorV8thQXP76iBlBmI1 bsfGQ6PjEukHgVImDaItmSm1Tq18RcAo7G9/1bPeIl0VcFAPYglVkpECmuukKZNz zyu7PjT/jsTd76NDRRmDyut5YXaSujKo6YSxWhjWMZGroo4CZaZmQUqUxcz1JKQS caAhpMbxjR2PWW8zeQfJ6KKtVvcV6a7L2NRZiBUIxa4vY9Mu7Yu+7vjJq/QAvJ8j KJ7ZsvG9nkwzPo8iOeUzWRokNyCeVZJc4sevSaVyiImhvPOcoz6cmX2ObJNC6xdX 7RjBf6sC2BFlzrQL4b3w9c3LJPPbnv3Up6vGBVvt+7b0NQHL7CBdtzIxUoA9M9U= =P+W6 -----END PGP SIGNATURE-----

6 years, 7 months

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[commit] r1762 - trunk

by repository service

Author: stefanct Date: Sat Oct 26 19:02:03 2013 New Revision: 1762 URL: http://flashrom.org/trac/flashrom/changeset/1762 Log: Add board enable for abit BF6. Because the board does not have any PCI subsystem IDs set and the DMI strings are not very specific at all, autodetection has been disabled. The GPIO was found by roxfan and the patch tested on hardware by Gelip, thanks! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Oct 25 02:33:37 2013 (r1761) +++ trunk/board_enable.c Sat Oct 26 19:02:03 2013 (r1762) @@ -2266,13 +2266,13 @@ * NOTE: Please add boards that _don't_ need such enables or don't work yet * to the respective tables in print.c. Thanks! * - * We use 2 sets of IDs here, you're free to choose which is which. This + * We use 2 sets of PCI IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles * subsystem/card IDs in a sane manner. * * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs - * NULLed if they don't identify the board fully and if you can't use DMI. + * and the dmi identifier NULLed if they don't identify the board fully to disable autodetection. * But please take care to provide an as complete set of pci ids as possible; * autodetection is the preferred behaviour and we would like to make sure that * matches are unique. @@ -2306,6 +2306,7 @@ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Oct 25 02:33:37 2013 (r1761) +++ trunk/print.c Sat Oct 26 19:02:03 2013 (r1762) @@ -530,6 +530,7 @@ B("abit", "AN-M2", OK, NULL, NULL), B("abit", "AV8", OK, NULL, NULL), B("abit", "AX8", OK, NULL, NULL), + B("abit", "BF6", OK, NULL, NULL), B("abit", "BM6", OK, NULL, NULL), B("abit", "Fatal1ty F-I90HD", OK, NULL, NULL), B("abit", "IC7", OK, NULL, NULL),

6 years, 7 months

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flashing supermicro X8DT6-F/DTE-F motherboard

by Ryan VanRiper

Hi, I have a supermicro X8DT6-F/DTE-F motherboard with a broken IPMI BMC controller (AFAICT). The bios at POST sits for a very log time trying to "initialize IPMI" and eventually fails. I have contacted supermicro tech support about reflashing the BMC IPMI software with one of their online images, but have been unsuccessful using the recommended yafukcs tool. The tool gives the errors.. Error in SendTimedImbRequest Error in Getting FMH Info Error in FirmwareInfo The supermicro techs gave up quick and simply said RMA it. I was wondering if anyone has had success using flashrom to reflash the Nuvoton WPCM450RA0BX chip that is on this board ? If so could you explain how and which programmer you used ? I'm also interested in general approaches even if this has not been done before to try. At this point I don't think I can make things any worse. Thanks, Ryan FYI Here is output from flashrom on the board: ./flashrom -V --programmer internal flashrom v0.9.7-r1711 on Linux 2.6.32-358.18.1.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, GCC 4.4.7 20120313 (Red Hat 4.4.7-3), little endian Command line (3 args): ./flashrom -V --programmer internal Calibrating delay loop... OS timer resolution is 1 usecs, 1195M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1004 us, 10000 myus = 10005 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X8DT6" DMI string system-version: "1234567890" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X8DT6" DMI string baseboard-version: "1234567890" DMI string chassis-type: "Main Server Chassis" Found Winbond Super I/O, id 0x52 Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=0, FLOCKDN=0 Programming OPCODES... done 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004130 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605D/MX25L1608D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205(A)" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3206E" (4096 kB, SPI) at physical address 0xffc00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Multiple flash chip definitions match the detected chip(s): "MX25L3205(A)", "MX25L3205D/MX25L3208D", "MX25L3206E" Please specify which chip definition to use with the -c <chipname> option. Restoring MMIO space at 0x7f754100c8a0 Restoring MMIO space at 0x7f754100c89c Restoring MMIO space at 0x7f754100c898 Restoring MMIO space at 0x7f754100c896 Restoring MMIO space at 0x7f754100c894 Restoring PCI config space for 00:1f:0 reg 0xdc

6 years, 7 months

2
3
0 0

Asrock 960GM-GS3 FX

by Fuley Istvan

Hello, I just would like to report a successful bios update with flashrom on my Asrock 960GM-GS3 FX moteherboard. Everything worked perfect using flashrom -w ./960GMGF1.40 -V -p internal server:/home/ifuley # flashrom -p internal flashrom v0.9.6.1-r1564 on Linux 3.7.10-1.1-desktop (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Winbond flash chip "W25Q80" (1024 kB, SPI) at physical address 0xfff00000. No operations were specified. Thanks, and keep up the good work, István

6 years, 7 months

2
1
0 0

Re: [flashrom] [PATCH] Refactor Intel Chipset Enables.

by Stefan Tauner

On Sat, 21 Sep 2013 05:15:35 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - Combine enable_flash_ich_4e() and enable_flash_ich_dc() to > enable_flash_ich_fwh(). > - Remove unjustified (chipset) name parameters from various > enable_flash_ich* functions. > - Make Poulsbo and Tunnel Creek use generic enables by refining existing > functions to work with them, including everything in ichspi.c. > - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for > all chipsets. > - Add support for Intel Atom Centerton (S12x0). > - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally > anyway. > - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi() > - Various small cleanups. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Self-acked and committed in r1761. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

6 years, 7 months

1
0
0 0

[commit] r1761 - trunk

by repository service

Author: stefanct Date: Fri Oct 25 02:33:37 2013 New Revision: 1761 URL: http://flashrom.org/trac/flashrom/changeset/1761 Log: Refactor Intel Chipset Enables. - Combine enable_flash_ich_4e() and enable_flash_ich_dc() to enable_flash_ich_fwh(). - Remove unjustified (chipset) name parameters from various enable_flash_ich* functions. - Make Poulsbo and Tunnel Creek use generic enables by refining existing functions to work with them, including everything in ichspi.c. - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for all chipsets. - Add support for Intel Atom Centerton (S12x0). - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally anyway. - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi() - Various small cleanups. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/ichspi.c trunk/programmer.h Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Oct 21 23:49:08 2013 (r1760) +++ trunk/chipset_enable.c Fri Oct 25 02:33:37 2013 (r1761) @@ -260,20 +260,44 @@ return 0; } -/* - * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" - * http://download.intel.com/design/chipsets/datashts/30701303.pdf - */ -static int enable_flash_ich(struct pci_dev *dev, const char *name, uint8_t bios_cntl) +/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom + * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ +static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) { uint8_t old, new, wanted; - /* - * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Tunnel Creek it is even 32b, but - * just treating it as 8 bit wide seems to work fine in practice. - */ - wanted = old = pci_read_byte(dev, bios_cntl); + switch (ich_generation) { + case CHIPSET_ICH_UNKNOWN: + return ERROR_FATAL; + /* Non-SPI-capable */ + case CHIPSET_ICH: + case CHIPSET_ICH2345: + break; + /* Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to what + * other SPI-capable chipsets have at DCh. + * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it + * mentions that the prefetching and caching does only happen for direct memory reads. + * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the + * programmed access only and not memory mapping. */ + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_POULSBO: + case CHIPSET_CENTERTON: + old = pci_read_byte(dev, bios_cntl + 1); + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); + break; + case CHIPSET_ICH7: + default: /* Future version might behave the same */ + old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; + msg_pdbg("SPI Read Configuration: "); + if (old == 3) + msg_pdbg("invalid prefetching/caching settings, "); + else + msg_pdbg("prefetching %sabled, caching %sabled, ", + (old & 0x2) ? "en" : "dis", + (old & 0x1) ? "dis" : "en"); + } + wanted = old = pci_read_byte(dev, bios_cntl); /* * Quote from the 6 Series datasheet (Document Number: 324645-004): * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) @@ -283,11 +307,23 @@ * * Try to unset it in any case. * It won't hurt and makes sense in some cases according to Stefan Reinauer. + * + * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom + * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway. */ - wanted &= ~(1 << 5); + int smm_bwp_bit; + if (ich_generation == CHIPSET_CENTERTON) + smm_bwp_bit = 7; + else + smm_bwp_bit = 5; + wanted &= ~(1 << smm_bwp_bit); + + /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */ + if (ich_generation == CHIPSET_TUNNEL_CREEK) + wanted |= (1 << 2); - /* Set BIOS Write Enable */ - wanted |= (1 << 0); + wanted |= (1 << 0); /* Set BIOS Write Enable */ + wanted &= ~(1 << 1); /* Disable lock (futile) */ /* Only write the register if it's necessary */ if (wanted != old) { @@ -299,76 +335,77 @@ msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new); msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis"); msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis"); - if (new & (1 << 5)) + if (new & (1 << smm_bwp_bit)) msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); - if (new != wanted) - msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x on %s failed.\n" - "New value is 0x%02x.\n", bios_cntl, old, wanted, name, new); + msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" + "New value is 0x%02x.\n", bios_cntl, old, wanted, new); - /* Return an error if we could not set the write enable */ + /* Return an error if we could not set the write enable only. */ if (!(new & (1 << 0))) return -1; return 0; } -static int enable_flash_ich0(struct pci_dev *dev, const char *name) +static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) { - internal_buses_supported = BUS_FWH; - /* FIXME: Make this use enable_flash_ich_4e() too and add IDSEL support. Unlike later chipsets, - * ICH and ICH-0 do only support mapping of the top-most 4MB and therefore do only feature - * FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ - return enable_flash_ich(dev, name, 0x4e); -} - -static int enable_flash_ich_fwh_decode(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) -{ - uint32_t fwh_conf; - uint8_t fwh_sel1, fwh_sel2, fwh_dec_en_lo, fwh_dec_en_hi; - int i, tmp; - char *idsel = NULL; - int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; - int contiguous = 1; - - if (ich_generation >= CHIPSET_ICH6) { - fwh_sel1 = 0xd0; - fwh_sel2 = 0xd4; - fwh_dec_en_lo = 0xd8; - fwh_dec_en_hi = 0xd9; - } else if (ich_generation >= CHIPSET_ICH2) { + uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ + bool implemented = 0; + switch (ich_generation) { + case CHIPSET_ICH: + /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB + * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ + break; + case CHIPSET_ICH2345: fwh_sel1 = 0xe8; fwh_sel2 = 0xee; fwh_dec_en_lo = 0xf0; fwh_dec_en_hi = 0xe3; - } else { - msg_perr("Error: FWH decode setting not implemented.\n"); - return ERROR_FATAL; + implemented = 1; + break; + case CHIPSET_POULSBO: + case CHIPSET_TUNNEL_CREEK: + /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each, + * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */ + break; + case CHIPSET_CENTERTON: + /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ + break; + case CHIPSET_ICH6: + case CHIPSET_ICH7: + default: /* Future version might behave the same */ + fwh_sel1 = 0xd0; + fwh_sel2 = 0xd4; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + implemented = 1; + break; } - idsel = extract_programmer_param("fwh_idsel"); + char *idsel = extract_programmer_param("fwh_idsel"); if (idsel && strlen(idsel)) { - uint64_t fwh_idsel_old, fwh_idsel; + if (!implemented) { + msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); + goto idsel_garbage_out; + } errno = 0; /* Base 16, nothing else makes sense. */ - fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16); + uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16); if (errno) { - msg_perr("Error: fwh_idsel= specified, but value could " - "not be converted.\n"); + msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); goto idsel_garbage_out; } if (fwh_idsel & 0xffff000000000000ULL) { - msg_perr("Error: fwh_idsel= specified, but value had " - "unused bits set.\n"); + msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); goto idsel_garbage_out; } - fwh_idsel_old = pci_read_long(dev, fwh_sel1); + uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); fwh_idsel_old <<= 16; fwh_idsel_old |= pci_read_word(dev, fwh_sel2); - msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to " - "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old, - fwh_idsel); + msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.", + fwh_idsel_old, fwh_idsel); rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ @@ -380,15 +417,23 @@ } free(idsel); + if (!implemented) { + msg_pdbg2("FWH IDSEL handling is not implemented on this chipset."); + return 0; + } + /* Ignore all legacy ranges below 1 MB. * We currently only support flashing the chip which responds to * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations * have to be adjusted. */ + int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; + bool contiguous = 1; + uint32_t fwh_conf = pci_read_long(dev, fwh_sel1); + int i; /* FWH_SEL1 */ - fwh_conf = pci_read_long(dev, fwh_sel1); for (i = 7; i >= 0; i--) { - tmp = (fwh_conf >> (i * 4)) & 0xf; + int tmp = (fwh_conf >> (i * 4)) & 0xf; msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, @@ -402,7 +447,7 @@ /* FWH_SEL2 */ fwh_conf = pci_read_word(dev, fwh_sel2); for (i = 3; i >= 0; i--) { - tmp = (fwh_conf >> (i * 4)) & 0xf; + int tmp = (fwh_conf >> (i * 4)) & 0xf; msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, @@ -419,7 +464,7 @@ fwh_conf <<= 8; fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); for (i = 7; i >= 0; i--) { - tmp = (fwh_conf >> (i + 0x8)) & 0x1; + int tmp = (fwh_conf >> (i + 0x8)) & 0x1; msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, @@ -431,7 +476,7 @@ } } for (i = 3; i >= 0; i--) { - tmp = (fwh_conf >> i) & 0x1; + int tmp = (fwh_conf >> i) & 0x1; msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, @@ -448,146 +493,56 @@ return 0; } -static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) +static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) { int err; /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) + if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0) return err; internal_buses_supported = BUS_FWH; - return enable_flash_ich(dev, name, 0x4e); + return enable_flash_ich_bios_cntl(dev, ich_generation, bios_cntl); } -static int enable_flash_ich2(struct pci_dev *dev, const char *name) -{ - return enable_flash_ich_4e(dev, name, CHIPSET_ICH2); -} - -static int enable_flash_ich3(struct pci_dev *dev, const char *name) -{ - return enable_flash_ich_4e(dev, name, CHIPSET_ICH3); -} - -static int enable_flash_ich4(struct pci_dev *dev, const char *name) +static int enable_flash_ich0(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH4); + return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e); } -static int enable_flash_ich5(struct pci_dev *dev, const char *name) +static int enable_flash_ich2345(struct pci_dev *dev, const char *name) { - return enable_flash_ich_4e(dev, name, CHIPSET_ICH5); -} - -static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation) -{ - int err; - - /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, name, ich_generation)) != 0) - return err; - - /* If we're called by enable_flash_ich_dc_spi, it will override - * internal_buses_supported anyway. - */ - internal_buses_supported = BUS_FWH; - return enable_flash_ich(dev, name, 0xdc); + return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e); } static int enable_flash_ich6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc(dev, name, CHIPSET_ICH6); + return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc); } static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) { - uint16_t old, new; - int err; - - if ((err = enable_flash_ich(dev, name, 0xd8)) != 0) - return err; - - old = pci_read_byte(dev, 0xd9); - msg_pdbg("BIOS Prefetch Enable: %sabled, ", - (old & 1) ? "en" : "dis"); - new = old & ~1; - - if (new != old) - rpci_write_byte(dev, 0xd9, new); - - internal_buses_supported = BUS_FWH; - return 0; -} - -static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) -{ - uint16_t old, new; - uint32_t tmp, bnt; - void *rcrb; - int ret; - - /* Enable Flash Writes */ - ret = enable_flash_ich(dev, name, 0xd8); - if (ret == ERROR_FATAL) - return ret; - - /* Make sure BIOS prefetch mechanism is disabled */ - old = pci_read_byte(dev, 0xd9); - msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); - new = old & ~1; - if (new != old) - rpci_write_byte(dev, 0xd9, new); - - /* Get physical address of Root Complex Register Block */ - tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); - - /* Map RCBA to virtual memory */ - rcrb = rphysmap("ICH RCRB", tmp, 0x4000); - if (rcrb == ERROR_PTR) - return ERROR_FATAL; - - /* Test Boot BIOS Strap Status */ - bnt = mmio_readl(rcrb + 0x3410); - if (bnt & 0x02) { - /* If strapped to LPC, no SPI initialization is required */ - internal_buses_supported = BUS_FWH; - return 0; - } - - /* This adds BUS_SPI */ - if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { - if (!ret) - ret = ERROR_NONFATAL; - } - - return ret; + return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } -static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, - enum ich_chipset ich_generation) +static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) { - int ret, ret_spi; - uint8_t bbs, buc; - uint32_t tmp, gcs; - void *rcrb; - const char *const *straps_names; - static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; + static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" }; - static const char *const straps_names_pch8_lp[] = { "SPI", "LPC", "unknown", "unknown" }; + static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; + const char *const *straps_names; switch (ich_generation) { case CHIPSET_ICH7: /* EP80579 may need further changes, but this is the least * intrusive way to get correct BOOT Strap printing without * changing the rest of its code path). */ - if (strcmp(name, "EP80579") == 0) + if (dev->device_id == 0x5031) straps_names = straps_names_EP80579; else straps_names = straps_names_ich7_nm10; @@ -597,6 +552,9 @@ case CHIPSET_ICH10: straps_names = straps_names_ich8910; break; + case CHIPSET_TUNNEL_CREEK: + straps_names = straps_names_tunnel_creek; + break; case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: @@ -609,35 +567,33 @@ straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet + case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all straps_names = straps_names_unknown; break; default: - msg_gerr("%s: unknown ICH generation. Please report!\n", - __func__); + msg_gerr("%s: unknown ICH generation. Please report!\n", __func__); straps_names = straps_names_unknown; break; } - /* Enable Flash Writes */ - ret = enable_flash_ich_dc(dev, name, ich_generation); - if (ret == ERROR_FATAL) - return ret; - /* Get physical address of Root Complex Register Block */ - tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("Root Complex Register Block address = 0x%x\n", tmp); + uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); /* Map RCBA to virtual memory */ - rcrb = rphysmap("ICH RCRB", tmp, 0x4000); + void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); if (rcrb == ERROR_PTR) return ERROR_FATAL; - gcs = mmio_readl(rcrb + 0x3410); + uint32_t gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); - msg_pdbg("BIOS Interface Lock-Down: %sabled, ", - (gcs & 0x1) ? "en" : "dis"); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); + uint8_t bbs; switch (ich_generation) { + case CHIPSET_TUNNEL_CREEK: + bbs = (gcs >> 1) & 0x1; + break; case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet /* Lynx Point LP uses a single bit for GCS */ @@ -650,91 +606,110 @@ } msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - buc = mmio_readb(rcrb + 0x3414); - msg_pdbg("Top Swap : %s\n", - (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); - - /* It seems the ICH7 does not support SPI and LPC chips at the same - * time. At least not with our current code. So we prevent searching - * on ICH7 when the southbridge is strapped to LPC - */ - internal_buses_supported = BUS_FWH; - if (ich_generation == CHIPSET_ICH7) { - if (bbs == 0x03) { - /* If strapped to LPC, no further SPI initialization is - * required. */ - return ret; - } else { - /* Disable LPC/FWH if strapped to PCI or SPI */ - internal_buses_supported = BUS_NONE; - } + if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) { + uint8_t buc = mmio_readb(rcrb + 0x3414); + msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); + } + + /* Handle FWH-related parameters and initialization */ + int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); + if (ret_fwh == ERROR_FATAL) + return ret_fwh; + + /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ + uint16_t spibar_offset; + switch (ich_generation) { + case CHIPSET_ICH_UNKNOWN: + return ERROR_FATAL; + case CHIPSET_ICH7: + case CHIPSET_ICH8: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: + spibar_offset = 0x3020; + break; + case CHIPSET_ICH9: + default: /* Future version might behave the same */ + spibar_offset = 0x3800; + break; } + msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset); + void *spibar = rcrb + spibar_offset; /* This adds BUS_SPI */ - ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation); + int ret_spi = ich_init_spi(dev, spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; - if (ret || ret_spi) - ret = ERROR_NONFATAL; + if (ret_fwh || ret_spi) + return ERROR_NONFATAL; - return ret; + return 0; +} + +static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8); +} + +static int enable_flash_s12x0(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8); } static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7); + return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8); + return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9); + return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10); + return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK); + return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT); + return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); } /* Panther Point aka. 7 series */ static int enable_flash_pch7(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_7_SERIES_PANTHER_POINT); + return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); } /* Lynx Point aka. 8 series */ static int enable_flash_pch8(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT); + return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); } -/* Lynx Point aka. 8 series low-power */ +/* Lynx Point LP aka. 8 series low-power */ static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_LYNX_POINT_LP); + return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); } /* Wellsburg (for Haswell-EP Xeons) */ static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) { - return enable_flash_ich_dc_spi(dev, name, CHIPSET_8_SERIES_WELLSBURG); + return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } static int via_no_byte_merge(struct pci_dev *dev, const char *name) @@ -1503,6 +1478,7 @@ {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, + {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6}, @@ -1541,15 +1517,15 @@ {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2}, - {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich3}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich3}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich4}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich4}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich5}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich5}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, + {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Oct 21 23:49:08 2013 (r1760) +++ trunk/ichspi.c Fri Oct 25 02:33:37 2013 (r1761) @@ -466,6 +466,8 @@ switch (ich_generation) { case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); @@ -529,7 +531,7 @@ opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); } - /*Program Allowable Opcodes 4 - 7 */ + /* Program Allowable Opcodes 4 - 7 */ opmenu[1] = 0; for (a = 4; a < 8; a++) { opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); @@ -538,6 +540,8 @@ msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (ich_generation) { case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -603,6 +607,8 @@ int bbar_off; switch (ich_generation) { case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: bbar_off = 0x50; break; case CHIPSET_ICH8: @@ -975,6 +981,8 @@ switch (ich_generation) { case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: return ich7_run_opcode(op, offset, datalength, data, maxlength); case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1545,12 +1553,10 @@ .erase = ich_hwseq_block_erase, }; -int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - enum ich_chipset ich_gen) +int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) { int i; - uint8_t old, new; - uint16_t spibar_offset, tmp2; + uint16_t tmp2; uint32_t tmp; char *arg; int ich_spi_force = 0; @@ -1564,42 +1570,18 @@ } ich_spi_mode = ich_auto; ich_generation = ich_gen; - - switch (ich_generation) { - case CHIPSET_ICH_UNKNOWN: - return ERROR_FATAL; - case CHIPSET_ICH7: - case CHIPSET_ICH8: - spibar_offset = 0x3020; - break; - case CHIPSET_ICH9: - default: /* Future version might behave the same */ - spibar_offset = 0x3800; - break; - } - - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); - - /* Assign Virtual Address */ - ich_spibar = rcrb + spibar_offset; + ich_spibar = spibar; switch (ich_generation) { case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); - for (i = 0; i < 8; i++) { - int offs; - offs = 8 + (i * 8); - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(ich_spibar + offs + 4), i); - } ichspi_bbar = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); @@ -1811,21 +1793,6 @@ break; } - old = pci_read_byte(dev, 0xdc); - msg_pdbg("SPI Read Configuration: "); - new = (old >> 2) & 0x3; - switch (new) { - case 0: - case 1: - case 2: - msg_pdbg("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", - (new & 0x1) ? "dis" : "en"); - break; - default: - msg_pdbg("invalid prefetching/caching settings, "); - break; - } return 0; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Mon Oct 21 23:49:08 2013 (r1760) +++ trunk/programmer.h Fri Oct 25 02:33:37 2013 (r1761) @@ -557,11 +557,12 @@ /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ enum ich_chipset { CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH2 = 2, - CHIPSET_ICH3, - CHIPSET_ICH4, - CHIPSET_ICH5, + CHIPSET_ICH, + CHIPSET_ICH2345, CHIPSET_ICH6, + CHIPSET_POULSBO, /* SCH U* */ + CHIPSET_TUNNEL_CREEK, /* Atom E6xx */ + CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */ CHIPSET_ICH7, CHIPSET_ICH8, CHIPSET_ICH9, @@ -577,8 +578,7 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; -int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - enum ich_chipset ich_generation); +int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_generation); int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); /* amd_imc.c */

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flashrom October 2013