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flashrom January 2013

flashrom@flashrom.org

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[PATCH 4/5] uintptr_t-ify physmap.c.
by Stefan Tauner 01 Jan '13

01 Jan '13

unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in physmap.c where applicable. This should be done in a lot of other places in flashrom too, but that's a huge pile of work and we better start it with a small step than never (which is the forseeable alternative ;) This patch also changes the display width of all address values in physmap.c to 16/8 hex … [View More]characters depending on the architecture. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- physmap.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/physmap.c b/physmap.c index a9445d5..8b9fea7 100644 --- a/physmap.c +++ b/physmap.c @@ -20,6 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <inttypes.h> #include <unistd.h> #include <stdbool.h> #include <stdio.h> @@ -35,6 +36,8 @@ #include <errno.h> #endif +#define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) + #ifdef __DJGPP__ #include <dpmi.h> #include <sys/nearptr.h> @@ -43,7 +46,7 @@ static void *realmem_map; -static void *map_first_meg(unsigned long phys_addr, size_t len) +static void *map_first_meg(uintptr_t phys_addr, size_t len) { if (realmem_map) return realmem_map + phys_addr; @@ -62,7 +65,7 @@ static void *map_first_meg(unsigned long phys_addr, size_t len) return realmem_map + phys_addr; } -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { int ret; __dpmi_meminfo mi; @@ -110,7 +113,7 @@ void physunmap(void *virt_addr, size_t len) #define MEM_DEV "" -void *sys_physmap(unsigned long phys_addr, size_t len) +void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } @@ -134,7 +137,7 @@ void cleanup_cpu_msr(void) #define MEM_DEV "DirectHW" -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { /* The short form of ?: is a GNU extension. * FIXME: map_physical returns NULL both for errors and for success @@ -166,7 +169,7 @@ static int fd_mem = -1; static int fd_mem_cached = -1; /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ -static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) +static void *sys_physmap_rw_uncached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -186,7 +189,7 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* For reading DMI/coreboot/whatever tables. We should never write, and we * do not care about caching. */ -static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +static void *sys_physmap_ro_cached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -232,14 +235,13 @@ static int physmap_shutdown(void *data) return 0; } -static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, +static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool mayfail, bool readonly, bool autocleanup) { void *virt_addr; if (len == 0) { - msg_pspew("Not mapping %s, zero size at 0x%08lx.\n", - descr, phys_addr); + msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr); return ERROR_PTR; } @@ -261,8 +263,8 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, size_t l if (ERROR_PTR == virt_addr) { if (NULL == descr) descr = "memory"; - msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, - (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%0zx bytes at 0x%0*" PRIxPTR "\n", + descr, len, PRIxPTR_WIDTH, phys_addr); perror(MEM_DEV " mmap failed"); #ifdef __linux__ if (EINVAL == errno) { @@ -302,17 +304,17 @@ unmap_out: return ERROR_PTR; } -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, false, false, false); } -void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len) +void *physmap_autocleanup(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, false, false, true); } -void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, true, true, false); } -- Kind regards, Stefan Tauner [View Less]

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[PATCH 3/5] Automatically unmap physmap()s.
by Stefan Tauner 01 Jan '13

01 Jan '13

Similarly to the previous PCI self-clean up patch this one allows to get rid of a huge number of programmer shutdown functions and makes introducing bugs harder. It adds a new function physmap_autocleanup() that takes care of unmapping at shutdown. Callers are changed where it makes sense. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 12 +++++++----- drkaiser.c | 12 ++---------- gfxnvidia.c | 11 ++--------- ichspi.c … [View More] | 4 +++- it85spi.c | 3 +++ mcp6x_spi.c | 15 +++++---------- nicintel.c | 22 +++------------------- nicintel_spi.c | 10 +++------- ogp_spi.c | 11 ++--------- physmap.c | 54 ++++++++++++++++++++++++++++++++++++++++++++---------- programmer.h | 1 + satamv.c | 11 +---------- satasii.c | 14 ++++---------- sb600spi.c | 6 ++++-- 14 files changed, 84 insertions(+), 102 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 0dc1d7e..0635268 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -480,7 +480,9 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ - rcrb = physmap("ICH RCRB", tmp, 0x4000); + rcrb = physmap_autocleanup("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return 1; /* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -551,7 +553,9 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, msg_pdbg("Root Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ - rcrb = physmap("ICH RCRB", tmp, 0x4000); + rcrb = physmap_autocleanup("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return 1; gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -703,10 +707,8 @@ static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) case 0x8410: /* VX900 */ mmio_base = pci_read_long(dev, 0xbc) << 8; mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); - if (mmio_base_physmapped == ERROR_PTR) { - physunmap(mmio_base_physmapped, SPI_CNTL_LEN); + if (mmio_base_physmapped == ERROR_PTR) return ERROR_FATAL; - } /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; diff --git a/drkaiser.c b/drkaiser.c index a6eca1c..062ec73 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -56,12 +56,6 @@ static const struct par_programmer par_programmer_drkaiser = { .chip_writen = fallback_chip_writen, }; -static int drkaiser_shutdown(void *data) -{ - physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); - return 0; -} - int drkaiser_init(void) { uint32_t addr; @@ -77,10 +71,8 @@ int drkaiser_init(void) PCI_MAGIC_DRKAISER_VALUE); /* Map 128kB flash memory window. */ - drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", - addr, DRKAISER_MEMMAP_SIZE); - - if (register_shutdown(drkaiser_shutdown, NULL)) + drkaiser_bar = physmap_autocleanup("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); + if (drkaiser_bar == ERROR_PTR) return 1; max_rom_decode.parallel = 128 * 1024; diff --git a/gfxnvidia.c b/gfxnvidia.c index a994d68..ec63cf6 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -77,12 +77,6 @@ static const struct par_programmer par_programmer_gfxnvidia = { .chip_writen = fallback_chip_writen, }; -static int gfxnvidia_shutdown(void *data) -{ - physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); - return 0; -} - int gfxnvidia_init(void) { uint32_t reg32; @@ -96,9 +90,8 @@ int gfxnvidia_init(void) io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); - nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); - - if (register_shutdown(gfxnvidia_shutdown, NULL)) + nvidia_bar = physmap_autocleanup("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); + if (nvidia_bar == ERROR_PTR) return 1; /* Allow access to flash interface (will disable screen). */ diff --git a/ichspi.c b/ichspi.c index fadfe62..4b52745 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1845,7 +1845,9 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) { int i; - ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + ich_spibar = physmap_autocleanup("VIA SPI MMIO registers", mmio_base, 0x70); + if (ich_spibar == ERROR_PTR) + return ERROR_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ diff --git a/it85spi.c b/it85spi.c index 0b074eb..b778436 100644 --- a/it85spi.c +++ b/it85spi.c @@ -262,6 +262,9 @@ static int it85xx_spi_common_init(struct superio s) * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); + if (base == ERROR_PTR) + return 1; + msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ diff --git a/mcp6x_spi.c b/mcp6x_spi.c index ac40557..0c519eb 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -135,25 +135,20 @@ int mcp6x_spi_init(int want_spi) /* Accessing a NULL pointer BAR is evil. Don't do it. */ if (!mcp6x_spibaraddr && want_spi) { - msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR " - "is invalid.\n"); + msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR is invalid.\n"); return 1; } else if (!mcp6x_spibaraddr && !want_spi) { msg_pdbg("MCP SPI is not used.\n"); return 0; } else if (mcp6x_spibaraddr && !want_spi) { - msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently" - " doesn't have SPI enabled.\n"); + msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled.\n"); /* FIXME: Should we enable SPI anyway? */ return 0; } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); - -#if 0 - /* FIXME: Run the physunmap in a shutdown function. */ - physunmap(mcp6x_spibar, 0x544); -#endif + mcp6x_spibar = physmap_autocleanup("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); + if (mcp6x_spibar == ERROR_PTR) + return 1; status = mmio_readw(mcp6x_spibar + 0x530); msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", diff --git a/nicintel.c b/nicintel.c index 8481915..5463af2 100644 --- a/nicintel.c +++ b/nicintel.c @@ -59,13 +59,6 @@ static const struct par_programmer par_programmer_nicintel = { .chip_writen = fallback_chip_writen, }; -static int nicintel_shutdown(void *data) -{ - physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); - physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); - return 0; -} - int nicintel_init(void) { uintptr_t addr; @@ -81,19 +74,15 @@ int nicintel_init(void) */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); - nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); + nicintel_bar = physmap_autocleanup("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) - goto error_out_unmap; + return 1; /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */ addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0); /* FIXME: This is not an aligned mapping. Use 4k? */ - nicintel_control_bar = physmap("Intel NIC control/status reg", - addr, NICINTEL_CONTROL_MEMMAP_SIZE); + nicintel_control_bar = physmap_autocleanup("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); if (nicintel_control_bar == ERROR_PTR) - goto error_out; - - if (register_shutdown(nicintel_shutdown, NULL)) return 1; /* FIXME: This register is pretty undocumented in all publicly available @@ -111,11 +100,6 @@ int nicintel_init(void) register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; - -error_out_unmap: - physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); -error_out: - return 1; } static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, diff --git a/nicintel_spi.c b/nicintel_spi.c index f61c2b1..8630f3f 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -151,16 +151,12 @@ static int nicintel_spi_shutdown(void *data) { uint32_t tmp; - /* Disable writes manually. See the comment about EECD in - * nicintel_spi_init() for details. - */ + /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; pci_mmio_writel(tmp, nicintel_spibar + EECD); - physunmap(nicintel_spibar, MEMMAP_SIZE); - return 0; } @@ -174,8 +170,8 @@ int nicintel_spi_init(void) /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); - nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", - io_base_addr, MEMMAP_SIZE); + nicintel_spibar = physmap_autocleanup("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be diff --git a/ogp_spi.c b/ogp_spi.c index 6fb1a77..d66b2ef 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -97,12 +97,6 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { .half_period = 0, }; -static int ogp_spi_shutdown(void *data) -{ - physunmap(ogp_spibar, 4096); - return 0; -} - int ogp_spi_init(void) { char *type; @@ -133,9 +127,8 @@ int ogp_spi_init(void) io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); - ogp_spibar = physmap("OGP registers", io_base_addr, 4096); - - if (register_shutdown(ogp_spi_shutdown, NULL)) + ogp_spibar = physmap_autocleanup("OGP registers", io_base_addr, 4096); + if (ogp_spibar == ERROR_PTR) return 1; if (bitbang_spi_init(&bitbang_spi_master_ogp)) diff --git a/physmap.c b/physmap.c index 5aa9874..a9445d5 100644 --- a/physmap.c +++ b/physmap.c @@ -21,6 +21,7 @@ */ #include <unistd.h> +#include <stdbool.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -214,13 +215,25 @@ void physunmap(void *virt_addr, size_t len) } #endif -#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 -#define PHYSMAP_RW 0 -#define PHYSMAP_RO 1 +struct physmap_stutdown_data { + void *addr; + size_t len; +}; -static void *physmap_common(const char *descr, unsigned long phys_addr, - size_t len, int mayfail, int readonly) +static int physmap_shutdown(void *data) +{ + if (data == NULL) { + msg_perr("%s: tried to shutdown without valid data!\n", __func__); + return 1; + } + struct physmap_stutdown_data *d = data; + physunmap(d->addr, d->len); + free(data); + return 0; +} + +static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, + bool readonly, bool autocleanup) { void *virt_addr; @@ -268,19 +281,40 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, exit(3); } + if (autocleanup) { + struct physmap_stutdown_data *d = malloc(sizeof(struct physmap_stutdown_data)); + if (d == NULL) { + msg_perr("%s: Out of memory!\n", __func__); + goto unmap_out; + } + + d->addr = virt_addr; + d->len = len; + if (register_shutdown(physmap_shutdown, d) != 0) { + msg_perr("%s: Could not register shutdown function!\n", __func__); + goto unmap_out; + } + } + return virt_addr; +unmap_out: + physunmap(virt_addr, len); + return ERROR_PTR; } void *physmap(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, - PHYSMAP_RW); + return physmap_common(descr, phys_addr, len, false, false, false); +} + +void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, false, false, true); } void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, - PHYSMAP_RO); + return physmap_common(descr, phys_addr, len, true, true, false); } #if defined(__i386__) || defined(__x86_64__) diff --git a/programmer.h b/programmer.h index 4302809..77b78bd 100644 --- a/programmer.h +++ b/programmer.h @@ -272,6 +272,7 @@ int processor_flash_enable(void); /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len); void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 diff --git a/satamv.c b/satamv.c index 46a0e2d..726dd5a 100644 --- a/satamv.c +++ b/satamv.c @@ -57,12 +57,6 @@ static const struct par_programmer par_programmer_satamv = { .chip_writen = fallback_chip_writen, }; -static int satamv_shutdown(void *data) -{ - physunmap(mv_bar, 0x20000); - return 0; -} - /* * Random notes: * FCE# Flash Chip Enable @@ -93,13 +87,10 @@ int satamv_init(void) */ addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); - mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + mv_bar = physmap_autocleanup("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) return 1; - if (register_shutdown(satamv_shutdown, NULL)) - return 1; - tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); msg_pspew("Flash Parameters:\n"); msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); diff --git a/satasii.c b/satasii.c index 730c420..36f4cd1 100644 --- a/satasii.c +++ b/satasii.c @@ -54,12 +54,6 @@ static const struct par_programmer par_programmer_satasii = { .chip_writen = fallback_chip_writen, }; -static int satasii_shutdown(void *data) -{ - physunmap(sii_bar, SATASII_MEMMAP_SIZE); - return 0; -} - static uint32_t satasii_wait_done(void) { uint32_t ctrl_reg; @@ -94,15 +88,15 @@ int satasii_init(void) reg_offset = 0x50; } - sii_bar = physmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE) + reg_offset; + sii_bar = physmap_autocleanup("SATA SiI registers", addr, SATASII_MEMMAP_SIZE); + if (sii_bar == ERROR_PTR) + return 1; + sii_bar += reg_offset; /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - if (register_shutdown(satasii_shutdown, NULL)) - return 1; - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); return 0; diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..7888bb9 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -224,8 +224,10 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); + sb600_spibar = physmap_autocleanup("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (sb600_spibar == ERROR_PTR) + return 1; + /* The low bits of the SPI base address are used as offset into * the mapped page. */ -- Kind regards, Stefan Tauner [View Less]

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[PATCH 2/5] Add pci_init_common() to unify PCI init.
by Stefan Tauner 01 Jan '13

01 Jan '13

Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- internal.c | 6 ++---- pcidev.c | 15 +++++++++++---- programmer.h | 1 + 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/internal.c b/… [View More]internal.c index eda4d59..9b34715 100644 --- a/internal.c +++ b/internal.c @@ -245,10 +245,8 @@ int internal_init(void) internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ - pacc = pci_alloc(); /* Get the pci_access structure */ - /* Set all options you want -- here we stick with the defaults */ - pci_init(pacc); /* Initialize the PCI library */ - pci_scan_bus(pacc); /* We want to get the list of devices */ + if(pci_init_common() != 0) + return 1; if (processor_flash_enable()) { msg_perr("Processor detection/init failed.\n" diff --git a/pcidev.c b/pcidev.c index 37bcc22..a5a7088 100644 --- a/pcidev.c +++ b/pcidev.c @@ -162,6 +162,16 @@ static int pcidev_shutdown(void *data) return 0; } +int pci_init_common(void) +{ + pacc = pci_alloc(); /* Get the pci_access structure */ + pci_init(pacc); /* Initialize the PCI library */ + if (register_shutdown(pcidev_shutdown, NULL)) + return 1; + pci_scan_bus(pacc); /* We want to get the list of devices */ + return 0; +} + uintptr_t pcidev_init(int bar, const struct dev_entry *devs) { struct pci_dev *dev; @@ -172,11 +182,8 @@ uintptr_t pcidev_init(int bar, const struct dev_entry *devs) int i; uintptr_t addr = 0, curaddr = 0; - pacc = pci_alloc(); /* Get the pci_access structure */ - pci_init(pacc); /* Initialize the PCI library */ - if (register_shutdown(pcidev_shutdown, NULL)) + if(pci_init_common() != 0) return 1; - pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); /* Filter by bb:dd.f (if supplied by the user). */ diff --git a/programmer.h b/programmer.h index 8de42bc..4302809 100644 --- a/programmer.h +++ b/programmer.h @@ -238,6 +238,7 @@ void internal_delay(int usecs); extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_dev *pcidev_dev; +int pci_init_common(void); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); uintptr_t pcidev_init(int bar, const struct dev_entry *devs); /* rpci_write_* are reversible writes. The original PCI config space register -- Kind regards, Stefan Tauner [View Less]

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[PATCH 1/5] Let pcidev clean itself up.
by Stefan Tauner 01 Jan '13

01 Jan '13

We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- atahpt.c | 10 ---------- drkaiser.c | 3 +-- gfxnvidia.c | 6 +----- … [View More] nic3com.c | 2 +- nicintel.c | 5 +---- nicintel_spi.c | 2 +- nicrealtek.c | 7 +++++-- ogp_spi.c | 2 -- pcidev.c | 15 +++++++++++++++ satamv.c | 7 +------ satasii.c | 1 - 11 files changed, 26 insertions(+), 34 deletions(-) diff --git a/atahpt.c b/atahpt.c index 461191d..d19cb75 100644 --- a/atahpt.c +++ b/atahpt.c @@ -56,13 +56,6 @@ static const struct par_programmer par_programmer_atahpt = { .chip_writen = fallback_chip_writen, }; -static int atahpt_shutdown(void *data) -{ - /* Flash access is disabled automatically by PCI restore. */ - pci_cleanup(pacc); - return 0; -} - int atahpt_init(void) { uint32_t reg32; @@ -72,9 +65,6 @@ int atahpt_init(void) io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); - if (register_shutdown(atahpt_shutdown, NULL)) - return 1; - /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); diff --git a/drkaiser.c b/drkaiser.c index e461061..a6eca1c 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -59,8 +59,6 @@ static const struct par_programmer par_programmer_drkaiser = { static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); - /* Flash write is disabled automatically by PCI restore. */ - pci_cleanup(pacc); return 0; } @@ -71,6 +69,7 @@ int drkaiser_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); /* Write magic register to enable flash write. */ diff --git a/gfxnvidia.c b/gfxnvidia.c index 624fd7c..a994d68 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -80,10 +80,6 @@ static const struct par_programmer par_programmer_gfxnvidia = { static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); - /* Flash interface access is disabled (and screen enabled) automatically - * by PCI restore. - */ - pci_cleanup(pacc); return 0; } @@ -94,6 +90,7 @@ int gfxnvidia_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; @@ -101,7 +98,6 @@ int gfxnvidia_init(void) nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); - /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) return 1; diff --git a/nic3com.c b/nic3com.c index 05eada6..4ec6193 100644 --- a/nic3com.c +++ b/nic3com.c @@ -81,7 +81,6 @@ static int nic3com_shutdown(void *data) OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); } - pci_cleanup(pacc); return 0; } @@ -90,6 +89,7 @@ int nic3com_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); id = pcidev_dev->device_id; diff --git a/nicintel.c b/nicintel.c index d210d78..8481915 100644 --- a/nicintel.c +++ b/nicintel.c @@ -63,7 +63,6 @@ static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -77,8 +76,7 @@ int nicintel_init(void) if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. + /* No need to check for errors, pcidev_init() will not return in case of errors. * FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); @@ -117,7 +115,6 @@ int nicintel_init(void) error_out_unmap: physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); error_out: - pci_cleanup(pacc); return 1; } diff --git a/nicintel_spi.c b/nicintel_spi.c index 325e61c..f61c2b1 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -160,7 +160,6 @@ static int nicintel_spi_shutdown(void *data) pci_mmio_writel(tmp, nicintel_spibar + EECD); physunmap(nicintel_spibar, MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -172,6 +171,7 @@ int nicintel_spi_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", diff --git a/nicrealtek.c b/nicrealtek.c index 3c3b261..0929e5d 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -51,22 +51,25 @@ static const struct par_programmer par_programmer_nicrealtek = { .chip_writen = fallback_chip_writen, }; +#if 0 static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ - pci_cleanup(pacc); return 0; } +#endif int nicrealtek_init(void) { if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - +#if 0 if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; +#endif /* Beware, this ignores the vendor ID! */ switch (pcidev_dev->device_id) { diff --git a/ogp_spi.c b/ogp_spi.c index d1bb12f..6fb1a77 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -100,8 +100,6 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { static int ogp_spi_shutdown(void *data) { physunmap(ogp_spibar, 4096); - pci_cleanup(pacc); - return 0; } diff --git a/pcidev.c b/pcidev.c index 1a26e99..37bcc22 100644 --- a/pcidev.c +++ b/pcidev.c @@ -154,6 +154,14 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) return (uintptr_t)addr; } +static int pcidev_shutdown(void *data) +{ + if (pacc != NULL) + pci_cleanup(pacc); + pcidev_dev = NULL; + return 0; +} + uintptr_t pcidev_init(int bar, const struct dev_entry *devs) { struct pci_dev *dev; @@ -166,6 +174,8 @@ uintptr_t pcidev_init(int bar, const struct dev_entry *devs) pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ + if (register_shutdown(pcidev_shutdown, NULL)) + return 1; pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); @@ -244,6 +254,11 @@ struct undo_pci_write_data { int undo_pci_write(void *p) { struct undo_pci_write_data *data = p; + if (pacc == NULL) { + msg_perr("%s: Tried to undo PCI writes without a valid PCI context!\n" + "Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n", data->dev.bus, data->dev.dev, data->dev.func, data->reg); switch (data->type) { diff --git a/satamv.c b/satamv.c index c0c1ffa..46a0e2d 100644 --- a/satamv.c +++ b/satamv.c @@ -60,7 +60,6 @@ static const struct par_programmer par_programmer_satamv = { static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); - pci_cleanup(pacc); return 0; } @@ -96,7 +95,7 @@ int satamv_init(void) mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) - goto error_out; + return 1; if (register_shutdown(satamv_shutdown, NULL)) return 1; @@ -159,10 +158,6 @@ int satamv_init(void) register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); return 0; - -error_out: - pci_cleanup(pacc); - return 1; } /* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. diff --git a/satasii.c b/satasii.c index 7b94203..730c420 100644 --- a/satasii.c +++ b/satasii.c @@ -57,7 +57,6 @@ static const struct par_programmer par_programmer_satasii = { static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } -- Kind regards, Stefan Tauner [View Less]

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[PATCH 0/5] Improve PCI and physmapping 2.0
by Stefan Tauner 01 Jan '13

01 Jan '13

Now using uintptr_t to hopefully make freebsd happy and do things right*. Stefan Tauner (5): Let pcidev clean itself up. Add pci_init_common() to unify PCI init. Automatically unmap physmap()s. uintptr_t-ify physmap.c. Allow physmap_common() to round address ranges to page boundaries. atahpt.c | 10 ----- chipset_enable.c | 12 +++--- drkaiser.c | 15 ++----- gfxnvidia.c | 17 ++------ ichspi.c | 4 +- internal.c | 6 +-- it85spi.c … [View More]

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Some additions for the intel-mysteries file
by Steven Zakulec 01 Jan '13

01 Jan '13

Hi, I've tried to make some sense out of the ME documents, and after some study, I've put together a list of the ways mentioned in Intel sheets to disable/stop the ME, and what chipsets they apply to/don't apply to. I've then included some observations I've made. If you find this useful (and think it's more likely valid than not), reply, and I'll send a sign-off so it can be put in a patch. ME disabling methods (all from section 4.5 or section on FPT (Flash Programming Tool): Manufacturer mode … [View More]jumper (GPIO 33) (also Flash Descriptor Override) Works on: Montevina (Oct 2007 guide) (1), (3) Intel 3 series chipset (2) Ibex Peak (4), (7) Intel 6 series chipset (5), (6) Remove all memory from Bank 0 (1), (2), (3) >From (2): This causes the ME to boot up in an error state, which is saved on the flash device. Once the OS has booted, you can program the flash device. Works on: Montevina (ICH9M) (Oct 2007 guide) (1), (3) Intel 3 series chipset (2) Doesn't work on: Ibex Peak (4) Intel 6 series chipset (5), (6) or presumably anything after Ibex Peak. HMRFPO message Works on: Ibex Peak (4) Intel 6 series chipset (5), (6) Set ME disable bits (2) >From (2): Set ME disable bits in the strap sections of the descriptor region- see ICH EDS for more info Works on: Intel 3 series chipset (2) Security override strap? (2) Temporarily stop ME thru MEbx? (4), (5) (7) says this: Temporarily disable the Intel® ME through the MEBX. Power off or cold reset. - This option is only applicable to non-Intel ME Ignition firmware. (4), (5) says Stopping ME is not a requirement when writing to the fixed offset region. (6) says FPT will stop ME SPI accessing automatically if it try to write data into the ME region. Customers do not have to do extra step to stop ME if using FPT tool to update ME region. (5) does not mention this note. Section 8 (Update Parameter Tool) of (4),(5),(6) is interesting- the tool will work with ME manufacturing mode bit set, and a locked Descriptor region. References: (1) Montevina SW/FW OEM Bring up Guide, October 2007, Rev 0.4 (2) System Tools User Guide, July 2007, Rev 0.92 (Intel 3 series chipset ) (3) Intel Management Engine, System Tools User Guide, October 2007, Rev 0.60 (4) (Ibex Peak) System Tools User Guide for Intel® Management Engine Firmware 6.0 (Corporate), User Guide, June 2009, Revision 0.60 (5) System Tools for Intel® 6 Series Chipset Family Intel® Management Engine, Firmware 7.0 SKU’s, User Guide, May 2010, Revision: 0.81 (6) (Cougar Point) System Tools for Intel® 6 Series Chipset Family Intel® Management Engine, Firmware 7.0 SKU’s, User Guide, December 2010, Revision: 1.08 (7) Ibex Peak SPI Programming Guide, Application Note, January 2009, Revision 1.3 In theory, pre-Ibex Peak chipsets should be able to take advantage of the removing memory method, which would be fairly easy to do. The Update Parameters tool is interesting, especially if it works, but since it's a separate tool, it's not of real use. [View Less]

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[commit] r1640 - trunk
by repository service 01 Jan '13

01 Jan '13

Author: stefanct Date: Tue Jan 1 01:06:51 2013 New Revision: 1640 URL: http://flashrom.org/trac/flashrom/changeset/1640 Log: Add a bunch of new/tested stuff and various small changes 16. Tested Mainboards: OK: - Acer V75-M (used in IBM Aptiva 2170-G http://www.flashrom.org/pipermail/flashrom/2012-December/010300.html - ASRock 4CoreDual-VSTA with W39V040FB http://paste.flashrom.org/view.php?id=1446 - ASRock 775Dual-VSTA http://www.flashrom.org/pipermail/flashrom/2012-December/… [View More]

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