flashrom January 2013

flashrom@flashrom.org

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97 discussions

[PATCH 4/5] uintptr_t-ify physmap.c.
by Stefan Tauner 01 Jan '13

01 Jan '13

unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in physmap.c where applicable. This should be done in a lot of other places in flashrom too, but that's a huge pile of work and we better start it with a small step than never (which is the forseeable alternative ;) This patch also changes the display width of all address values in physmap.c to 16/8 hex characters depending on the architecture. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- physmap.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/physmap.c b/physmap.c index a9445d5..8b9fea7 100644 --- a/physmap.c +++ b/physmap.c @@ -20,6 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <inttypes.h> #include <unistd.h> #include <stdbool.h> #include <stdio.h> @@ -35,6 +36,8 @@ #include <errno.h> #endif +#define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) + #ifdef __DJGPP__ #include <dpmi.h> #include <sys/nearptr.h> @@ -43,7 +46,7 @@ static void *realmem_map; -static void *map_first_meg(unsigned long phys_addr, size_t len) +static void *map_first_meg(uintptr_t phys_addr, size_t len) { if (realmem_map) return realmem_map + phys_addr; @@ -62,7 +65,7 @@ static void *map_first_meg(unsigned long phys_addr, size_t len) return realmem_map + phys_addr; } -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { int ret; __dpmi_meminfo mi; @@ -110,7 +113,7 @@ void physunmap(void *virt_addr, size_t len) #define MEM_DEV "" -void *sys_physmap(unsigned long phys_addr, size_t len) +void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } @@ -134,7 +137,7 @@ void cleanup_cpu_msr(void) #define MEM_DEV "DirectHW" -static void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { /* The short form of ?: is a GNU extension. * FIXME: map_physical returns NULL both for errors and for success @@ -166,7 +169,7 @@ static int fd_mem = -1; static int fd_mem_cached = -1; /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ -static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) +static void *sys_physmap_rw_uncached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -186,7 +189,7 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* For reading DMI/coreboot/whatever tables. We should never write, and we * do not care about caching. */ -static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +static void *sys_physmap_ro_cached(uintptr_t phys_addr, size_t len) { void *virt_addr; @@ -232,14 +235,13 @@ static int physmap_shutdown(void *data) return 0; } -static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, +static void *physmap_common(const char *descr, uintptr_t phys_addr, size_t len, bool mayfail, bool readonly, bool autocleanup) { void *virt_addr; if (len == 0) { - msg_pspew("Not mapping %s, zero size at 0x%08lx.\n", - descr, phys_addr); + msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr); return ERROR_PTR; } @@ -261,8 +263,8 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, size_t l if (ERROR_PTR == virt_addr) { if (NULL == descr) descr = "memory"; - msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, - (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%0zx bytes at 0x%0*" PRIxPTR "\n", + descr, len, PRIxPTR_WIDTH, phys_addr); perror(MEM_DEV " mmap failed"); #ifdef __linux__ if (EINVAL == errno) { @@ -302,17 +304,17 @@ unmap_out: return ERROR_PTR; } -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +void *physmap(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, false, false, false); } -void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len) +void *physmap_autocleanup(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, false, false, true); } -void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, true, true, false); } -- Kind regards, Stefan Tauner

1 0

[PATCH 3/5] Automatically unmap physmap()s.
by Stefan Tauner 01 Jan '13

01 Jan '13

Similarly to the previous PCI self-clean up patch this one allows to get rid of a huge number of programmer shutdown functions and makes introducing bugs harder. It adds a new function physmap_autocleanup() that takes care of unmapping at shutdown. Callers are changed where it makes sense. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 12 +++++++----- drkaiser.c | 12 ++---------- gfxnvidia.c | 11 ++--------- ichspi.c | 4 +++- it85spi.c | 3 +++ mcp6x_spi.c | 15 +++++---------- nicintel.c | 22 +++------------------- nicintel_spi.c | 10 +++------- ogp_spi.c | 11 ++--------- physmap.c | 54 ++++++++++++++++++++++++++++++++++++++++++++---------- programmer.h | 1 + satamv.c | 11 +---------- satasii.c | 14 ++++---------- sb600spi.c | 6 ++++-- 14 files changed, 84 insertions(+), 102 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 0dc1d7e..0635268 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -480,7 +480,9 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ - rcrb = physmap("ICH RCRB", tmp, 0x4000); + rcrb = physmap_autocleanup("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return 1; /* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -551,7 +553,9 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, msg_pdbg("Root Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ - rcrb = physmap("ICH RCRB", tmp, 0x4000); + rcrb = physmap_autocleanup("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return 1; gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -703,10 +707,8 @@ static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) case 0x8410: /* VX900 */ mmio_base = pci_read_long(dev, 0xbc) << 8; mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); - if (mmio_base_physmapped == ERROR_PTR) { - physunmap(mmio_base_physmapped, SPI_CNTL_LEN); + if (mmio_base_physmapped == ERROR_PTR) return ERROR_FATAL; - } /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; diff --git a/drkaiser.c b/drkaiser.c index a6eca1c..062ec73 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -56,12 +56,6 @@ static const struct par_programmer par_programmer_drkaiser = { .chip_writen = fallback_chip_writen, }; -static int drkaiser_shutdown(void *data) -{ - physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); - return 0; -} - int drkaiser_init(void) { uint32_t addr; @@ -77,10 +71,8 @@ int drkaiser_init(void) PCI_MAGIC_DRKAISER_VALUE); /* Map 128kB flash memory window. */ - drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", - addr, DRKAISER_MEMMAP_SIZE); - - if (register_shutdown(drkaiser_shutdown, NULL)) + drkaiser_bar = physmap_autocleanup("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); + if (drkaiser_bar == ERROR_PTR) return 1; max_rom_decode.parallel = 128 * 1024; diff --git a/gfxnvidia.c b/gfxnvidia.c index a994d68..ec63cf6 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -77,12 +77,6 @@ static const struct par_programmer par_programmer_gfxnvidia = { .chip_writen = fallback_chip_writen, }; -static int gfxnvidia_shutdown(void *data) -{ - physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); - return 0; -} - int gfxnvidia_init(void) { uint32_t reg32; @@ -96,9 +90,8 @@ int gfxnvidia_init(void) io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); - nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); - - if (register_shutdown(gfxnvidia_shutdown, NULL)) + nvidia_bar = physmap_autocleanup("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); + if (nvidia_bar == ERROR_PTR) return 1; /* Allow access to flash interface (will disable screen). */ diff --git a/ichspi.c b/ichspi.c index fadfe62..4b52745 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1845,7 +1845,9 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) { int i; - ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + ich_spibar = physmap_autocleanup("VIA SPI MMIO registers", mmio_base, 0x70); + if (ich_spibar == ERROR_PTR) + return ERROR_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ diff --git a/it85spi.c b/it85spi.c index 0b074eb..b778436 100644 --- a/it85spi.c +++ b/it85spi.c @@ -262,6 +262,9 @@ static int it85xx_spi_common_init(struct superio s) * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); + if (base == ERROR_PTR) + return 1; + msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ diff --git a/mcp6x_spi.c b/mcp6x_spi.c index ac40557..0c519eb 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -135,25 +135,20 @@ int mcp6x_spi_init(int want_spi) /* Accessing a NULL pointer BAR is evil. Don't do it. */ if (!mcp6x_spibaraddr && want_spi) { - msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR " - "is invalid.\n"); + msg_perr("Error: Chipset is strapped for SPI, but MCP SPI BAR is invalid.\n"); return 1; } else if (!mcp6x_spibaraddr && !want_spi) { msg_pdbg("MCP SPI is not used.\n"); return 0; } else if (mcp6x_spibaraddr && !want_spi) { - msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently" - " doesn't have SPI enabled.\n"); + msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled.\n"); /* FIXME: Should we enable SPI anyway? */ return 0; } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); - -#if 0 - /* FIXME: Run the physunmap in a shutdown function. */ - physunmap(mcp6x_spibar, 0x544); -#endif + mcp6x_spibar = physmap_autocleanup("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); + if (mcp6x_spibar == ERROR_PTR) + return 1; status = mmio_readw(mcp6x_spibar + 0x530); msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", diff --git a/nicintel.c b/nicintel.c index 8481915..5463af2 100644 --- a/nicintel.c +++ b/nicintel.c @@ -59,13 +59,6 @@ static const struct par_programmer par_programmer_nicintel = { .chip_writen = fallback_chip_writen, }; -static int nicintel_shutdown(void *data) -{ - physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); - physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); - return 0; -} - int nicintel_init(void) { uintptr_t addr; @@ -81,19 +74,15 @@ int nicintel_init(void) */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); - nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); + nicintel_bar = physmap_autocleanup("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) - goto error_out_unmap; + return 1; /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */ addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0); /* FIXME: This is not an aligned mapping. Use 4k? */ - nicintel_control_bar = physmap("Intel NIC control/status reg", - addr, NICINTEL_CONTROL_MEMMAP_SIZE); + nicintel_control_bar = physmap_autocleanup("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); if (nicintel_control_bar == ERROR_PTR) - goto error_out; - - if (register_shutdown(nicintel_shutdown, NULL)) return 1; /* FIXME: This register is pretty undocumented in all publicly available @@ -111,11 +100,6 @@ int nicintel_init(void) register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); return 0; - -error_out_unmap: - physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); -error_out: - return 1; } static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, diff --git a/nicintel_spi.c b/nicintel_spi.c index f61c2b1..8630f3f 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -151,16 +151,12 @@ static int nicintel_spi_shutdown(void *data) { uint32_t tmp; - /* Disable writes manually. See the comment about EECD in - * nicintel_spi_init() for details. - */ + /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; pci_mmio_writel(tmp, nicintel_spibar + EECD); - physunmap(nicintel_spibar, MEMMAP_SIZE); - return 0; } @@ -174,8 +170,8 @@ int nicintel_spi_init(void) /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); - nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", - io_base_addr, MEMMAP_SIZE); + nicintel_spibar = physmap_autocleanup("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be diff --git a/ogp_spi.c b/ogp_spi.c index 6fb1a77..d66b2ef 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -97,12 +97,6 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { .half_period = 0, }; -static int ogp_spi_shutdown(void *data) -{ - physunmap(ogp_spibar, 4096); - return 0; -} - int ogp_spi_init(void) { char *type; @@ -133,9 +127,8 @@ int ogp_spi_init(void) io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); - ogp_spibar = physmap("OGP registers", io_base_addr, 4096); - - if (register_shutdown(ogp_spi_shutdown, NULL)) + ogp_spibar = physmap_autocleanup("OGP registers", io_base_addr, 4096); + if (ogp_spibar == ERROR_PTR) return 1; if (bitbang_spi_init(&bitbang_spi_master_ogp)) diff --git a/physmap.c b/physmap.c index 5aa9874..a9445d5 100644 --- a/physmap.c +++ b/physmap.c @@ -21,6 +21,7 @@ */ #include <unistd.h> +#include <stdbool.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -214,13 +215,25 @@ void physunmap(void *virt_addr, size_t len) } #endif -#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 -#define PHYSMAP_RW 0 -#define PHYSMAP_RO 1 +struct physmap_stutdown_data { + void *addr; + size_t len; +}; -static void *physmap_common(const char *descr, unsigned long phys_addr, - size_t len, int mayfail, int readonly) +static int physmap_shutdown(void *data) +{ + if (data == NULL) { + msg_perr("%s: tried to shutdown without valid data!\n", __func__); + return 1; + } + struct physmap_stutdown_data *d = data; + physunmap(d->addr, d->len); + free(data); + return 0; +} + +static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, bool mayfail, + bool readonly, bool autocleanup) { void *virt_addr; @@ -268,19 +281,40 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, exit(3); } + if (autocleanup) { + struct physmap_stutdown_data *d = malloc(sizeof(struct physmap_stutdown_data)); + if (d == NULL) { + msg_perr("%s: Out of memory!\n", __func__); + goto unmap_out; + } + + d->addr = virt_addr; + d->len = len; + if (register_shutdown(physmap_shutdown, d) != 0) { + msg_perr("%s: Could not register shutdown function!\n", __func__); + goto unmap_out; + } + } + return virt_addr; +unmap_out: + physunmap(virt_addr, len); + return ERROR_PTR; } void *physmap(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, - PHYSMAP_RW); + return physmap_common(descr, phys_addr, len, false, false, false); +} + +void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, false, false, true); } void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, - PHYSMAP_RO); + return physmap_common(descr, phys_addr, len, true, true, false); } #if defined(__i386__) || defined(__x86_64__) diff --git a/programmer.h b/programmer.h index 4302809..77b78bd 100644 --- a/programmer.h +++ b/programmer.h @@ -272,6 +272,7 @@ int processor_flash_enable(void); /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_autocleanup(const char *descr, unsigned long phys_addr, size_t len); void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); #if CONFIG_INTERNAL == 1 diff --git a/satamv.c b/satamv.c index 46a0e2d..726dd5a 100644 --- a/satamv.c +++ b/satamv.c @@ -57,12 +57,6 @@ static const struct par_programmer par_programmer_satamv = { .chip_writen = fallback_chip_writen, }; -static int satamv_shutdown(void *data) -{ - physunmap(mv_bar, 0x20000); - return 0; -} - /* * Random notes: * FCE# Flash Chip Enable @@ -93,13 +87,10 @@ int satamv_init(void) */ addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); - mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + mv_bar = physmap_autocleanup("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) return 1; - if (register_shutdown(satamv_shutdown, NULL)) - return 1; - tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); msg_pspew("Flash Parameters:\n"); msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); diff --git a/satasii.c b/satasii.c index 730c420..36f4cd1 100644 --- a/satasii.c +++ b/satasii.c @@ -54,12 +54,6 @@ static const struct par_programmer par_programmer_satasii = { .chip_writen = fallback_chip_writen, }; -static int satasii_shutdown(void *data) -{ - physunmap(sii_bar, SATASII_MEMMAP_SIZE); - return 0; -} - static uint32_t satasii_wait_done(void) { uint32_t ctrl_reg; @@ -94,15 +88,15 @@ int satasii_init(void) reg_offset = 0x50; } - sii_bar = physmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE) + reg_offset; + sii_bar = physmap_autocleanup("SATA SiI registers", addr, SATASII_MEMMAP_SIZE); + if (sii_bar == ERROR_PTR) + return 1; + sii_bar += reg_offset; /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - if (register_shutdown(satasii_shutdown, NULL)) - return 1; - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); return 0; diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..7888bb9 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -224,8 +224,10 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); + sb600_spibar = physmap_autocleanup("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (sb600_spibar == ERROR_PTR) + return 1; + /* The low bits of the SPI base address are used as offset into * the mapped page. */ -- Kind regards, Stefan Tauner

1 0

[PATCH 2/5] Add pci_init_common() to unify PCI init.
by Stefan Tauner 01 Jan '13

01 Jan '13

Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- internal.c | 6 ++---- pcidev.c | 15 +++++++++++---- programmer.h | 1 + 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/internal.c b/internal.c index eda4d59..9b34715 100644 --- a/internal.c +++ b/internal.c @@ -245,10 +245,8 @@ int internal_init(void) internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ - pacc = pci_alloc(); /* Get the pci_access structure */ - /* Set all options you want -- here we stick with the defaults */ - pci_init(pacc); /* Initialize the PCI library */ - pci_scan_bus(pacc); /* We want to get the list of devices */ + if(pci_init_common() != 0) + return 1; if (processor_flash_enable()) { msg_perr("Processor detection/init failed.\n" diff --git a/pcidev.c b/pcidev.c index 37bcc22..a5a7088 100644 --- a/pcidev.c +++ b/pcidev.c @@ -162,6 +162,16 @@ static int pcidev_shutdown(void *data) return 0; } +int pci_init_common(void) +{ + pacc = pci_alloc(); /* Get the pci_access structure */ + pci_init(pacc); /* Initialize the PCI library */ + if (register_shutdown(pcidev_shutdown, NULL)) + return 1; + pci_scan_bus(pacc); /* We want to get the list of devices */ + return 0; +} + uintptr_t pcidev_init(int bar, const struct dev_entry *devs) { struct pci_dev *dev; @@ -172,11 +182,8 @@ uintptr_t pcidev_init(int bar, const struct dev_entry *devs) int i; uintptr_t addr = 0, curaddr = 0; - pacc = pci_alloc(); /* Get the pci_access structure */ - pci_init(pacc); /* Initialize the PCI library */ - if (register_shutdown(pcidev_shutdown, NULL)) + if(pci_init_common() != 0) return 1; - pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); /* Filter by bb:dd.f (if supplied by the user). */ diff --git a/programmer.h b/programmer.h index 8de42bc..4302809 100644 --- a/programmer.h +++ b/programmer.h @@ -238,6 +238,7 @@ void internal_delay(int usecs); extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_dev *pcidev_dev; +int pci_init_common(void); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); uintptr_t pcidev_init(int bar, const struct dev_entry *devs); /* rpci_write_* are reversible writes. The original PCI config space register -- Kind regards, Stefan Tauner

1 0

[PATCH 1/5] Let pcidev clean itself up.
by Stefan Tauner 01 Jan '13

01 Jan '13

We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- atahpt.c | 10 ---------- drkaiser.c | 3 +-- gfxnvidia.c | 6 +----- nic3com.c | 2 +- nicintel.c | 5 +---- nicintel_spi.c | 2 +- nicrealtek.c | 7 +++++-- ogp_spi.c | 2 -- pcidev.c | 15 +++++++++++++++ satamv.c | 7 +------ satasii.c | 1 - 11 files changed, 26 insertions(+), 34 deletions(-) diff --git a/atahpt.c b/atahpt.c index 461191d..d19cb75 100644 --- a/atahpt.c +++ b/atahpt.c @@ -56,13 +56,6 @@ static const struct par_programmer par_programmer_atahpt = { .chip_writen = fallback_chip_writen, }; -static int atahpt_shutdown(void *data) -{ - /* Flash access is disabled automatically by PCI restore. */ - pci_cleanup(pacc); - return 0; -} - int atahpt_init(void) { uint32_t reg32; @@ -72,9 +65,6 @@ int atahpt_init(void) io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); - if (register_shutdown(atahpt_shutdown, NULL)) - return 1; - /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); diff --git a/drkaiser.c b/drkaiser.c index e461061..a6eca1c 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -59,8 +59,6 @@ static const struct par_programmer par_programmer_drkaiser = { static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); - /* Flash write is disabled automatically by PCI restore. */ - pci_cleanup(pacc); return 0; } @@ -71,6 +69,7 @@ int drkaiser_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); /* Write magic register to enable flash write. */ diff --git a/gfxnvidia.c b/gfxnvidia.c index 624fd7c..a994d68 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -80,10 +80,6 @@ static const struct par_programmer par_programmer_gfxnvidia = { static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); - /* Flash interface access is disabled (and screen enabled) automatically - * by PCI restore. - */ - pci_cleanup(pacc); return 0; } @@ -94,6 +90,7 @@ int gfxnvidia_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; @@ -101,7 +98,6 @@ int gfxnvidia_init(void) nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); - /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) return 1; diff --git a/nic3com.c b/nic3com.c index 05eada6..4ec6193 100644 --- a/nic3com.c +++ b/nic3com.c @@ -81,7 +81,6 @@ static int nic3com_shutdown(void *data) OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); } - pci_cleanup(pacc); return 0; } @@ -90,6 +89,7 @@ int nic3com_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); id = pcidev_dev->device_id; diff --git a/nicintel.c b/nicintel.c index d210d78..8481915 100644 --- a/nicintel.c +++ b/nicintel.c @@ -63,7 +63,6 @@ static int nicintel_shutdown(void *data) { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -77,8 +76,7 @@ int nicintel_init(void) if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. + /* No need to check for errors, pcidev_init() will not return in case of errors. * FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); @@ -117,7 +115,6 @@ int nicintel_init(void) error_out_unmap: physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); error_out: - pci_cleanup(pacc); return 1; } diff --git a/nicintel_spi.c b/nicintel_spi.c index 325e61c..f61c2b1 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -160,7 +160,6 @@ static int nicintel_spi_shutdown(void *data) pci_mmio_writel(tmp, nicintel_spibar + EECD); physunmap(nicintel_spibar, MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -172,6 +171,7 @@ int nicintel_spi_init(void) if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", diff --git a/nicrealtek.c b/nicrealtek.c index 3c3b261..0929e5d 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -51,22 +51,25 @@ static const struct par_programmer par_programmer_nicrealtek = { .chip_writen = fallback_chip_writen, }; +#if 0 static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ - pci_cleanup(pacc); return 0; } +#endif int nicrealtek_init(void) { if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - +#if 0 if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; +#endif /* Beware, this ignores the vendor ID! */ switch (pcidev_dev->device_id) { diff --git a/ogp_spi.c b/ogp_spi.c index d1bb12f..6fb1a77 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -100,8 +100,6 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { static int ogp_spi_shutdown(void *data) { physunmap(ogp_spibar, 4096); - pci_cleanup(pacc); - return 0; } diff --git a/pcidev.c b/pcidev.c index 1a26e99..37bcc22 100644 --- a/pcidev.c +++ b/pcidev.c @@ -154,6 +154,14 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) return (uintptr_t)addr; } +static int pcidev_shutdown(void *data) +{ + if (pacc != NULL) + pci_cleanup(pacc); + pcidev_dev = NULL; + return 0; +} + uintptr_t pcidev_init(int bar, const struct dev_entry *devs) { struct pci_dev *dev; @@ -166,6 +174,8 @@ uintptr_t pcidev_init(int bar, const struct dev_entry *devs) pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ + if (register_shutdown(pcidev_shutdown, NULL)) + return 1; pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); @@ -244,6 +254,11 @@ struct undo_pci_write_data { int undo_pci_write(void *p) { struct undo_pci_write_data *data = p; + if (pacc == NULL) { + msg_perr("%s: Tried to undo PCI writes without a valid PCI context!\n" + "Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n", data->dev.bus, data->dev.dev, data->dev.func, data->reg); switch (data->type) { diff --git a/satamv.c b/satamv.c index c0c1ffa..46a0e2d 100644 --- a/satamv.c +++ b/satamv.c @@ -60,7 +60,6 @@ static const struct par_programmer par_programmer_satamv = { static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); - pci_cleanup(pacc); return 0; } @@ -96,7 +95,7 @@ int satamv_init(void) mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) - goto error_out; + return 1; if (register_shutdown(satamv_shutdown, NULL)) return 1; @@ -159,10 +158,6 @@ int satamv_init(void) register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); return 0; - -error_out: - pci_cleanup(pacc); - return 1; } /* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. diff --git a/satasii.c b/satasii.c index 7b94203..730c420 100644 --- a/satasii.c +++ b/satasii.c @@ -57,7 +57,6 @@ static const struct par_programmer par_programmer_satasii = { static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } -- Kind regards, Stefan Tauner

1 0

[PATCH 0/5] Improve PCI and physmapping 2.0
by Stefan Tauner 01 Jan '13

01 Jan '13

1 0

Some additions for the intel-mysteries file
by Steven Zakulec 01 Jan '13

01 Jan '13

Hi, I've tried to make some sense out of the ME documents, and after some study, I've put together a list of the ways mentioned in Intel sheets to disable/stop the ME, and what chipsets they apply to/don't apply to. I've then included some observations I've made. If you find this useful (and think it's more likely valid than not), reply, and I'll send a sign-off so it can be put in a patch. ME disabling methods (all from section 4.5 or section on FPT (Flash Programming Tool): Manufacturer mode jumper (GPIO 33) (also Flash Descriptor Override) Works on: Montevina (Oct 2007 guide) (1), (3) Intel 3 series chipset (2) Ibex Peak (4), (7) Intel 6 series chipset (5), (6) Remove all memory from Bank 0 (1), (2), (3) >From (2): This causes the ME to boot up in an error state, which is saved on the flash device. Once the OS has booted, you can program the flash device. Works on: Montevina (ICH9M) (Oct 2007 guide) (1), (3) Intel 3 series chipset (2) Doesn't work on: Ibex Peak (4) Intel 6 series chipset (5), (6) or presumably anything after Ibex Peak. HMRFPO message Works on: Ibex Peak (4) Intel 6 series chipset (5), (6) Set ME disable bits (2) >From (2): Set ME disable bits in the strap sections of the descriptor region- see ICH EDS for more info Works on: Intel 3 series chipset (2) Security override strap? (2) Temporarily stop ME thru MEbx? (4), (5) (7) says this: Temporarily disable the Intel® ME through the MEBX. Power off or cold reset. - This option is only applicable to non-Intel ME Ignition firmware. (4), (5) says Stopping ME is not a requirement when writing to the fixed offset region. (6) says FPT will stop ME SPI accessing automatically if it try to write data into the ME region. Customers do not have to do extra step to stop ME if using FPT tool to update ME region. (5) does not mention this note. Section 8 (Update Parameter Tool) of (4),(5),(6) is interesting- the tool will work with ME manufacturing mode bit set, and a locked Descriptor region. References: (1) Montevina SW/FW OEM Bring up Guide, October 2007, Rev 0.4 (2) System Tools User Guide, July 2007, Rev 0.92 (Intel 3 series chipset ) (3) Intel Management Engine, System Tools User Guide, October 2007, Rev 0.60 (4) (Ibex Peak) System Tools User Guide for Intel® Management Engine Firmware 6.0 (Corporate), User Guide, June 2009, Revision 0.60 (5) System Tools for Intel® 6 Series Chipset Family Intel® Management Engine, Firmware 7.0 SKU’s, User Guide, May 2010, Revision: 0.81 (6) (Cougar Point) System Tools for Intel® 6 Series Chipset Family Intel® Management Engine, Firmware 7.0 SKU’s, User Guide, December 2010, Revision: 1.08 (7) Ibex Peak SPI Programming Guide, Application Note, January 2009, Revision 1.3 In theory, pre-Ibex Peak chipsets should be able to take advantage of the removing memory method, which would be fairly easy to do. The Update Parameters tool is interesting, especially if it works, but since it's a separate tool, it's not of real use.

1 0

[commit] r1640 - trunk
by repository service 01 Jan '13

01 Jan '13

Author: stefanct Date: Tue Jan 1 01:06:51 2013 New Revision: 1640 URL: http://flashrom.org/trac/flashrom/changeset/1640 Log: Add a bunch of new/tested stuff and various small changes 16. Tested Mainboards: OK: - Acer V75-M (used in IBM Aptiva 2170-G http://www.flashrom.org/pipermail/flashrom/2012-December/010300.html - ASRock 4CoreDual-VSTA with W39V040FB http://paste.flashrom.org/view.php?id=1446 - ASRock 775Dual-VSTA http://www.flashrom.org/pipermail/flashrom/2012-December/010294.html - ASRock E350M1/USB3 http://paste.flashrom.org/view.php?id=1465 - ASUS P5B-VM http://www.flashrom.org/pipermail/flashrom/2012-December/010351.html - ASUS SABERTOOTH 990FX R2.0 http://www.flashrom.org/pipermail/flashrom/2012-December/010210.html - Elitegroup A928 (including a laptop whitelist board enable) http://www.flashrom.org/pipermail/flashrom/2012-November/010119.html - EVGA 122-CK-NF68 Reported by Stephanie Daugherty on IRC http://paste.flashrom.org/view.php?id=1431 - GIGABYTE GA-A75M-UD2H Reported by Soul_keeper on IRC http://paste.flashrom.org/view.php?id=1490 - Intel D945GCNL Add board enable to override laptop detection too. http://www.flashrom.org/pipermail/flashrom/2012-December/010276.html - MSI G33M (MS-7357) http://www.flashrom.org/pipermail/flashrom/2012-October/010056.html - Shuttle FB61 http://www.flashrom.org/pipermail/flashrom/2012-November/010105.html - Tyan S4882 (Thunder K8QS Pro) Reported on IRC NOT OK: Alienware Aurora-R2 http://www.flashrom.org/pipermail/flashrom/2012-December/010225.html Biostar H61MU3 http://www.flashrom.org/pipermail/flashrom/2012-November/010144.html Dell OptiPlex 7010 http://paste.flashrom.org/view.php?id=1481 Intel DH67CL http://www.flashrom.org/pipermail/flashrom/2012-November/010112.html Supermicro X9DRT-HF+ http://www.flashrom.org/pipermail/flashrom/2012-November/010155.html Supermicro X9DRW http://www.flashrom.org/pipermail/flashrom/2012-November/010150.html Tested flash chips: - Atmel AT25FS010 to PREW (+PREW) http://paste.flashrom.org/view.php?id=1484 - Eon EN25F64 to PREW (+EW) http://www.flashrom.org/pipermail/flashrom/2012-December/010210.html - Spansion S25FL032A/P to PREW (+EW) http://paste.flashrom.org/view.php?id=1510 - ST M29F002T/NT to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-December/010300.html - Winbond W25X10 to PREW (+PREW) http://paste.flashrom.org/view.php?id=1486 Tested chipsets: - NVIDIA MCP78S http://www.flashrom.org/pipermail/flashrom/2012-November/010176.html - SiS 650 http://www.flashrom.org/pipermail/flashrom/2012-November/010119.html Miscellaneous: - Typo in GA-X58A-UDR3 (correct is GA-X58A-UD3R). - Force 2-digit hex numbers in prints were it makes sense. - Share code between enable_flash_sis530() and enable_flash_sis540(). - Some SST 25 series chips support both WRSR enable commands... - S25FL032A and S25FL064A share the IDs with their P versions, so rename them. - Fix a few memleaks in serprog. - Dediprog uses UINT_MAX so include limits.h (fixes the Windows build of dediprog) - Add (another) hint regarding the mandatory -p parameter to the manpage to make Debian bug #690478 happy. http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=690478 - Fix whitespace issues. - On shutdown, reset count of registered programmers (by Nico Huber) - Fix atahpt.c shutdown. The order of pcidev_init, register_shutdown and rpci_write_* is important! Thanks to Roy for reporting the problem and testing the fix. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Makefile trunk/atahpt.c trunk/board_enable.c trunk/chipset_enable.c trunk/dediprog.c trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8 trunk/flashrom.c trunk/print.c trunk/serprog.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/Makefile Tue Jan 1 01:06:51 2013 (r1640) @@ -581,7 +581,7 @@ else ifeq ($(TARGET_OS), Darwin) # DirectHW framework can be found in the DirectHW library. -PCILIBS += -framework IOKit -framework DirectHW +PCILIBS += -framework IOKit -framework DirectHW else endif endif Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/atahpt.c Tue Jan 1 01:06:51 2013 (r1640) @@ -72,14 +72,14 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); + if (register_shutdown(atahpt_shutdown, NULL)) + return 1; + /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - if (register_shutdown(atahpt_shutdown, NULL)) - return 1; - register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); return 0; Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/board_enable.c Tue Jan 1 01:06:51 2013 (r1640) @@ -2378,6 +2378,7 @@ {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e}, + {0x1039, 0x6325, 0x1019, 0x0f05, 0x1039, 0x0016, 0, 0, NULL, NULL, NULL, P2, "Elitegroup", "A928", 0, OK, p2_whitelist_laptop}, {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, @@ -2406,6 +2407,7 @@ {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, + {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/chipset_enable.c Tue Jan 1 01:06:51 2013 (r1640) @@ -95,19 +95,20 @@ static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) { + #define SIS_MAPREG 0x40 uint8_t new, newer; /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ - new = pci_read_byte(dev, 0x40); + new = pci_read_byte(dev, SIS_MAPREG); new &= (~0x04); /* No idea why we clear bit 2. */ new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ - rpci_write_byte(dev, 0x40, new); - newer = pci_read_byte(dev, 0x40); - if (newer != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x40, new, name); - msg_pinfo("Stuck at 0x%x\n", newer); + rpci_write_byte(dev, SIS_MAPREG, new); + newer = pci_read_byte(dev, SIS_MAPREG); + if (newer != new) { /* FIXME: share this with other code? */ + msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", + SIS_MAPREG, new, name); + msg_pinfo("Stuck at 0x%02x.\n", newer); return -1; } return 0; @@ -176,8 +177,9 @@ return ret; } -static int enable_flash_sis530(struct pci_dev *dev, const char *name) +static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask) { + #define SIS_REG 0x45 uint8_t new, newer; int ret = 0; struct pci_dev *sbdev; @@ -188,46 +190,28 @@ ret = enable_flash_sis_mapping(sbdev, name); - new = pci_read_byte(sbdev, 0x45); - new &= (~0x20); - new |= 0x4; - rpci_write_byte(sbdev, 0x45, new); - newer = pci_read_byte(sbdev, 0x45); - if (newer != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x45, new, name); - msg_pinfo("Stuck at 0x%x\n", newer); + new = pci_read_byte(sbdev, SIS_REG); + new &= (~dis_mask); + new |= en_mask; + rpci_write_byte(sbdev, SIS_REG, new); + newer = pci_read_byte(sbdev, SIS_REG); + if (newer != new) { /* FIXME: share this with other code? */ + msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name); + msg_pinfo("Stuck at 0x%02x\n", newer); ret = -1; } return ret; } -static int enable_flash_sis540(struct pci_dev *dev, const char *name) +static int enable_flash_sis530(struct pci_dev *dev, const char *name) { - uint8_t new, newer; - int ret = 0; - struct pci_dev *sbdev; - - sbdev = find_southbridge(dev->vendor_id, name); - if (!sbdev) - return -1; - - ret = enable_flash_sis_mapping(sbdev, name); - - new = pci_read_byte(sbdev, 0x45); - new &= (~0x80); - new |= 0x40; - rpci_write_byte(sbdev, 0x45, new); - newer = pci_read_byte(sbdev, 0x45); - if (newer != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x45, new, name); - msg_pinfo("Stuck at 0x%x\n", newer); - ret = -1; - } + return enable_flash_sis5x0(dev, name, 0x20, 0x04); +} - return ret; +static int enable_flash_sis540(struct pci_dev *dev, const char *name) +{ + return enable_flash_sis5x0(dev, name, 0x80, 0x40); } /* Datasheet: @@ -268,9 +252,8 @@ rpci_write_word(dev, xbcs, new); - if (pci_read_word(dev, xbcs) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", xbcs, new, name); + if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */ + msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name); return -1; } @@ -678,8 +661,7 @@ rpci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", - name); + msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } @@ -851,15 +833,15 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name) { + #define SC_REG 0x52 uint8_t new; - rpci_write_byte(dev, 0x52, 0xee); + rpci_write_byte(dev, SC_REG, 0xee); - new = pci_read_byte(dev, 0x52); + new = pci_read_byte(dev, SC_REG); - if (new != 0xee) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x52, new, name); + if (new != 0xee) { /* FIXME: share this with other code? */ + msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name); return -1; } @@ -869,29 +851,31 @@ /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { + #define AMD_MAPREG 0x43 + #define AMD_ENREG 0x40 uint8_t old, new; /* Enable decoding at 0xffb00000 to 0xffffffff. */ - old = pci_read_byte(dev, 0x43); + old = pci_read_byte(dev, AMD_MAPREG); new = old | 0xC0; if (new != old) { - rpci_write_byte(dev, 0x43, new); - if (pci_read_byte(dev, 0x43) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x43, new, name); + rpci_write_byte(dev, AMD_MAPREG, new); + if (pci_read_byte(dev, AMD_MAPREG) != new) { + msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", + AMD_MAPREG, new, name); } } /* Enable 'ROM write' bit. */ - old = pci_read_byte(dev, 0x40); + old = pci_read_byte(dev, AMD_ENREG); new = old | 0x01; if (new == old) return 0; - rpci_write_byte(dev, 0x40, new); + rpci_write_byte(dev, AMD_ENREG, new); - if (pci_read_byte(dev, 0x40) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x40, new, name); + if (pci_read_byte(dev, AMD_ENREG) != new) { + msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", + AMD_ENREG, new, name); return -1; } @@ -1055,8 +1039,8 @@ new = old | 0xC0; if (new != old) { rpci_write_byte(dev, reg, new); - if (pci_read_byte(dev, reg) != new) { - msg_pinfo("Setting register 0x%02x to 0x%x on %s failed.\n", reg, new, name); + if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */ + msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name); err++; } } @@ -1298,7 +1282,7 @@ {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, - {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, @@ -1355,7 +1339,7 @@ {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, - {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, + {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/dediprog.c Tue Jan 1 01:06:51 2013 (r1640) @@ -19,6 +19,7 @@ #include <stdio.h> #include <string.h> +#include <limits.h> #include <errno.h> #include <usb.h> #include "flash.h" Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/flashchips.c Tue Jan 1 01:06:51 2013 (r1640) @@ -1864,7 +1864,7 @@ .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3598,7 +3598,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6832,14 +6832,14 @@ { .vendor = "Spansion", - .name = "S25FL032A", + .name = "S25FL032A/P", .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, .model_id = SPANSION_S25FL032A, .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6861,7 +6861,7 @@ { .vendor = "Spansion", - .name = "S25FL064A", + .name = "S25FL064A/P", .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, .model_id = SPANSION_S25FL064A, @@ -6922,13 +6922,13 @@ { .vendor = "SST", - .name = "SST25LF080A", + .name = "SST25LF080(A)", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF080_REMS, .total_size = 1024, .page_size = 256, - .feature_bits = FEATURE_WRSR_EWSR, + .feature_bits = FEATURE_WRSR_EITHER, .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, @@ -6992,7 +6992,7 @@ .model_id = SST_SST25VF016B, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_EWSR, + .feature_bits = FEATURE_WRSR_EITHER, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -8659,7 +8659,7 @@ .total_size = 256, .page_size = 64 * 1024, .feature_bits = FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = @@ -9600,7 +9600,7 @@ .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/flashchips.h Tue Jan 1 01:06:51 2013 (r1640) @@ -483,8 +483,8 @@ #define SPANSION_S25FL004A 0x0212 #define SPANSION_S25FL008A 0x0213 #define SPANSION_S25FL016A 0x0214 -#define SPANSION_S25FL032A 0x0215 -#define SPANSION_S25FL064A 0x0216 +#define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ +#define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ /* * SST25 chips are SPI, first byte of device ID is memory type, second Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/flashrom.8 Tue Jan 1 01:06:51 2013 (r1640) @@ -34,7 +34,9 @@ in probe-only mode and check the output. Also you are advised to make a backup of your current ROM contents with .B \-r -before you try to write a new image. +before you try to write a new image. All operations involving any chip access (probe/read/write/...) require the +.B -p/--programmer +option to be used (please see below). .TP .B "\-r, \-\-read <file>" Read flash ROM contents and save them into the given @@ -128,7 +130,7 @@ .sp .B " flashrom \-p prog \-\-layout rom.layout \-\-image normal \-w some.rom" .sp -To update only the images named +To update only the images named .BR "normal " "and " "fallback" ", run:" .sp .B " flashrom \-p prog \-l rom.layout \-i normal -i fallback \-w some.rom" @@ -694,11 +696,11 @@ .BR "pony_spi " programmer The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is specified using the mandatory -.B dev +.B dev parameter. The adapter type is selectable between SI-Prog (used for SPI devices with PonyProg 2000) or a custom made serial bitbanging programmer named "serbang". The optional -.B type +.B type parameter accepts the values "si_prog" (default) or "serbang". .sp Information about the SI-Prog adapter can be found at @@ -724,7 +726,7 @@ .B cprom or .B s3 -for the configuration ROM and +for the configuration ROM and .B bprom or .B bios @@ -733,7 +735,7 @@ you want to use with the .B pci= parameter as explained in the -.B nic3com et al.\& +.B nic3com et al.\& section above. .sp More information about the hardware is available at Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/flashrom.c Tue Jan 1 01:06:51 2013 (r1640) @@ -397,7 +397,10 @@ int i = --shutdown_fn_count; ret |= shutdown_fn[i].func(shutdown_fn[i].data); } + programmer_param = NULL; + registered_programmer_count = 0; + return ret; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/print.c Tue Jan 1 01:06:51 2013 (r1640) @@ -517,15 +517,19 @@ B("abit", "NF7-S", OK, NULL, NULL), B("abit", "VA6", OK, NULL, NULL), B("abit", "VT6X4", OK, NULL, NULL), + B("Acer", "V75-M", OK, NULL, "This is an OEM board used by IBM in e.g. Aptiva 2170-G"), B("Acorp", "6A815EPD", OK, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL), B("Advantech", "PCM-5820", OK, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", OK, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", OK, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ + B("Alienware", "Aurora-R2", BAD, NULL, "Mainboard model is 0RV30W. Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("AOpen", "i945GMx-VFX", OK, NULL, "This is (also?) an OEM board from FSC (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), B("AOpen", "vKM400Am-S", OK, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", OK, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", OK, "http://wiki.thincan.org/DBE62", NULL), B("ASI", "MB-5BLMP", OK, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), + B("ASRock", "4CoreDual-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=4CoreDual-VSTA", "W39V040FB"), + B("ASRock", "775Dual-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=775Dual-VSTA", NULL), B("ASRock", "775i65G", OK, "http://www.asrock.com/mb/overview.asp?Model=775i65G", NULL), B("ASRock", "880G Pro3", OK, "http://www.asrock.com/mb/overview.asp?Model=880G%20Pro3", NULL), B("ASRock", "890GX Extreme3", OK, "http://www.asrock.com/mb/overview.asp?Model=890GX%20Extreme3", NULL), @@ -535,6 +539,7 @@ B("ASRock", "A780FullHD", OK, "http://www.asrock.com/mb/overview.asp?Model=A780FullHD", "While flashrom is working correctly, there might be problems with the firmware images themselves. Please see http://www.flashrom.org/pipermail/flashrom/2012-July/009600.html for details."), B("ASRock", "ALiveNF6G-DVI", OK, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), B("ASRock", "AM2NF6G-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), + B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", NULL), B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), @@ -636,6 +641,7 @@ B("ASUS", "P5A", OK, NULL, NULL), B("ASUS", "P5B", OK, NULL, NULL), B("ASUS", "P5B-Deluxe", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5B_Deluxe/", NULL), + B("ASUS", "P5B-VM", OK, NULL, NULL), B("ASUS", "P5BV-M", BAD, NULL, "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5BV-R", OK, "http://www.asus.com/Server_Workstation/Servers/RS120E5PA2/", "Used in RS120-E5/PA2 servers."), B("ASUS", "P5GC-MX/1333", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5GCMX1333/", NULL), @@ -684,6 +690,7 @@ B("ASUS", "P8Z68-V PRO", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO/GEN3", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V_PROGEN3/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), B("ASUS", "SABERTOOTH 990FX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX/", NULL), + B("ASUS", "SABERTOOTH 990FX R2.0", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX_R20/", NULL), B("ASUS", "CUSL2-C", OK, NULL, "The image provided by ASUS is only 256 kB big and has to be written to the upper 256 kB of the 512 kB chip."), B("ASUS", "TUSL2-C", NT, "http://support.asus.com/download.aspx?SLanguage=en&p=1&s=4&m=TUSL2-C&os=&ha…", "Untested board enable."), B("ASUS", "Z8NA-D6C", OK, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8NAD6C/", NULL), @@ -691,6 +698,7 @@ B("Bachmann", "OT200", OK, "http://www.bachmann.info/produkte/bedien-und-beobachtungsgeraete/operator-t…", NULL), B("BCOM", "WinNET100", OK, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), B("Bifferos", "Bifferboard", OK, "http://bifferos.co.uk/", NULL), + B("Biostar", "H61MGC", BAD, NULL, "Probing works (Eon EN25Q32(A/B), 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Biostar", "H61MU3", BAD, NULL, "Probing works (Eon EN25Q32(A/B), 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Biostar", "M6TBA", BAD, "ftp://ftp.biostar-usa.com/manuals/M6TBA/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("Biostar", "M7NCD Pro", OK, "http://www.biostar.com.tw/app/en/mb/introduction.php?S_ID=260", NULL), @@ -703,6 +711,7 @@ B("Boser", "HS-6637", BAD, "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf", "Reported by Mark Robinson <mark(a)zl2tod.net> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or F29C51002T unlocking. May work now."), B("Congatec", "conga-X852", OK, "http://www.congatec.com/single_news+M57715f6263d.html?&L=1", NULL), B("Dell", "Inspiron 580", BAD, "http://support.dell.com/support/edocs/systems/insp580/en/index.htm", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), + B("Dell", "OptiPlex 7010", BAD, NULL, "Mainboard model is 0KRC95. Probing works (Hardware Sequencing 4 + 8MB), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Dell", "OptiPlex GX1", OK, "http://support.dell.com/support/edocs/systems/ban_gx1/en/index.htm", NULL), B("Dell", "PowerEdge 1850", OK, "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm", NULL), B("Dell", "PowerEdge C6220", BAD, NULL, "Mainboard model is 0HYFFG. Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked (and there are even overlapping PRs)."), @@ -730,6 +739,7 @@ B("EPoX", "EP-8RDA3+", OK, "http://www.epox.com/product.asp?ID=EP-8RDA3plus", NULL), B("EPoX", "EP-9NPA7I", OK, "http://www.epox.com/product.asp?ID=EP-9NPA7I", NULL), B("EPoX", "EP-BX3", OK, "http://www.epox.com/product.asp?ID=EP-BX3", NULL), + B("EVGA", "122-CK-NF68", OK, NULL, NULL), B("EVGA", "132-CK-NF78", OK, "http://www.evga.com/articles/385.asp", NULL), B("EVGA", "270-WS-W555-A2 (Classified SR-2)", OK, "http://www.evga.com/products/moreInfo.asp?pn=270-WS-W555-A2", NULL), B("FIC", "VA-502", BAD, "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. Seems the PCI subsystem IDs are identical with the Tekram P6Pro-A5. May work now."), @@ -747,7 +757,6 @@ B("GIGABYTE", "GA-6IEM", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1379", NULL), B("GIGABYTE", "GA-6VXE7+", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2410", NULL), B("GIGABYTE", "GA-6ZMA", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1541", NULL), - B("GIGABYTE", "GA-MA785GMT-UD2H (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3156", NULL), B("GIGABYTE", "GA-770TA-UD3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3272", NULL), B("GIGABYTE", "GA-7DXR", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1302", NULL), B("GIGABYTE", "GA-7VT600", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), @@ -761,6 +770,7 @@ B("GIGABYTE", "GA-945PL-S3P (rev. 6.6)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2541", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), + B("GIGABYTE", "GA-A75M-UD2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3928", NULL), B("GIGABYTE", "GA-EP31-DS3L (rev. 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), B("GIGABYTE", "GA-EP35-DS3L", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-G41MT-S2PT", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3960", NULL), @@ -780,6 +790,7 @@ B("GIGABYTE", "GA-MA770-UD3 (rev. 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3302", NULL), B("GIGABYTE", "GA-MA770T-UD3P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), B("GIGABYTE", "GA-MA780G-UD3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3004", NULL), + B("GIGABYTE", "GA-MA785GMT-UD2H (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3156", NULL), B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), B("GIGABYTE", "GA-MA78GM-S2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2758", NULL), /* TODO: Rev. 1.BAD, 1.OK, or 2.x? */ B("GIGABYTE", "GA-MA78GPM-DS2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), @@ -788,8 +799,8 @@ B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("GIGABYTE", "GA-P67A-UD3P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL), + B("GIGABYTE", "GA-X58A-UD3R (rev. 2.0)", OK, NULL, NULL), B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", OK, NULL, NULL), - B("GIGABYTE", "GA-X58A-UDR3 (rev. 2.0)", OK, NULL, NULL), B("GIGABYTE", "GA-X79-UD5", OK, NULL, NULL), B("GIGABYTE", "GA-Z68MX-UD2H-B (rev. 1.3)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3854", NULL), B("GIGABYTE", "GA-Z68XP-UD3 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3892", NULL), @@ -813,11 +824,13 @@ B("Intel", "D201GLY", OK, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL), B("Intel", "D425KT", BAD, "http://www.intel.com/content/www/us/en/motherboards/desktop-motherboards/de…", "NM10 with SPI lock down, BIOS lock, see http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html"), B("Intel", "D865GLC", BAD, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775"), + B("Intel", "D945GCNL", OK, NULL, NULL), B("Intel", "DG45ID", BAD, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.h…", "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "DQ965GF", BAD, NULL, "Probing enables Hardware Sequencing (behind that hides a SST SST25VF016B, 2048 kB). Parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked (and the platform data region seems to be bogus)."), B("Intel", "DG965OT", BAD, NULL, "Probing enables Hardware Sequencing (behind that hides a SST SST25VF080B, 1024 kB). Parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked (and the platform data region seems to be bogus)."), B("Intel", "DH61AG ", BAD, NULL, "H61 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html"), B("Intel", "DH67CF", BAD, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html"), + B("Intel", "DH67CL", BAD, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2012-November/010112.html"), B("Intel", "DN2800MT (Marshalltown)", BAD, NULL, "BIOS locked via BIOS_CNTL."), B("Intel", "EP80759", OK, NULL, NULL), B("Intel", "Foxhollow", OK, NULL, "Intel reference board."), @@ -865,6 +878,7 @@ B("MSI", "MS-7309 (K9N6PGM2-V2)", OK, "http://www.msi.com/product/mb/K9N6PGM2-V2.html", NULL), B("MSI", "MS-7312 (K9MM-V)", OK, "http://www.msi.com/product/mb/K9MM-V.html", NULL), B("MSI", "MS-7345 (P35 Neo2-FIR)", OK, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), + B("MSI", "MS-7357 (G33M)", OK, "http://www.msi.com/product/mb/G33M.html", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", OK, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), B("MSI", "MS-7369 (K9N Neo V2)", OK, "http://www.msi.com/product/mb/K9N-Neo-V2.html", NULL), B("MSI", "MS-7376 (K9A2 Platinum V1)", OK, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), @@ -903,6 +917,7 @@ B("Shuttle", "AK38N", OK, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", OK, NULL, NULL), B("Shuttle", "AV18E2", OK, "http://www.shuttle.eu/_archive/older/de/av18.htm", NULL), + B("Shuttle", "FB61", OK, "http://www.shuttle.eu/_archive/older/en/fb61.htm#mainboardfb6", "Used in SB61G2 systems."), B("Shuttle", "FD37", OK, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL), B("Shuttle", "FH67", OK, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/", NULL), B("Shuttle", "FN25", OK, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL), @@ -931,6 +946,8 @@ B("Supermicro", "X8SIE(-F)", BAD, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", OK, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("Supermicro", "X9DR3-F", BAD, "http://www.supermicro.com/products/motherboard/xeon/c600/x9dr3-f.cfm", "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9DRT-HF+", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), + B("Supermicro", "X9DRW", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9QRi-F+", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C600/X9QRi-F_.cfm", "Probing works (Macronix MX25L12805, 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), B("Supermicro", "X9SCA-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9SCL", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), @@ -957,6 +974,7 @@ B("Tyan", "S2933 (Thunder n3600S)", OK, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=478&SKU=600000063", NULL), B("Tyan", "S3095 (Tomcat i945GM)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=181", NULL), B("Tyan", "S3992 (Thunder h2000M)", OK, "http://tyan.com/product_board_detail.aspx?pid=235", NULL), + B("Tyan", "S4882 (Thunder K8QS Pro)", OK, "http://www.tyan.com/archive/products/html/thunderk8qspro.html", NULL), B("Tyan", "S5180 (Toledo i965R)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=456", NULL), B("Tyan", "S5191 (Toledo i3000R)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=343", NULL), B("Tyan", "S5197 (Toledo i3010W)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=349", NULL), @@ -1008,6 +1026,8 @@ B("Dell", "Latitude CPi A366XT", BAD, "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop."), B("Dell", "Vostro 3700", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html."), B("Dell", "Latitude E6520", BAD, NULL, "Locked ME, see http://www.flashrom.org/pipermail/flashrom/2012-June/009420.html."), + B("Elitegroup", "A928", OK, NULL, "Bootsector is locked and needs to be skipped with a layout file (writeable address range is 00000000:0003bfff"), + B("HP/Compaq", "EliteBook 8560p", BAD, NULL, "SPI lock down, SMM protection, PR in BIOS region, read-only descriptor, locked ME region."), B("HP/Compaq", "nx9005", BAD, "http://h18000.www1.hp.com/products/quickspecs/11602_na/11602_na.HTML", "Shuts down when probing for a chip. http://www.flashrom.org/pipermail/flashrom/2010-May/003321.html"), B("HP/Compaq", "nx9010", BAD, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)."), B("IBM/Lenovo", "Thinkpad T40p", BAD, "http://www.thinkwiki.org/wiki/Category:T40p", NULL), Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Sun Dec 30 02:23:17 2012 (r1639) +++ trunk/serprog.c Tue Jan 1 01:06:51 2013 (r1640) @@ -223,7 +223,7 @@ { if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { msg_pdbg("Warning: Automatic command availability check failed " - "for cmd 0x%x - won't execute cmd\n", cmd); + "for cmd 0x%02x - won't execute cmd\n", cmd); return 1; } return 0; @@ -522,6 +522,7 @@ f_spi_req = strtol(spispeed, &f_spi_suffix, 0); if (errno != 0 || spispeed == f_spi_suffix) { msg_perr("Error: Could not convert 'spispeed'.\n"); + free(spispeed); return 1; } if (strlen(f_spi_suffix) == 1) { @@ -531,10 +532,12 @@ f_spi_req *= 1000; else { msg_perr("Error: Garbage following 'spispeed' value.\n"); + free(spispeed); return 1; } } else if (strlen(f_spi_suffix) > 1) { msg_perr("Error: Garbage following 'spispeed' value.\n"); + free(spispeed); return 1; }

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flashrom January 2013