February 2012 - flashrom - mail.coreboot.org

Re: [flashrom] Verified working on Gigabyte 880GMA-USB3
by Stefan Tauner Feb. 17, 2012

Feb. 17, 2012

On Mon, 13 Feb 2012 12:09:53 +0200 Shahar Or <mightyiampresence(a)gmail.com> wrote: > Dear ones, > > I'm not subscribed to the list so please reply directly. > > I've tested read and write on Gigabyte GA-880GMA-USB3 (rev 3.1). > > Thanks so much for enabling me to flash my BIOS ROM from Linux! > > Here's the link to the mainboard's page in Gigabyte: > http://www.gigabyte.com/products/product-page.aspx?pid=3817 Hello Shahar, thanks for your report! I have marked the mainboard as tested and will commit that later together with other small changes. It would be appreciated if you could upload verbose logs of flashrom with such reports (at least a verbose probing with flashrom -V). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add a bunch of new/tested stuff and various small changes 10
by Stefan Tauner Feb. 17, 2012

Feb. 17, 2012

was committed with some additional changes in r1499. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for SFDP (JESD216).
by Carl-Daniel Hailfinger Feb. 17, 2012

Feb. 17, 2012

And here's the rest of the review, as promised. Please note that I do not have the stgandard at hand, so this is not a correctness review, but a code review. Am 31.01.2012 06:59 schrieb Stefan Tauner: > --- /dev/null > +++ b/sfdp.c > @@ -0,0 +1,355 @@ [...] > +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) *flash instead of *f, please. > +{ > + uint32_t tmp32; > + uint8_t tmp8; > + uint32_t total_size; /* in bytes */ > + uint32_t bsize; > + uint8_t opcode_4k = 0xFF; > + int dw, j; > + > + msg_cdbg("Parsing JEDEC SFDP parameter table... "); ... JEDEC flash parameter table... > + if (len != 9 * 4 && len != 4 * 4) { > + msg_cerr("%s: len out of spec\n", __func__); > + return 1; > + } > + msg_cdbg2("\n"); > + > + /* 1. double word */ > + dw = 0; > + tmp32 = buf[(4 * dw) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; > + > + tmp8 = (tmp32 >> 17) & 0x3; > + switch (tmp8) { > + case 0x0: > + msg_cdbg2(" 3-Byte only addressing.\n"); > + break; > + case 0x1: > + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); > + break; > + case 0x2: > + msg_cdbg(" 4-Byte only addressing not supported.\n"); > + return 1; > + default: > + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", > + tmp8); > + return 1; > + } > + > + msg_cdbg2(" Writes to the status register have "); > + if (tmp32 & (1 << 3)) { > + msg_cdbg2("to be enabled with "); > + if (tmp32 & (1 << 4)) { > + f->feature_bits = FEATURE_WRSR_WREN; > + msg_cdbg2("WREN (0x06).\n"); > + } else { > + f->feature_bits = FEATURE_WRSR_EWSR; > + msg_cdbg2("EWSR (0x50).\n"); > + } > + } else > + msg_cdbg2("not to be especially enabled.\n"); The "Writing to Volatile Status Register" part of JESD216 is one of the most confusing wordings I ever saw in a standard. I expect some flash chip vendors to conform to the letter of the spec which will cause pretty explosions: If the status register is nonvolatile and needs EWSR or WREN for writes, the standard explicitly requires the vendor to set bits 3+4 to 0 (EWSR/WREN not needed). I don't think JEDEC understood the implications of that wording. Suggestion for a standards-conforming code flow: msg_cdbg2(" Status register is "); if (tmp32 & (1 << 3)) { msg_cdbg2("volatile and writes to the status register have to be enabled with "); [your bit 4 code] } else msg_cdbg2("nonvolatile and the standard does not allow vendors to tell us whether EWSR/WREN is needed for status register writes"); > + > + msg_cdbg2(" Write granularity is "); I know they call it write granularity, but flashrom calls it writechunk size. Please use our terminology here even if the standard calls it differently. You can add a comment if you think that clarifies the code for future developers. > + if (tmp32 & (1 << 2)) { > + msg_cdbg2("at least 64 B.\n"); > + f->write = spi_chip_write_256; Please insert flash->page_size = 64; > + } else { > + msg_cdbg2("1 B only.\n"); > + f->write = spi_chip_write_1; flash->page_size = 256; (I know that page_size needs to die, but right now we use it.) > + } > + > + if ((tmp32 & 0x3) == 0x1) { > + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ > + } What about this instead? switch (tmp32 & 0x03) { case 0x0: case 0x2: msg_cerr("4k erase is reserved... should not happen"); return 1; break; case 0x1: opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ break; case 0x3: if (((tmp32 >> 8) & 0xFF) != 0xFF) { msg_cdbg("wtf inconsistent 4k erase settings?!?"); return 1; } } Admittedly, the wording could be better. > + > + /* 2. double word */ > + dw = 1; > + tmp32 = buf[(4 * dw) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; > + > + if (tmp32 & (1 << 31)) { > + msg_cerr("Flash chip size >= 4 Gb/512 MB not supported.\n"); > + return 1; > + } > + total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; > + f->total_size = total_size / 1024; > + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); > + > + /* FIXME: double words 3-7 contain unused fast read information */ > + > + if (len == 4 * 4) { > + msg_cdbg("It seems like this chip supports the preliminary " > + "Intel version of SFDP, skipping processing of double " > + "words 3-9.\n"); > + goto proc_4k; > + } > + > + dw = 8; > + for (j = 0; j < 4; j++) { > + /* 8 double words from the start + 2 words for every eraser */ > + tmp32 = buf[(4 * dw) + (2 * j)]; use tmp8 instead? > + if (tmp32 == 0) { > + msg_cdbg2(" Block eraser %d is unused.\n", j); > + continue; > + } > + if (tmp32 >= 31) { > + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." "... too big for flashrom." > + "\n", j, tmp32); > + continue; > + } > + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ > + > + tmp8 = buf[(4 * dw) + (2 * j) + 1]; > + if(sfdp_add_uniform_eraser(f, tmp8, bsize)) > + continue; > + /* If there is a valid 4k value in the last double words, > + * we want to override the value from double word 1, hence force > + * skipping its processing: */ > + if (bsize == 4 * 1024) > + opcode_4k = 0xFF; Not really. What happens if there are multiple valid opcodes for 4k erase? Such chips do exist IIRC. What about if (bsize == 4 * 1024) { if (tmp8 == opcode_4k) opcode_4k == 0xFF; else msg_cdbg("More than one 4kB eraser opcode found: 0x%02x and 0x%02x.", tmp8, opcode_4k); } > + } > + > +proc_4k: > + if (opcode_4k != 0xFF) { > + sfdp_add_uniform_eraser(f, opcode_4k, 4 * 1024); > + } > + msg_cdbg("done.\n"); > + return 0; > +} > + > +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) > +{ > + uint16_t i; > + if (spi_sfdp(flash, addr, buf, len)) { > + msg_cerr("Receiving SFDP parameter table failed.\n"); > + return 1; > + } > + msg_cspew(" Parameter table contents:\n"); > + for(i = 0; i < len; i++) { > + if ((i % 8) == 0) { > + msg_cspew(" 0x%03x: ", i); > + } > + msg_cspew(" 0x%02x", buf[i]); > + if ((i % 8) == 7) { > + msg_cspew("\n"); > + continue; > + } > + if ((i % 8) == 3) { > + msg_cspew(" "); > + continue; > + } > + } > + msg_cspew("\n"); Do we have some generic hexdump() function? I agree that dumping the parameter table contents may make sense, but open-coding your own hexdump is probably not the best idea. Do we want this hexdump functionality at all, and if yes, should it be factored out? > + return 0; > +} > + > +int probe_spi_sfdp(struct flashctx *flash) > +{ > + int ret = 0; > + uint8_t buf[8]; > + uint32_t tmp32; > + uint8_t nph; > + /* need to limit the table loop by comparing i to uint8_t nph hence: */ > + uint16_t i; > + struct sfdp_tbl_hdr *hdrs; > + uint8_t *hbuf; > + uint8_t *tbuf; > + > + if (spi_sfdp(flash, 0x00, buf, 4)) { > + msg_cerr("Receiving SFDP signature failed.\n"); Hmmm... should all boards with IT87/ICH SPI and unknown flash chips see an error message? While I'm often for upgrading error messages to msg_*err, I believe that this case should be rather mag_*dbg. > + return 0; > + } > + tmp32 = buf[0]; > + tmp32 |= ((unsigned int)buf[1]) << 8; > + tmp32 |= ((unsigned int)buf[2]) << 16; > + tmp32 |= ((unsigned int)buf[3]) << 24; > + > + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); > + if (tmp32 != 0x50444653) { > + msg_cdbg("No SFDP signature found.\n"); > + return 0; > + } > + if (spi_sfdp(flash, 0x04, buf, 3)) { > + msg_cerr("Receiving SFDP revision and number of parameter " > + "headers (NPH) failed. "); > + return 0; > + } > + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); return 0 if major revision is unknown (i.e. not 0x01). A new major revision may change the meaning of any field and that's why we should abort. > + nph = buf[2]; > + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" > + "\n", nph); > + > + /* Fetch all parameter headers, even if we don't use them all (yet). */ > + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); > + hdrs = malloc((nph + 1) * 8); Why is 8 a magic unexplained constant for hdrs allocation, but sizeof struct sfdp_tbl_hdr (which is 8 as well) is used for hbuf allocation? Did you mix up the two by accident? And why is (nph+1) the first factor in the second malloc and the second factor in the first malloc? > + if (hbuf == NULL || hdrs == NULL ) { > + msg_gerr("Out of memory!\n"); insert the following code: ret = 0; goto cleanup_hdrs; > + exit(1); /* FIXME: shutdown gracefully */ and kill the exit(1). It would be nice to change the probe interface to return 0 on success... that would allow us to return detailed errors. OTOH, we might want to use the probe interface to return match accuracy, in which case 0 would be nomatch. Comments appreciated. > + } > + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { > + msg_cerr("Receiving SFDP parameter table headers failed.\n"); > + goto cleanup_hdrs; > + } > + > + i = 0; > + do { for (i=0; i <=nph; i++) { > + uint16_t len; > + hdrs[i].id = hbuf[(8 * i) + 0]; > + hdrs[i].v_minor = hbuf[(8 * i) + 1]; > + hdrs[i].v_major = hbuf[(8 * i) + 2]; > + hdrs[i].len = hbuf[(8 * i) + 3]; > + hdrs[i].ptp = hbuf[(8 * i) + 4]; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; > + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); > + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, > + hdrs[i].v_major, hdrs[i].v_minor); > + len = hdrs[i].len * 4; > + tmp32 = hdrs[i].ptp; > + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", > + len, tmp32); > + > + if (len + tmp32 > UINT16_MAX) { > + msg_cerr("SFDP Parameter Table %d supposedly " > + "overflows addressable SFDP area. This most\n" > + "probably indicates a corrupt SFDP parameter " > + "table header. Aborting SFDP probe!\n", i); > + ret = 0; > + goto cleanup_hdrs; > + } > + > + tbuf = malloc(len); > + if (tbuf == NULL) { > + msg_gerr("Out of memory!\n"); insert the following code: ret = 0; goto cleanup_hdrs; > + exit(1); /* FIXME: shutdown gracefully */ and kill the exit(1) > + } > + if (sfdp_fetch_pt(flash, tmp32, tbuf, len)){ > + msg_cerr("Fetching SFDP parameter table %d failed.\n", > + i); > + free(tbuf); > + break; > + } > + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ > + if (hdrs[i].id != 0) > + msg_cdbg("ID of the mandatory JEDEC SFDP " msg_cerr, then cleanup and return 0. Maybe even ask user to report? > + "parameter table is not 0 as demanded " > + "by JESD216 (warning only).\n"); Check hdrs[i].v_major here and do the error dance for unexpected values. > + > + if (len != 9 * 4 && len != 4 * 4) { > + msg_cdbg("Length of the mandatory JEDEC SFDP " msg_cerr, then cleanup and return 0. Maybe even ask user to report? > + "parameter table is %d B instead of " > + "36 B (i.e. 9 double words) as " > + "demanded by JESD216, skipping " > + "parsing.\n", len); > + } else if (sfdp_fill_flash(flash, tbuf, len) == 0) > + ret = 1; > + } > + > + free(tbuf); > + i++; > + } while(i <= nph); > + > +cleanup_hdrs: > + free(hdrs); > + free(hbuf); > + return ret; > +} Cross-checked against the standard, looks pretty good. Next round will be acked. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1499 - trunk
by repository service Feb. 16, 2012

Feb. 16, 2012

Author: stefanct Date: Thu Feb 16 22:07:07 2012 New Revision: 1499 URL: http://flashrom.org/trac/flashrom/changeset/1499 Log: Add a bunch of new/tested stuff and various small changes 10 Tested mainboards: OK: - ABIT A-S78H http://www.flashrom.org/pipermail/flashrom/2012-January/008603.html - ASRock AM2NF6G-VSTA http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - ASUS KFSN4-DRE/SAS reported by ted on IRC - ASUS M2A-VM (HDMI variant) http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html - ASUS M4N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008598.html - ASUS P5K-V http://www.flashrom.org/pipermail/flashrom/2012-February/008737.html - ASUS P5KPL-CM http://www.flashrom.org/pipermail/flashrom/2012-January/008522.html - ASUS P5N7A-VM http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - ASUS P5QPL-AM http://www.flashrom.org/pipermail/flashrom/2012-January/008557.html - ECS GF7100PVT-M3 http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - ECS K7SEM http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - ECS P4M800PRO-M V2.0 http://www.flashrom.org/pipermail/flashrom/2012-January/008478.html - Gigabyte 880GMA-USB3 http://www.flashrom.org/pipermail/flashrom/2012-February/008715.html - Gigabyte GA-EP31-DS3L http://www.flashrom.org/pipermail/flashrom/2012-January/008601.html - Gigabyte GA-X58A-UDR3 http://www.flashrom.org/pipermail/flashrom/2012-January/008572.html - Gigabyte GA-Z68XP-UD3 http://paste.flashrom.org/view.php?id=1058 - HP ProLiant N40L http://www.flashrom.org/pipermail/flashrom/2012-February/008650.html - MSI MS-7309 (K9N6PGM2-V2) http://www.flashrom.org/pipermail/flashrom/2011-December/008441.html - MSI MS-7548 (Aspen-GL8E used in HP Pavilion a6750f) http://www.flashrom.org/pipermail/flashrom/2012-February/008666.html - MSI MS-7676 (H67MA-ED55(B3)) http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html - PC Engines Alix.6f2 Reported by Philip Prindeville on IRC - Shuttle AV18E2 http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - Supermicro X8DTE-F http://www.flashrom.org/pipermail/flashrom/2011-November/008304.html - Supermicro X8DTT-HIBQF http://www.flashrom.org/pipermail/flashrom/2012-January/008520.html NOT OK: - ASUS P8H61-M LE/USB3 http://www.flashrom.org/pipermail/flashrom/2012-January/008491.html - ASUS P8H67-M PRO http://www.flashrom.org/pipermail/flashrom/2011-December/008321.html - ASUS P8Z68-V PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008469.html - Clevo P150HM (laptop) http://www.flashrom.org/pipermail/flashrom/2012-February/008717.html - Intel D425KT http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html - Supermicro X9SCA-F http://www.flashrom.org/pipermail/flashrom/2011-December/008313.html Tested flash chips: - mark AT29C512 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=977 - mark M25P40 as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-December/008351.html - mark M25PE80 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=1061 - mark MX25L6405 as TEST_OK_PREW tested myself with an MX25L6436E variant on serprog - mark W39V080A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html Tested chipsets: - SiS 730 (:0730) http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - NVIDIA MCP61 (:03e0) http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - NVIDIA MCP73 (:07d7) http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - NVIDIA MCP79 (:0aac) http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - VIA VT82C69x (0691) and VT82C686A/B (:0686) http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - AMD's SB950 (and presumably also SB920) have the same PCI ID as previous generations, hence change the chipset enable device string. Thanks to Christian Ruppert for the suggestion. - Fix the board enable of the abit NF-M2 nView which had the IDs of its onboard graphics card in its pattern. Change this to the LPC controller. - Intel X79 SPI registers are identical to 6 Series', so use the chipsetenable wrapper of it (enable_flash_pch6). - Fix two paranoid checks for address < 0 in ichspi.c which became futile (and generate clang warnings) with the unsignify patch committed in r1470. - Rename AT25DF641 to AT25DF641(A). They are almost idencical, but could be distinguished by an extended RDID probe (Atmel's patented EDI procedure), which we do not support yet, hence handle them as one model for now. - Source format fixes and typos the addition of the ASRock AM2NF6G-VSTA to print.c is Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/dediprog.c trunk/dummyflasher.c trunk/flashchips.c trunk/flashchips.h trunk/ichspi.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/board_enable.c Thu Feb 16 22:07:07 2012 (r1499) @@ -1562,7 +1562,7 @@ /* * Suited for: * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ... - * - FCS ESPRIMO Q5010 (SMBIOS: D2544-B1) + * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1) */ static int intel_ich_gpio38_raise(void) { @@ -2114,7 +2114,7 @@ {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/chipset_enable.c Thu Feb 16 22:07:07 2012 (r1499) @@ -1155,7 +1155,7 @@ #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, @@ -1178,7 +1178,7 @@ {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, - {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, @@ -1222,7 +1222,7 @@ {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ - {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, @@ -1233,8 +1233,8 @@ {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, - {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, + {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, @@ -1243,12 +1243,12 @@ {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, - {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */ + {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, /* VIA southbridges */ {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, - {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_amd8111}, {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, @@ -1279,8 +1279,8 @@ {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, - {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ - {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ + {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_pch6}, + {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_pch6}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/dediprog.c Thu Feb 16 22:07:07 2012 (r1499) @@ -299,7 +299,7 @@ return 0; } -/* Bulk write interface, will read multiple page_size byte chunks aligned to page_size bytes. +/* Bulk write interface, will write multiple page_size byte chunks aligned to page_size bytes. * @start start address * @len length * @return 0 on success, 1 on failure Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/dummyflasher.c Thu Feb 16 22:07:07 2012 (r1499) @@ -435,7 +435,7 @@ msg_perr("No command sent to the chip!\n"); return 1; } - /* spi_blacklist has precedence before spi_ignorelist. */ + /* spi_blacklist has precedence over spi_ignorelist. */ for (i = 0; i < spi_blacklist_size; i++) { if (writearr[0] == spi_blacklist[i]) { msg_pdbg("Refusing blacklisted SPI command 0x%02x\n", Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/flashchips.c Thu Feb 16 22:07:07 2012 (r1499) @@ -1579,7 +1579,7 @@ { .vendor = "Atmel", - .name = "AT25DF641", + .name = "AT25DF641(A)", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT25DF641, @@ -1967,7 +1967,7 @@ .total_size = 64, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10000, /* 10mS, Enter=Exec */ .block_erasers = @@ -4427,7 +4427,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4957,7 +4957,7 @@ .model_id = ST_M25PE80, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6910,7 +6910,7 @@ .model_id = ST_M25P40, .total_size = 512, .page_size = 256, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8690,9 +8690,9 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/flashchips.h Thu Feb 16 22:07:07 2012 (r1499) @@ -364,7 +364,7 @@ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L3205{,D} */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D}, MX25L6406E, MX25L6436E */ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/ichspi.c Thu Feb 16 22:07:07 2012 (r1499) @@ -1286,7 +1286,7 @@ uint16_t timeout = 100 * 60; uint8_t block_len; - if (addr < 0 || addr + len > flash->total_size * 1024) { + if (addr + len > flash->total_size * 1024) { msg_perr("Request to read from an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; @@ -1324,7 +1324,7 @@ uint16_t timeout = 100 * 60; uint8_t block_len; - if (addr < 0 || addr + len > flash->total_size * 1024) { + if (addr + len > flash->total_size * 1024) { msg_perr("Request to write to an inaccessible memory address " "(addr=0x%x, len=%d).\n", addr, len); return -1; Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Feb 16 22:00:27 2012 (r1498) +++ trunk/print.c Thu Feb 16 22:07:07 2012 (r1499) @@ -546,6 +546,7 @@ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), + B("abit", "A-S78H", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AV8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), @@ -565,7 +566,7 @@ B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", 1, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", 1, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ - B("AOpen", "i945GMx-VFX", 1, NULL, "This is (also?) an OEM board from FCS (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), + B("AOpen", "i945GMx-VFX", 1, NULL, "This is (also?) an OEM board from FSC (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), B("AOpen", "vKM400Am-S", 1, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", 1, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), @@ -576,6 +577,7 @@ B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), + B("ASRock", "AM2NF6G-VSTA", 1, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), B("ASRock", "ConRoeXFire-eSATA2", 1, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7S41GX", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL), @@ -594,7 +596,7 @@ B("ASUS", "A7V8X-MX", 1, "http://www.asus.com/Motherboards/AMD_Socket_A/A7V8XMX/", NULL), B("ASUS", "A7V8X-MX SE", 1, "http://www.asus.com/Motherboards/AMD_Socket_A/A7V8XMX_SE/", NULL), B("ASUS", "A7V8X-X", 1, "http://www.asus.com/Motherboards/AMD_Socket_A/A7V8XX/", NULL), - B("ASUS", "A8M2N-LA (NodusM3-GL8E)", 1, "http://h10010.www1.hp.com/ewfrf/wc/document?docname=c00757531&cc=us&dlc=en&…", "This is an OEM board from HP, the HP name is NodusM3-GL8E."), + B("ASUS", "A8M2N-LA (NodusM3-GL8E)", 1, "http://h10010.www1.hp.com/ewfrf/wc/document?docname=c00757531&cc=us&dlc=en&…", "This is an OEM board from HP, the HP name is NodusM3-GL8E."), B("ASUS", "A8N-E", 1, "http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/", NULL), B("ASUS", "A8N-LA (Nagami-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&cc=us&docname=c00647121&d…", "This is an OEM board from HP, the HP name is Nagami-GL8E."), B("ASUS", "A8N-SLI", 1, "http://www.asus.com/Motherboards/AMD_Socket_939/A8NSLI/", NULL), @@ -614,8 +616,9 @@ B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/Motherboards/AMD_Socket_754/K8V_SE_Deluxe/", NULL), B("ASUS", "K8V-X", 1, "http://www.asus.com/Motherboards/AMD_Socket_754/K8VX/", NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/Motherboards/AMD_Socket_754/K8VX_SE/", NULL), + B("ASUS", "KFSN4-DRE/SAS", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/KFSN4DRESAS/", NULL), B("ASUS", "M2A-MX", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AMX/", NULL), - B("ASUS", "M2A-VM", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AVM/", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html"), + B("ASUS", "M2A-VM (HDMI)", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2AVM/", NULL), B("ASUS", "M2N32-SLI Deluxe", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2N32SLI_DeluxeWireless_Edition/", NULL), B("ASUS", "M2N-E", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2NE/", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html"), B("ASUS", "M2N-E SLI", 1, "http://www.asus.com/Motherboards/AMD_AM2/M2NE_SLI/", NULL), @@ -629,12 +632,13 @@ B("ASUS", "M3A78-EM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M3A78EM/", NULL), B("ASUS", "M3N78-VM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M3N78VM/", NULL), B("ASUS", "M4A78-EM", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/", NULL), - B("ASUS", "M4A785TD-V EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDV_EVO/", NULL), B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDM_EVO/", NULL), + B("ASUS", "M4A785TD-V EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A785TDV_EVO/", NULL), B("ASUS", "M4A78LT-M LE", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A78LTM_LE/", NULL), B("ASUS", "M4A79T Deluxe", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A79T_Deluxe/", NULL), B("ASUS", "M4A87TD/USB3", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A87TDUSB3/", NULL), B("ASUS", "M4A89GTD PRO", 1, "http://www.asus.com/Motherboards/AMD_AM3/M4A89GTD_PRO/", NULL), + B("ASUS", "M4N78 PRO", 1, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_PRO/", NULL), B("ASUS", "M5A99X EVO", 1, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/", NULL), B("ASUS", "MEW-AM", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "MEW-VM", 0, "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -670,8 +674,10 @@ B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5GDC_Deluxe/", NULL), B("ASUS", "P5GDC-V Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5GDCV_Deluxe/", NULL), B("ASUS", "P5GD2/C variants", 0, NULL, "Untested board enable."), + B("ASUS", "P5K-V", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KV/", NULL), B("ASUS", "P5K-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KVM/", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KC/", NULL), + B("ASUS", "P5KPL-CM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5KPLCM/", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), @@ -682,8 +688,10 @@ B("ASUS", "P5N-D", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5ND/", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/Motherboards/Intel_Socket_775/P5NE_SLI/", "Untested board enable."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5N32E_SLI/", NULL), + B("ASUS", "P5N7A-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5N7AVM/", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5ND2SLI_Deluxe/", NULL), B("ASUS", "P5PE-VM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5PEVM/", NULL), + B("ASUS", "P5QPL-AM", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5QPLAM/", NULL), B("ASUS", "P5VD1-X", 1, "http://www.asus.com/Motherboards/Intel_Socket_775/P5VD1X/", NULL), B("ASUS", "P6T SE", 1, "http://www.asus.com/Motherboards/Intel_Socket_1366/P6T_SE/", NULL), B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/Motherboards/Intel_Socket_1366/P6T_Deluxe/", NULL), @@ -693,7 +701,10 @@ B("ASUS", "P8B-E/4L", 0, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8B WS", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H61 PRO", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H61-M LE/USB3", 0, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H67-M PRO", 0, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8P67 (rev. 3.1)", 0, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8Z68-V PRO", 0, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8NAD6C/", NULL), B("ASUS", "Z8PE-D12", 1, "http://www.asus.com/Server_Workstation/Server_Motherboards/Z8PED12/", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), @@ -710,10 +721,12 @@ B("DFI", "855GME-MGF", 0, "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…", "Probably needs a board enable. http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html"), B("DFI", "Blood-Iron P35 T2RL", 1, "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL), B("Elitegroup", "GeForce6100SM-M ", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=685&M…", NULL), + B("Elitegroup", "GF7100PVT-M3 (V1.0)", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=853&C…", NULL), B("Elitegroup", "K7S5A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…", NULL), B("Elitegroup", "K7S6A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…", NULL), + B("Elitegroup", "K7SEM (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=229&C…", NULL), B("Elitegroup", "K7VTA3", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…", NULL), - B("Elitegroup", "P4M800PRO-M (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), + B("Elitegroup", "P4M800PRO-M (V1.0A, V2.0)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P4VXMS (V1.0A)", 1, NULL, NULL), B("Elitegroup", "P6IWP-Fe", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6VAP-A+", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…", NULL), @@ -743,6 +756,7 @@ B("GIGABYTE", "GA-7DXR", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1302", NULL), B("GIGABYTE", "GA-7VT600", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), + B("GIGABYTE", "GA-880GMA-USB3 (rev. 3.1)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3817", NULL), B("GIGABYTE", "GA-8I945GZME-RH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2304", NULL), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), @@ -751,6 +765,7 @@ B("GIGABYTE", "GA-945PL-S3P (rev. 6.6)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2541", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), + B("GIGABYTE", "GA-EP31-DS3L (rev. 2.1)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), @@ -774,10 +789,13 @@ B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("GIGABYTE", "GA-P67A-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL), B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", 1, NULL, NULL), + B("GIGABYTE", "GA-X58A-UDR3 (rev. 2.0)", 1, NULL, NULL), B("GIGABYTE", "GA-Z68MX-UD2H-B (rev. 1.3)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3854", NULL), + B("GIGABYTE", "GA-Z68XP-UD3 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3892", NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), + B("HP", "ProLiant N40L", 1, NULL, NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), B("HP", "Vectra VL400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "Vectra VL420 SFF", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), @@ -787,6 +805,7 @@ B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), B("Intel", "D201GLY", 1, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL), + B("Intel", "D425KT", 0, "http://www.intel.com/content/www/us/en/motherboards/desktop-motherboards/de…", "NM10 with SPI lock down, BIOS lock, see http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html"), B("Intel", "D865GLC", 0, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775"), B("Intel", "DG45ID", 0, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.h…", "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "DH67CF", 0, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html"), @@ -830,6 +849,7 @@ B("MSI", "MS-7253 (K9VGM-V)", 1, "http://www.msi.com/product/mb/K9VGM-V.html", NULL), B("MSI", "MS-7255 (P4M890M)", 1, "http://www.msi.com/product/mb/P4M890M-L-IL.html", NULL), B("MSI", "MS-7260 (K9N Neo PCB 1.0)", 0, "http://www.msi.com/product/mb/K9N-Neo--PCB-1-0-.html", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), + B("MSI", "MS-7309 (K9N6PGM2-V2)", 1, "http://www.msi.com/product/mb/K9N6PGM2-V2.html", NULL), B("MSI", "MS-7312 (K9MM-V)", 1, "http://www.msi.com/product/mb/K9MM-V.html", NULL), B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), @@ -837,12 +857,14 @@ B("MSI", "MS-7376 (K9A2 Platinum V1)", 1, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), B("MSI", "MS-7529 (G31M3-L(S) V2)", 1, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), B("MSI", "MS-7529 (G31TM-P21)", 1, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), + B("MSI", "MS-7548 (Aspen-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01635688&lc=en&cc=us&d…", NULL), B("MSI", "MS-7596 (785GM-E51)", 1, "http://www.msi.com/product/mb/785GM-E51.html", NULL), B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7613 (Iona-GL8E)", 0, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c02014355&lc=en&cc=dk&d…", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("MSI", "MS-7635 (H55M-ED55)", 0, "http://www.msi.com/product/mb/H55M-ED55.html", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", NULL), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/product/mb/890GXM-G65.html", NULL), + B("MSI", "MS-7676 (H67MA-ED55(B3))", 1, "http://www.msi.com/product/mb/H67MA-ED55--B3-.html", "Seems to work fine basically, but user reported (hopefully unrelated) buggy behavior of the board after a firmware upgrade. See http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html"), B("MSI", "MS-7696 (A75MA-G55)", 1, "http://www.msi.com/product/mb/A75MA-G55.html", NULL), B("MSI", "MS-7698 (E350IA-E45)", 1, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), @@ -855,6 +877,7 @@ B("PC Engines", "Alix.2d3", 1, "http://pcengines.ch/alix2d3.htm", NULL), B("PC Engines", "Alix.3c3", 1, "http://pcengines.ch/alix3c3.htm", NULL), B("PC Engines", "Alix.3d3", 1, "http://pcengines.ch/alix3d3.htm", NULL), + B("PC Engines", "Alix.6f2", 1, "http://pcengines.ch/alix6f2.htm", NULL), B("PC Engines", "WRAP.2E", 1, "http://pcengines.ch/wrap2e1.htm", NULL), B("Portwell", "PEB-4700VLA", 1, "http://www.portwell.com/products/detail.asp?CUSTCHAR1=PEB-4700VLA", NULL), B("RCA", "RM4100", 1, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL), @@ -862,6 +885,7 @@ B("Shuttle", "AK31", 1, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL), B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", 1, NULL, NULL), + B("Shuttle", "AV18E2", 1, "http://www.shuttle.eu/_archive/older/de/av18.htm", NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL), B("Shuttle", "FH67", 1, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/", NULL), B("Shuttle", "FN25", 1, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL), @@ -880,12 +904,15 @@ B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), B("Supermicro", "X7SPA-HF", 1, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPA.cfm?typ=H&IP…", NULL), B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), + B("Supermicro", "X8DTE-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT6-F.cfm?IPMI=Y&…", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTT-HIBQF", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-H.cfm", NULL), B("Supermicro", "X8DTU-6TF+", 0, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU_.cfm?TYP=SAS&…", "Probing works (Atmel AT25DF321A, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), + B("Supermicro", "X9SCA-F", 0, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9SCL", 0, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), @@ -951,11 +978,12 @@ B("ASUS", "A8Jm", 1, NULL, NULL), B("ASUS", "Eee PC 701 4G", 0, "http://www.asus.com/Eee/Eee_PC/Eee_PC_4G/", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)."), B("ASUS", "M6Ne", 0, "http://www.asus.com/Notebooks/Versatile_Performance/M6NNe/", "Untested board enable."), + B("Clevo", "P150HM", 0, "http://www.clevo.com.tw/en/products/prodinfo_2.asp?productid=307", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Dell", "Latitude CPi A366XT", 0, "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop."), B("HP/Compaq", "nx9005", 0, "http://h18000.www1.hp.com/products/quickspecs/11602_na/11602_na.HTML", "Shuts down when probing for a chip. http://www.flashrom.org/pipermail/flashrom/2010-May/003321.html"), B("HP/Compaq", "nx9010", 0, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)."), B("IBM/Lenovo", "Thinkpad T40p", 0, "http://www.thinkwiki.org/wiki/Category:T40p", NULL), - B("IBM/Lenovo", "Thinkpad T410s", 0, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25x64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME and platform are locked."), + B("IBM/Lenovo", "Thinkpad T410s", 0, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME and platform are locked."), B("IBM/Lenovo", "240", 0, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."), B("Lenovo", "3000 V100 TF05Cxx", 1, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL), #endif

1 0

[PATCH] Document and enable the linux_spi driver
by Carl-Daniel Hailfinger Feb. 16, 2012

Feb. 16, 2012

The linux_spi driver is now enabled by default on Linux. A man page entry and a line in --list-supported output have been added. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-linux_spi_documentation/Makefile =================================================================== --- flashrom-linux_spi_documentation/Makefile (Revision 1495) +++ flashrom-linux_spi_documentation/Makefile (Arbeitskopie) @@ -209,6 +209,14 @@ endif endif +ifneq ($(TARGET_OS), Linux) +ifeq ($(CONFIG_LINUX_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LINUX_SPI=yes +else +override CONFIG_LINUX_SPI = no +endif +endif + # Determine the destination processor architecture. # IMPORTANT: The following line must be placed before ARCH is ever used # (of course), but should come after any lines setting CC because the line @@ -324,16 +332,15 @@ # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATE_SPI ?= yes -# Disable Linux spidev interface support for now, until we check for a Linux -# device (not host, as DOS binaries for example are built on a Linux host). -CONFIG_LINUX_SPI ?= no - # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no # Always enable Marvell SATA controllers for now. CONFIG_SATAMV ?= yes +# Enable Linux spidev interface by default. We disable it on non-Linux targets. +CONFIG_LINUX_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -465,11 +472,6 @@ NEED_SERIAL := yes endif -ifeq ($(CONFIG_LINUX_SPI), yes) -FEATURE_CFLAGS += -D'CONFIG_LINUX_SPI=1' -PROGRAMMER_OBJS += linux_spi.o -endif - ifeq ($(CONFIG_DEDIPROG), yes) FEATURE_CFLAGS += -D'CONFIG_DEDIPROG=1' FEATURE_LIBS += -lusb @@ -482,6 +484,11 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_LINUX_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_LINUX_SPI=1' +PROGRAMMER_OBJS += linux_spi.o +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-linux_spi_documentation/flashrom.8 =================================================================== --- flashrom-linux_spi_documentation/flashrom.8 (Revision 1495) +++ flashrom-linux_spi_documentation/flashrom.8 (Arbeitskopie) @@ -205,6 +205,8 @@ .sp .BR "* ogp_spi" " (for SPI flash ROMs on Open Graphics Project graphics card)" .sp +.BR "* linux_spi" " (for SPI flash ROMs accessible via /dev/spidevX.Y on Linux)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -607,6 +609,17 @@ .sp More information about the hardware is available at .BR http://wiki.opengraphics.org . +.TP +.BR "linux_spi " programmer +You have to specify the SPI controller to use with the +.sp +.B " flashrom \-p linux_spi:dev=/dev/spidevX.Y" +.sp +syntax where +.B /dev/spidevX.Y +is the Linux device node for your SPI controller. +.sp +Please note that the linux_spi driver only works on Linux. .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. Index: flashrom-linux_spi_documentation/print.c =================================================================== --- flashrom-linux_spi_documentation/print.c (Revision 1495) +++ flashrom-linux_spi_documentation/print.c (Arbeitskopie) @@ -527,6 +527,11 @@ programmer_table[PROGRAMMER_SATAMV].name); print_supported_pcidevs(satas_mv); #endif +#if CONFIG_LINUX_SPI == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_LINUX_SPI].name); + msg_ginfo("Device files /dev/spidev*.*\n"); +#endif } #if CONFIG_INTERNAL == 1 -- http://www.hailfinger.org/

2 4

[PATCH] Reenable forced read
by Carl-Daniel Hailfinger Feb. 16, 2012

Feb. 16, 2012

Forced read functionality was disabled when programmer registration was merged in r. We now support registering more than one controller at once for each bus type. This can happen e.g. if one SPI controller has an attached flash chip and one controller doesn't. In such a case we rely on the probe mechanism to find exactly one chip, and the probe mechanism will remember which controller/bus the flash chip is attached to. A forced read does not have the luxury of knowing which compatible controller to use, so this case is handled by always picking the first one. That may or may not be the correct one, but there is no way (yet) to specify which controller a flash chip is attached to. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-forced_read_reenable/cli_classic.c =================================================================== --- flashrom-forced_read_reenable/cli_classic.c (Revision 1495) +++ flashrom-forced_read_reenable/cli_classic.c (Arbeitskopie) @@ -456,11 +456,27 @@ printf("Note: flashrom can never write if the flash " "chip isn't found automatically.\n"); } -#if 0 // FIXME: What happens for a forced chip read if multiple compatible programmers are registered? if (force && read_it && chip_to_probe) { + struct registered_programmer *pgm; + int compatible_programmers = 0; printf("Force read (-f -r -c) requested, pretending " "the chip is there:\n"); - startchip = probe_flash(0, &flashes[0], 1); + /* This loop just counts compatible controllers. */ + for (j = 0; j < registered_programmer_count; j++) { + pgm = &registered_programmers[j]; + if (pgm->buses_supported & flashes[0].bustype) + compatible_programmers++; + } + if (compatible_programmers > 1) + printf("More than one compatible controller " + "found for the requested flash chip, " + "using the first one.\n"); + for (j = 0; j < registered_programmer_count; j++) { + pgm = &registered_programmers[j]; + startchip = probe_flash(pgm, 0, &flashes[0], 1); + if (startchip != -1) + break; + } if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); @@ -471,7 +487,6 @@ "contain garbage.\n"); return read_flash_to_file(&flashes[0], filename); } -#endif ret = 1; goto out_shutdown; } else if (!chip_to_probe) { -- http://www.hailfinger.org/

2 4

[commit] r1498 - trunk
by repository service Feb. 16, 2012

Feb. 16, 2012

Author: hailfinger Date: Thu Feb 16 22:00:27 2012 New Revision: 1498 URL: http://flashrom.org/trac/flashrom/changeset/1498 Log: Document and enable the linux_spi driver The linux_spi driver is now enabled by default on Linux. A man page entry and a line in --list-supported output have been added. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Makefile trunk/flashrom.8 trunk/print.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Feb 16 21:55:27 2012 (r1497) +++ trunk/Makefile Thu Feb 16 22:00:27 2012 (r1498) @@ -209,6 +209,14 @@ endif endif +ifneq ($(TARGET_OS), Linux) +ifeq ($(CONFIG_LINUX_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LINUX_SPI=yes +else +override CONFIG_LINUX_SPI = no +endif +endif + # Determine the destination processor architecture. # IMPORTANT: The following line must be placed before ARCH is ever used # (of course), but should come after any lines setting CC because the line @@ -324,16 +332,15 @@ # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATE_SPI ?= yes -# Disable Linux spidev interface support for now, until we check for a Linux -# device (not host, as DOS binaries for example are built on a Linux host). -CONFIG_LINUX_SPI ?= no - # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no # Always enable Marvell SATA controllers for now. CONFIG_SATAMV ?= yes +# Enable Linux spidev interface by default. We disable it on non-Linux targets. +CONFIG_LINUX_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -465,11 +472,6 @@ NEED_SERIAL := yes endif -ifeq ($(CONFIG_LINUX_SPI), yes) -FEATURE_CFLAGS += -D'CONFIG_LINUX_SPI=1' -PROGRAMMER_OBJS += linux_spi.o -endif - ifeq ($(CONFIG_DEDIPROG), yes) FEATURE_CFLAGS += -D'CONFIG_DEDIPROG=1' FEATURE_LIBS += -lusb @@ -482,6 +484,11 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_LINUX_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_LINUX_SPI=1' +PROGRAMMER_OBJS += linux_spi.o +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Feb 16 21:55:27 2012 (r1497) +++ trunk/flashrom.8 Thu Feb 16 22:00:27 2012 (r1498) @@ -205,6 +205,8 @@ .sp .BR "* ogp_spi" " (for SPI flash ROMs on Open Graphics Project graphics card)" .sp +.BR "* linux_spi" " (for SPI flash ROMs accessible via /dev/spidevX.Y on Linux)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -639,6 +641,17 @@ .sp More information about the hardware is available at .BR http://wiki.opengraphics.org . +.SS +.BR "linux_spi " programmer +You have to specify the SPI controller to use with the +.sp +.B " flashrom \-p linux_spi:dev=/dev/spidevX.Y" +.sp +syntax where +.B /dev/spidevX.Y +is the Linux device node for your SPI controller. +.sp +Please note that the linux_spi driver only works on Linux. .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Feb 16 21:55:27 2012 (r1497) +++ trunk/print.c Thu Feb 16 22:00:27 2012 (r1498) @@ -527,6 +527,11 @@ programmer_table[PROGRAMMER_SATAMV].name); print_supported_pcidevs(satas_mv); #endif +#if CONFIG_LINUX_SPI == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_LINUX_SPI].name); + msg_ginfo("Device files /dev/spidev*.*\n"); +#endif } #if CONFIG_INTERNAL == 1

1 0

Re: [flashrom] [PATCH] Manpage improvements.
by Carl-Daniel Hailfinger Feb. 16, 2012

Feb. 16, 2012

Am 16.02.2012 21:44 schrieb Stefan Tauner: > The sections describing the various options of the internal and dummy > programmers have grown out of proportions. This patch adds some headlines > to devide the unrelated topics a bit (with .TP commands). The previous indented > paragraphs for the various programmers were transformed to subsections (.SS). > > Also, rephrase the documention related to laptops completely to make it > less redundant and more informative. > Document the laptop=this_is_not_a_laptop internal programmer parameter > > Change the contact info in the bugs section by removing the trac > reference and adding IRC (and the pastebin) instead. > > Remove some superfluous white space. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1497 - trunk
by repository service Feb. 16, 2012

Feb. 16, 2012

Author: stefanct Date: Thu Feb 16 21:55:27 2012 New Revision: 1497 URL: http://flashrom.org/trac/flashrom/changeset/1497 Log: Manpage improvements. The sections describing the various options of the internal and dummy programmers have grown out of proportions. This patch adds some headlines to devide the unrelated topics a bit (with .TP commands). The previous indented paragraphs for the various programmers were transformed to subsections (.SS). Also, rephrase the documention related to laptops completely to make it less redundant and more informative. Document the laptop=this_is_not_a_laptop internal programmer parameter Change the contact info in the bugs section by removing the trac reference and adding IRC (and the pastebin) instead. Remove some superfluous white space and a .RE (restore indentation) command. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashrom.8 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Feb 16 21:31:25 2012 (r1496) +++ trunk/flashrom.8 Thu Feb 16 21:55:27 2012 (r1497) @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Jul 25, 2011" +.TH FLASHROM 8 "Feb 15, 2012" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -223,8 +223,11 @@ colon. While some programmers take arguments at fixed positions, other programmers use a key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a comma or a colon. -.TP +.SS .BR "internal " programmer +.TP +.B Board Enables +.sp Some mainboards require to run mainboard specific code to enable flash erase and write support (and probe support on old systems with parallel flash). The mainboard brand and model (if it requires specific code) is usually @@ -275,17 +278,22 @@ enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +.TP +.B Coreboot +.sp On systems running coreboot, flashrom checks whether the desired image matches your mainboard. This needs some special board ID to be present in the image. If flashrom detects that the image you want to write and the current board do not match, it will refuse to write the image unless you specify .sp .B " flashrom \-p internal:boardmismatch=force" +.TP +.B ITE IT87 Super I/O .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of -using the value provided by the BIOS, use the +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp @@ -295,6 +303,9 @@ flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +.TP +.B Intel chipsets +.sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named @@ -346,6 +357,8 @@ .sp Example: .B "flashrom \-p internal:fwh_idsel=0x001122334567" +.TP +.B Laptops .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -353,21 +366,31 @@ section). The embedded controller (EC) in these machines often interacts badly with flashing. .B http://www.flashrom.org/Laptops -has more information. If flash is shared with the EC, erase is guaranteed to -brick your laptop and write is very likely to brick your laptop. -Chip read and probe may irritate your EC and cause fan failure, backlight -failure, sudden poweroff, and other nasty effects. -flashrom will attempt to detect laptops and abort immediately for safety -reasons. -If you want to proceed anyway at your own risk, use +has more information. For example the EC firmware sometimes resides on the same +flash chip as the host firmware. While flashrom tries to change the contents of +that memory the EC might need to fetch new instructions or data from it and +could stop working correctly. Probing for and reading from the chip may also +irritate your EC and cause fan failure, backlight failure, sudden poweroff, and +other nasty effects. flashrom will attempt to detect if it is running on a +laptop and abort immediately for safety reasons if it clearly identifies the +host computer as one. If you want to proceed anyway at your own risk, use .sp .B " flashrom \-p internal:laptop=force_I_want_a_brick" .sp -You have been warned. -.sp We will not help you if you force flashing on a laptop because this is a really dumb idea. -.TP +.sp +You have been warned. +.sp +Currently we rely on the chassis type encoded in the DMI/SMBIOS data to detect +laptops. Some vendors did not implement those bits correctly or set them to +generic and/or dummy values. flashrom will then issue a warning and bail out +like above. In this case you can use +.sp +.B " flashrom \-p internal:laptop=this_is_not_a_laptop" +.sp +to tell flashrom (at your own risk) that it does not running on a laptop. +.SS .BR "dummy " programmer The dummy programmer operates on a buffer in memory only. It provides a safe and fast way to test various aspects of flashrom and is mainly used in @@ -409,6 +432,8 @@ .sp Example: .B "flashrom -p dummy:emulate=SST25VF040.REMS" +.TP +.B Persistent images .sp If you use flash chip emulation, flash image persistence is available as well by using the @@ -422,6 +447,8 @@ .sp Example: .B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.TP +.B SPI write chunk size .sp If you use SPI flash chip emulation for a chip which supports SPI page write with the default opcode, you can set the maximum allowed write chunk size with @@ -436,6 +463,8 @@ Example: .sp .B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" +.TP +.B SPI blacklist .sp To simulate a programmer which refuses to send certain SPI commands to the flash chip, you can specify a blacklist of SPI commands with the @@ -448,6 +477,9 @@ commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom will detect an error during command execution. .sp +.TP +.B SPI ignorelist +.sp To simulate a flash chip which ignores (doesn't support) certain SPI commands, you can specify an ignorelist of SPI commands with the .sp @@ -458,7 +490,7 @@ command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom won't detect an error during command execution. -.TP +.SS .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ " , " satamv" ", and " atahpt " programmers @@ -480,7 +512,7 @@ .sp Example: .B "flashrom \-p nic3com:pci=05:04.0" -.TP +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -501,7 +533,7 @@ .B 4232H and the default interface is .BR B . -.TP +.SS .BR "serprog " programmer A mandatory parameter specifies either a serial device/baud combination or an IP/port combination for communication with the @@ -517,7 +549,7 @@ instead. More information about serprog is available in .B serprog-protocol.txt in the source distribution. -.TP +.SS .BR "buspirate_spi " programmer A required .B dev @@ -533,7 +565,7 @@ can be .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M " or " 8M (in Hz). The default is the maximum frequency of 8 MHz. -.TP +.SS .BR "dediprog " programmer An optional .B voltage @@ -549,7 +581,7 @@ can be .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. -.TP +.SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use the optional @@ -579,9 +611,9 @@ .BR "http://rayer.ic.cz/elektro/spipgm.htm " . The schematic of the Xilinx DLC 5 was published at .BR "http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html " . -.TP +.SS .BR "ogp_spi " programmer -The flash ROM chip to access must be specified with the +The flash ROM chip to access must be specified with the .B rom parameter. .sp @@ -665,25 +697,37 @@ .B "/etc/rc.securelevel" and rebooting, or rebooting into single user mode. .SH BUGS -Please report any bugs at -.sp -.B " http://www.flashrom.org/trac/flashrom/newticket" -.sp -or on the flashrom mailing list at +Please report any bugs to the flashrom mailing list at .B "<flashrom(a)flashrom.org>" .sp We recommend to subscribe first at .sp .B " http://www.flashrom.org/mailman/listinfo/flashrom" .sp -Using flashrom on laptops is dangerous and may easily make your hardware -unusable unless you can desolder the flash chip and have a full flash chip -backup. This is caused by the embedded controller (EC) present in many laptops, -which interacts badly with any flash attempts. This is a hardware limitation -and flashrom will attempt to detect it and abort immediately for safety reasons. -.sp -More information about flashrom on laptops is available from +Many of the developers communicate via the +.B "#flashrom" +IRC channel on +.BR chat.freenode.net . +You are welcome to join and ask questions, send us bug and success reports there +too. Please provide a way to contact you later (e.g. a mail address) and be +patient if there is no immediate reaction. Also, we provide a pastebin service +at +.B http://paste.flashrom.org +that is very useful when you want to share logs etc. without spamming the +channel. +.SS +.B Laptops .sp +Using flashrom on laptops is dangerous and may easily make your hardware +unusable. flashrom will attempt to detect if it is running on a laptop and abort +immediately for safety reasons. Please see the detailed discussion of this topic +and associated flashrom options in the +.B Laptops +paragraph in the +.B internal programmer +subsection of the +.B PROGRAMMER SPECIFIC INFO +section. .B " http://www.flashrom.org/Laptops" .SS One-time programmable (OTP) memory and unique IDs @@ -697,7 +741,6 @@ .sp Similar to OTP memories are unique, factory programmed, unforgeable IDs. They are not modifiable by the user at all. -.RE .SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are

1 0

[PATCH] Manpage improvements.
by Stefan Tauner Feb. 16, 2012

Feb. 16, 2012

The sections describing the various options of the internal and dummy programmers have grown out of proportions. This patch adds some headlines to devide the unrelated topics a bit (with .TP commands). The previous indented paragraphs for the various programmers were transformed to subsections (.SS). Also, rephrase the documention related to laptops completely to make it less redundant and more informative. Document the laptop=this_is_not_a_laptop internal programmer parameter Change the contact info in the bugs section by removing the trac reference and adding IRC (and the pastebin) instead. Remove some superfluous white space. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 111 +++++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 77 insertions(+), 34 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index 76aacba..782f30b 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Jul 25, 2011" +.TH FLASHROM 8 "Feb 15, 2012" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -223,8 +223,11 @@ parameters. These parameters are separated from the programmer name by a colon. While some programmers take arguments at fixed positions, other programmers use a key/value interface in which the key and value is separated by an equal sign and different pairs are separated by a comma or a colon. -.TP +.SS .BR "internal " programmer +.TP +.B Board Enables +.sp Some mainboards require to run mainboard specific code to enable flash erase and write support (and probe support on old systems with parallel flash). The mainboard brand and model (if it requires specific code) is usually @@ -275,17 +278,22 @@ has been written because it is known that writing/erasing without the board enable is going to fail. In any case (success or failure), please report to the flashrom mailing list, see below. .sp +.TP +.B Coreboot +.sp On systems running coreboot, flashrom checks whether the desired image matches your mainboard. This needs some special board ID to be present in the image. If flashrom detects that the image you want to write and the current board do not match, it will refuse to write the image unless you specify .sp .B " flashrom \-p internal:boardmismatch=force" +.TP +.B ITE IT87 Super I/O .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus translation, flashrom should autodetect that configuration. If you want to set the I/O base port of the IT87 series SPI controller manually instead of -using the value provided by the BIOS, use the +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp @@ -295,6 +303,9 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +.TP +.B Intel chipsets +.sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash attached, and if a valid descriptor was written to it (e.g. by the vendor), the chipset provides an alternative way to access the flash chip(s) named @@ -346,6 +357,8 @@ settings. The default value for ICH7 is given in the example below. .sp Example: .B "flashrom \-p internal:fwh_idsel=0x001122334567" +.TP +.B Laptops .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -353,21 +366,31 @@ unusable (see also the section). The embedded controller (EC) in these machines often interacts badly with flashing. .B http://www.flashrom.org/Laptops -has more information. If flash is shared with the EC, erase is guaranteed to -brick your laptop and write is very likely to brick your laptop. -Chip read and probe may irritate your EC and cause fan failure, backlight -failure, sudden poweroff, and other nasty effects. -flashrom will attempt to detect laptops and abort immediately for safety -reasons. -If you want to proceed anyway at your own risk, use +has more information. For example the EC firmware sometimes resides on the same +flash chip as the host firmware. While flashrom tries to change the contents of +that memory the EC might need to fetch new instructions or data from it and +could stop working correctly. Probing for and reading from the chip may also +irritate your EC and cause fan failure, backlight failure, sudden poweroff, and +other nasty effects. flashrom will attempt to detect if it is running on a +laptop and abort immediately for safety reasons if it clearly identifies the +host computer as one. If you want to proceed anyway at your own risk, use .sp .B " flashrom \-p internal:laptop=force_I_want_a_brick" .sp -You have been warned. -.sp We will not help you if you force flashing on a laptop because this is a really dumb idea. -.TP +.sp +You have been warned. +.sp +Currently we rely on the chassis type encoded in the DMI/SMBIOS data to detect +laptops. Some vendors did not implement those bits correctly or set them to +generic and/or dummy values. flashrom will then issue a warning and bail out +like above. In this case you can use +.sp +.B " flashrom \-p internal:laptop=this_is_not_a_laptop" +.sp +to tell flashrom (at your own risk) that it does not running on a laptop. +.SS .BR "dummy " programmer The dummy programmer operates on a buffer in memory only. It provides a safe and fast way to test various aspects of flashrom and is mainly used in @@ -409,6 +432,8 @@ vendor): .sp Example: .B "flashrom -p dummy:emulate=SST25VF040.REMS" +.TP +.B Persistent images .sp If you use flash chip emulation, flash image persistence is available as well by using the @@ -422,6 +447,8 @@ where the chip contents on flashrom shutdown are written to. .sp Example: .B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.TP +.B SPI write chunk size .sp If you use SPI flash chip emulation for a chip which supports SPI page write with the default opcode, you can set the maximum allowed write chunk size with @@ -436,6 +463,8 @@ is the number of bytes (min. 1, max. 256). Example: .sp .B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" +.TP +.B SPI blacklist .sp To simulate a programmer which refuses to send certain SPI commands to the flash chip, you can specify a blacklist of SPI commands with the @@ -448,6 +477,9 @@ controller refuses to run command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom will detect an error during command execution. .sp +.TP +.B SPI ignorelist +.sp To simulate a flash chip which ignores (doesn't support) certain SPI commands, you can specify an ignorelist of SPI commands with the .sp @@ -458,7 +490,7 @@ SPI commands. If commandlist is e.g. 0302, the emulated flash chip will ignore command 0x03 (READ) and command 0x02 (WRITE). commandlist may be up to 512 characters (256 commands) long. Implementation note: flashrom won't detect an error during command execution. -.TP +.SS .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ " , " satamv" ", and " atahpt " programmers @@ -480,7 +512,7 @@ is the PCI function number of the desired device. .sp Example: .B "flashrom \-p nic3com:pci=05:04.0" -.TP +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -501,7 +533,7 @@ The default model is .B 4232H and the default interface is .BR B . -.TP +.SS .BR "serprog " programmer A mandatory parameter specifies either a serial device/baud combination or an IP/port combination for communication with the @@ -517,7 +549,7 @@ syntax and for IP, you have to use instead. More information about serprog is available in .B serprog-protocol.txt in the source distribution. -.TP +.SS .BR "buspirate_spi " programmer A required .B dev @@ -533,7 +565,7 @@ where can be .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M " or " 8M (in Hz). The default is the maximum frequency of 8 MHz. -.TP +.SS .BR "dediprog " programmer An optional .B voltage @@ -549,7 +581,7 @@ where can be .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. -.TP +.SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use the optional @@ -579,9 +611,9 @@ More information about the RayeR hardware is available at .BR "http://rayer.ic.cz/elektro/spipgm.htm " . The schematic of the Xilinx DLC 5 was published at .BR "http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html " . -.TP +.SS .BR "ogp_spi " programmer -The flash ROM chip to access must be specified with the +The flash ROM chip to access must be specified with the .B rom parameter. .sp @@ -665,25 +697,37 @@ in .B "/etc/rc.securelevel" and rebooting, or rebooting into single user mode. .SH BUGS -Please report any bugs at -.sp -.B " http://www.flashrom.org/trac/flashrom/newticket" -.sp -or on the flashrom mailing list at +Please report any bugs to the flashrom mailing list at .B "<flashrom(a)flashrom.org>" .sp We recommend to subscribe first at .sp .B " http://www.flashrom.org/mailman/listinfo/flashrom" .sp -Using flashrom on laptops is dangerous and may easily make your hardware -unusable unless you can desolder the flash chip and have a full flash chip -backup. This is caused by the embedded controller (EC) present in many laptops, -which interacts badly with any flash attempts. This is a hardware limitation -and flashrom will attempt to detect it and abort immediately for safety reasons. -.sp -More information about flashrom on laptops is available from +Many of the developers communicate via the +.B "#flashrom" +IRC channel on +.BR chat.freenode.net . +You are welcome to join and ask questions, send us bug and success reports there +too. Please provide a way to contact you later (e.g. a mail address) and be +patient if there is no immediate reaction. Also, we provide a pastebin service +at +.B http://paste.flashrom.org +that is very useful when you want to share logs etc. without spamming the +channel. +.SS +.B Laptops .sp +Using flashrom on laptops is dangerous and may easily make your hardware +unusable. flashrom will attempt to detect if it is running on a laptop and abort +immediately for safety reasons. Please see the detailed discussion of this topic +and associated flashrom options in the +.B Laptops +paragraph in the +.B internal programmer +subsection of the +.B PROGRAMMER SPECIFIC INFO +section. .B " http://www.flashrom.org/Laptops" .SS One-time programmable (OTP) memory and unique IDs @@ -697,7 +741,6 @@ printed when they are detected. .sp Similar to OTP memories are unique, factory programmed, unforgeable IDs. They are not modifiable by the user at all. -.RE .SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are -- 1.7.1

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