This file is saturated with superfluous ifdefs arranged into
several nested levels. This in turn adds additional complexity
to process of adding another architecture.
I re-arranged all ifdef blocks and killed duplicated function
definitions. Also I added define(__amd64) to the list of x86-arches.
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
hwaccess.c | 85 +++++++++++++++++++++--------------------------------------
1 files changed, 30 insertions(+), 55 deletions(-)
diff …
[View More]--git a/hwaccess.c b/hwaccess.c
index 3a61e60..4e87642 100644
--- a/hwaccess.c
+++ b/hwaccess.c
@@ -29,30 +29,47 @@
#endif
#include "flash.h"
+#if !( defined(__i386__) || \
+ defined(__x86_64__) || defined(__amd64) || \
+ defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \
+ defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__))
+#error Unknown architecture
+#endif
+
#if defined(__i386__) || defined(__x86_64__)
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+int io_fd;
+#endif
+#endif
-/* sync primitive is not needed because x86 uses uncached accesses
- * which have a strongly ordered memory model.
- */
static inline void sync_primitive(void)
{
-}
-
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-int io_fd;
+/* sync primitive is needed only on PowerPC because
+ * x86 uses uncached accesses which have a strongly ordered memory model
+ * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model.
+ */
+#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+ /* Prevent reordering and/or merging of reads/writes to hardware.
+ * Such reordering and/or merging would break device accesses which
+ * depend on the exact access order.
+ */
+ asm("eieio" : : : "memory");
#endif
+}
void get_io_perms(void)
{
+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
#if defined(__DJGPP__)
/* We have full permissions by default. */
return;
#else
-#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#if defined (__sun)
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
#elif defined(__FreeBSD__) || defined (__DragonFly__)
if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
-#else
+#else
if (iopl(3) != 0) {
#endif
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
@@ -65,60 +82,18 @@ void get_io_perms(void)
exit(1);
}
#endif
+#endif
}
void release_io_perms(void)
{
+/* PCI port I/O is not yet implemented on PowerPC or MIPS. */
+#if defined(__i386__) || defined(__x86_64__) || defined(__amd64)
#if defined(__FreeBSD__) || defined(__DragonFly__)
close(io_fd);
#endif
-}
-
-#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
-
-static inline void sync_primitive(void)
-{
- /* Prevent reordering and/or merging of reads/writes to hardware.
- * Such reordering and/or merging would break device accesses which
- * depend on the exact access order.
- */
- asm("eieio" : : : "memory");
-}
-
-/* PCI port I/O is not yet implemented on PowerPC. */
-void get_io_perms(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on PowerPC. */
-void release_io_perms(void)
-{
-}
-
-#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
-
-/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
- * in mode 2 which has a strongly ordered memory model.
- */
-static inline void sync_primitive(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on MIPS. */
-void get_io_perms(void)
-{
-}
-
-/* PCI port I/O is not yet implemented on MIPS. */
-void release_io_perms(void)
-{
-}
-
-#else
-
-#error Unknown architecture
-
#endif
+}
void mmio_writeb(uint8_t val, void *addr)
{
--
1.7.2.3
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On 5/23/11 4:23 PM, Stefan Tauner wrote:
> Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at>
> ---
> chipset_enable.c | 12 +++++++++++-
> 1 files changed, 11 insertions(+), 1 deletions(-)
>
> diff --git a/chipset_enable.c b/chipset_enable.c
> index 83b49ad..339c6bb 100644
> --- a/chipset_enable.c
> +++ b/chipset_enable.c
> @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name,
> (old& (1…
[View More]<< 0)) ? "en" : "dis");
> msg_pdbg("BIOS_CNTL is 0x%x\n", old);
>
> - new = old | 1;
> + /*
> + * Quote from the 6 Series datasheet:
> + * "5: SMM BIOS Write Protect Disable (SMM_BWP)
> + * 1 = BIOS region SMM protection is enabled.
> + * The BIOS Region is not writable unless all processors are in SMM."
> + * In earlier chipsets this bit is reserved. */
> + if (old& (5<< 1)) {
> + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");
> + return -1;
You might still be successful doing the write, in case the SMM handler
does not enforce the protection, so maybe you should just print a
warning but not return here?
> + }
>
> + new = old | 1;
> if (new == old)
> return 0;
>
[View Less]
AT49F010 patch is basically a copy of the existing AT49F020 code, but
with half the size and the correct ID.
The log was from a write of random data, after the chip already
contained different random data. I did separate read, erase, write tests
before but this log seems to show that PREW all work.
CAT28F512 I have successfully probed and read data from, but erase
fails. Could be because it needs 12v VPP. The CAT28F512 I have is
soldered on to a NIC. I haven't investigated if VPP is …
[View More]connected at all
yet. Thought I'd include the patch as-is anyway.
Both patches:
Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com>
--
Andrew.
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Enable writing/erasing on the ASUS P4P800-X, tested by mindcat on IRC.
This board enable is inspired by the board enable for the ASUS P4P800-VM.
As a bonus, testin the erasing/writing functionality on the SST
SST49LF003A/B chip is now known to work.
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
Before (r1205/v0.9.3):
Write report: http://paste.flashrom.org/view.php?id=465
Write report: http://paste.flashrom.org/view.php?id=466
After (r1285):
Erase report: http://paste.flashrom.org/view.php?id=467
Am 20.06.2011 01:13 schrieb Michael Karcher:
> The currently unreferenced function in sharplhf00l04.c does a standard
> FWH block protection reset (writes 0 to the protection register) and a
> standard FWH block erase.
>
> The locking blocks of the FWH block lock cover 128KB areas, and thats
> the only thing page_size is used for in the functions referenced in the
> LHF00L04 entry.
>
My datasheet talks about 8 kB sectors and 64 kB blocks in "Figure 3.
Memory Map", …
[View More]but "Table 8. FWH Flash Registers Configuration Map" only
mentions registers for the 8 kB sectors in the top 64 kB block
explicitly. "Table 8" also mentions "XX002H Whole Block Lock Register"
as generic placeholder, and AFAICS those two X mean you have one block
lock register for each of the 15 bottom 64 kB blocks and one for each of
the 8 top 8 kB sectors. That also means the 82802ab unlocking as is
can't be used.
I was unable to find any 128 kB reference in my datasheet, so I'm going
to Nack that part.
> Finally, this adds a comment that there are non-volatile (flash memory)
> lock bits for 8 sectors in the last 64KB. They are write-only and clearable
> at once. Readback seems unsupported.
>
I have a slightly different interpretation of the datasheet (see above),
so I'm not sure how to proceed.
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
>
Killing sharplhf00l04.c is a good thing, though, so that part is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
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