flashrom August 2011

flashrom@flashrom.org

42 participants
219 discussions

[PATCH] Add a bunch of new/tested stuff and various small changes 7
by Stefan Tauner 01 Sep '11

01 Sep '11

- add Asus Crosshair IV Extreme to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007640.html - add P7H55-M LX to the list of supported boards although flashrom works correctly, it is marked as not ok, because flashing the vendor image will break the LAN interface. - add GA-X58A-UD7 to the list of supported boards http://paste.flashrom.org/view.php?id=739 - add Asus P4P800-VM to print.c (has a working board enable) - add Asus K8V-X to print.c reported by florz http://paste.flashrom.org/view.php?id=742 - add Intel D865GLC to print.c reported by jmd on IRC http://paste.flashrom.org/view.php?id=775 - add ECS P4M800PRO-M (V1.0A) to the list of supported boards reported by dweg on IRC (hot flashed a SST49LF040B, original was W39V040B) - add X8DTU-6TF+ to print.c (needs ME unlocking) http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - add Shuttle FH67 (used in the SH67H3 barebone) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add Tyan S2912 to the list of supported boards reported by erlan on IRC - add Zotac GeForce 8200 to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html - mark AT25DF321A as TEST_OK_PROBE http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - mark 28F001BN/BX-T as TEST_OK_PR http://www.flashrom.org/pipermail/flashrom/2011-July/007208.html - rename MX29F002 http://patchwork.coreboot.org/patch/2794/ - mark SST39SF040 as fully tested reported by Florian 'florz' Zumbiehl http://paste.flashrom.org/view.php?id=742 - mark SST49LF040B as fully tested reported by dweg on IRC and later by Armin on the ml: http://www.flashrom.org/pipermail/flashrom/2011-August/007764.html - mark H55 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html - mark H67 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add preliminary X79 (patsburg) PCI IDs 0x1d40 was reported already as working (not archived in our pipermail?) - mark "82557/8/9/0/1 Ethernet Pro 100" in nicintel.c as working http://www.flashrom.org/pipermail/flashrom/2011-August/007480.html - rename some chips that had gratuitous "probing" suffixes: - SST25VF010.REMS - SST25VF040.REMS - M25P05.RES - M25P10.RES - remove unneeded nicintel_spi-related function declarations in programmer.h - typos and whitespace fixes - fix Asus P4P800-E Deluxe detection The original board enable was added before DMI matching and used the IDs of a Promise controller as secondary PCI ID set. The controller could be disabled in the BIOS which would make the board not match. This patch uses the SMBUS controller instead and adds a DMI pattern. This was Tested-by: Michael Schneider <vdrportal_midas at gmx dot de> - add "Sealed-case PC" to the list of chassis type (as indicating "not a laptop") This is Acked-by: Idwer Vollering <vidwer(a)gmail.com> the fix for the typo unusued -> unused is Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- I think this is (more than) big enough to be committed. If no one vetoes i will commit it friday evening. board_enable.c | 2 +- chipset_enable.c | 12 +++++++----- dmi.c | 1 + flashchips.c | 24 ++++++++++++------------ flashchips.h | 8 ++++---- nicintel.c | 2 +- print.c | 11 +++++++++++ programmer.h | 3 --- 8 files changed, 37 insertions(+), 26 deletions(-) diff --git a/board_enable.c b/board_enable.c index 72f4cfe..896ab40 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2018,7 +2018,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index 336ad2e..ce00324 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -327,7 +327,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) } if (fwh_idsel & 0xffff000000000000ULL) { msg_perr("Error: fwh_idsel= specified, but value had " - "unusued bits set.\n"); + "unused bits set.\n"); goto idsel_garbage_out; } fwh_idsel_old = pci_read_long(dev, 0xd0); @@ -341,7 +341,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); -idsel_garbage_out: +idsel_garbage_out: free(idsel); /* FIXME: Return failure here once internal_init() starts * to care about the return value of the chipset enable. @@ -846,7 +846,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) if (new != old) { rpci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - msg_pinfo("Setting register to set 0x%x to 0x%x on %s " + msg_pinfo("Setting register to 0x%x to 0x%x on %s " "failed (WARNING ONLY).\n", 0x88, new, name); } } @@ -1196,7 +1196,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6}, {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, - {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6}, {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, @@ -1207,6 +1207,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, + {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ + {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, @@ -1249,7 +1251,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, - {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5}, {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, diff --git a/dmi.c b/dmi.c index 8f78376..5f64b94 100644 --- a/dmi.c +++ b/dmi.c @@ -81,6 +81,7 @@ static const struct { {0x0e, 1, "Sub Notebook"}, {0x11, 0, "Main Server Chassis"}, {0x17, 0, "Rack Mount Chassis"}, + {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ }; #define DMI_COMMAND_LEN_MAX 260 diff --git a/flashchips.c b/flashchips.c index 7e7f47d..5ee8210 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1544,7 +1544,7 @@ const struct flashchip flashchips[] = { .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3768,13 +3768,13 @@ const struct flashchip flashchips[] = { .model_id = INTEL_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {112 * 1024, 1}, {4 * 1024, 2}, {8 * 1024, 1}, @@ -4488,7 +4488,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002B", + .name = "MX29F002(N)B", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002B, @@ -4520,7 +4520,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002T", + .name = "MX29F002(N)T", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002T, @@ -5637,7 +5637,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF010.REMS", + .name = "SST25VF010", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF010_REMS, @@ -5775,7 +5775,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF040.REMS", + .name = "SST25VF040", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF040_REMS, @@ -6125,7 +6125,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -6610,7 +6610,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -6729,7 +6729,7 @@ const struct flashchip flashchips[] = { */ { .vendor = "ST", - .name = "M25P05.RES", + .name = "M25P05", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P05_RES, @@ -6784,7 +6784,7 @@ const struct flashchip flashchips[] = { /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", - .name = "M25P10.RES", + .name = "M25P10", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P10_RES, @@ -6837,7 +6837,7 @@ const struct flashchip flashchips[] = { }, { - .vendor = "ST", + .vendor = "ST", /* Numonyx */ .name = "M25P40", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index ff49d31..e8b46ad 100644 --- a/flashchips.h +++ b/flashchips.h @@ -369,8 +369,8 @@ #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ #define MACRONIX_MX29F004B 0x46 #define MACRONIX_MX29F004T 0x45 #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ @@ -474,7 +474,7 @@ #define SST_SST25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ #define SST_SST25VF040B 0x258D #define SST_SST25VF040B_REMS 0x8D /* REMS or RES opcode */ -#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode, same as SST25LF080A */ #define SST_SST25VF080B 0x258E #define SST_SST25VF080B_REMS 0x8E /* REMS or RES opcode */ #define SST_SST25VF016B 0x2541 @@ -526,7 +526,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 diff --git a/nicintel.c b/nicintel.c index 5410523..f94cbc9 100644 --- a/nicintel.c +++ b/nicintel.c @@ -28,7 +28,7 @@ uint8_t *nicintel_control_bar; const struct pcidev_status nics_intel[] = { {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, - {PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, + {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, {}, }; diff --git a/print.c b/print.c index f0bd477..66eb144 100644 --- a/print.c +++ b/print.c @@ -431,9 +431,11 @@ const struct board_info boards_known[] = { B("ASUS", "A8V Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU", NULL), B("ASUS", "A8V-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh", NULL), B("ASUS", "A8V-E SE", 1, "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"), + B("ASUS", "Crosshair IV Extreme", 1, "http://www.asus.com/product.aspx?P_ID=lt1ShF6xEn3rlLe7", NULL), B("ASUS", "E35M1-I DELUXE", 1, "http://www.asus.com/product.aspx?P_ID=9BmKhMwWCwqyl1lz", NULL), B("ASUS", "K8V", 1, "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm", NULL), B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o", NULL), + B("ASUS", "K8V-X", 1, NULL, NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr", NULL), B("ASUS", "M2A-MX", 1, "http://www.asus.com/product.aspx?P_ID=BmaOnPewi1JgltOZ", NULL), B("ASUS", "M2A-VM", 1, "http://www.asus.com/product.aspx?P_ID=St3pWpym8xXpROQS", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html"), @@ -469,6 +471,7 @@ const struct board_info boards_known[] = { B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL), B("ASUS", "P4P800", 1, "http://www.asus.com/product.aspx?P_ID=DYt1Et9MlBChqzLb", NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), + B("ASUS", "P4P800-VM", 1, NULL, NULL), B("ASUS", "P4SC-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4sc-e/", "Part of ASUS Terminator P4 533 barebone system"), B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505", NULL), B("ASUS", "P4S533-X", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4s533-x/", NULL), @@ -496,6 +499,7 @@ const struct board_info boards_known[] = { B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ", NULL), B("ASUS", "P6T Deluxe V2", 1, "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx", NULL), B("ASUS", "P7H57D-V EVO", 1, "http://www.asus.com/Motherboards/Intel_Socket_1156/P7H57DV_EVO/", NULL), + B("ASUS", "P7H55-M LX", 0, NULL, "flashrom works correctly, but GbE LAN is nonworking (probably due to a missing/bogus MAC address; see http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html and http://ubuntuforums.org/showthread.php?t=1534389 for a possible workaround)"), B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/product.aspx?P_ID=k81cpN8uEB01BpQ6", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), B("Biostar", "M6TBA", 0, "ftp://ftp.biostar-usa.com/manuals/M6TBA/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -512,6 +516,7 @@ const struct board_info boards_known[] = { B("Elitegroup", "K7S5A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…", NULL), B("Elitegroup", "K7S6A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…", NULL), B("Elitegroup", "K7VTA3", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…", NULL), + B("Elitegroup", "P4M800PRO-M (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6IWP-Fe", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6VAP-A+", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…", NULL), B("Elitegroup", "RS485M-M", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), @@ -567,6 +572,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), + B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", 1, NULL, NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), @@ -579,6 +585,7 @@ const struct board_info boards_known[] = { B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), B("Intel", "D201GLY", 1, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL), + B("Intel", "D865GLC", 0, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775"), B("Intel", "DG45ID", 0, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.h…", "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "EP80759", 1, NULL, NULL), B("Intel", "Foxhollow", 1, NULL, "Intel reference board."), @@ -647,6 +654,7 @@ const struct board_info boards_known[] = { B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", 1, NULL, NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL), + B("Shuttle", "FH67", 1, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/", NULL), B("Shuttle", "FN25", 1, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL), B("Shuttle", "X50/X50(B)", 1, "http://au.shuttle.com/product_detail_spec.jsp?PI=1241", NULL), B("Soyo", "SY-5VD", 0, "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -664,6 +672,7 @@ const struct board_info boards_known[] = { B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTU-6TF+", 0, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU_.cfm?TYP=SAS&…", "Probing works (Atmel AT25DF321A, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), @@ -683,6 +692,7 @@ const struct board_info boards_known[] = { B("Tyan", "S2891 (Thunder K8SRE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=144", NULL), B("Tyan", "S2892 (Thunder K8SE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=145", NULL), B("Tyan", "S2895 (Thunder K8WE)", 1, "http://www.tyan.com/archive/products/html/thunderk8we.html", NULL), + B("Tyan", "S2912 (Thunder n3600R)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=157", NULL), B("Tyan", "S2915 (Thunder n6650W)", 1, "http://tyan.com/product_board_detail.aspx?pid=163", NULL), B("Tyan", "S2915-E (Thunder n6650W)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=541&SKU=600000041", NULL), B("Tyan", "S2933 (Thunder n3600S)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=478&SKU=600000063", NULL), @@ -712,6 +722,7 @@ const struct board_info boards_known[] = { B("VIA", "pc2500e", 1, "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp", NULL), B("VIA", "PC3500G", 1, "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp", NULL), B("VIA", "VB700X", 1, "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL), + B("ZOTAC", "GeForce 8200", 1, "http://pden.zotac.com/index.php?page=shop.product_details&product_id=129&ca…", NULL), B("ZOTAC", "ZBOX HD-ID11", 1, "http://pdde.zotac.com/index.php?page=shop.product_details&product_id=240&ca…", NULL), #endif diff --git a/programmer.h b/programmer.h index 6a28dbe..70f3c09 100644 --- a/programmer.h +++ b/programmer.h @@ -424,9 +424,6 @@ extern const struct pcidev_status nics_intel[]; /* nicintel_spi.c */ #if CONFIG_NICINTEL_SPI == 1 int nicintel_spi_init(void); -int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr); extern const struct pcidev_status nics_intel_spi[]; #endif -- 1.7.1

1 0

Tested writing vendor bios on asus m2n-e
by Armin Preiml 01 Sep '11

01 Sep '11

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hello flashrom team I've tested writing the latest vendor bios (5001) on the asus m2n-e board. The log is attached. best regards - -- Armin Preiml Student of Computer Science -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iF4EAREIAAYFAk5egjcACgkQxbiSTpmfomFoHwD/T53aesUpjjiCkv6usPYD7PEa Gef+JILXJm3LGqmDBB4A/RFUaOFSYLKA3VhubY+9dJXsF6ocHk6smjh9fwZh/VJl =XN9F -----END PGP SIGNATURE-----

2 1

[PATCH] Revert parts of r1397
by Carl-Daniel Hailfinger 31 Aug '11

31 Aug '11

Hi, the whitespace and coding-style fixes in r1397 changed a few places which should have been left untouched or changed differently for various reasons: - Mixing uninitialized and initialized local variables leads to confusion. - ft2232_spi error cases should have gotten some error handling, and that's the reason the curly braces were there. - Depending on whom you ask about the C99 standard, a comma after the last element of an array initializer will cause another empty array element to be allocated, and that increases array size by 1 and may break some code which assumes certain fields to be nonzero. - Sometimes the introduced linebreaks look worse than before. - Fixing typos/wording in some places would have been nice given that those places were touched anyway. - If we insist on spelling "ASUS" all uppercase because the vendor said so, we have to spell "LPC Bridge" with an uppercase B because the datasheet said so. - #if/#else/#endif are sometimes hard to follow, and a comment at the #endif can improve readability a lot. Comments welcome. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-revert_r1397_partially/it87spi.c =================================================================== --- flashrom-revert_r1397_partially/it87spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/it87spi.c (Arbeitskopie) @@ -203,7 +203,8 @@ int init_superio_ite(void) { - int i, ret = 0; + int i; + int ret = 0; for (i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_ITE) Index: flashrom-revert_r1397_partially/cli_classic.c =================================================================== --- flashrom-revert_r1397_partially/cli_classic.c (Revision 1402) +++ flashrom-revert_r1397_partially/cli_classic.c (Arbeitskopie) @@ -104,13 +104,14 @@ struct flashchip flashes[3]; struct flashchip *fill_flash; const char *name; - int startchip = 0, chipcount = 0, namelen, opt, option_index = 0; - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int dont_verify_it = 0, list_supported = 0, force = 0; + int namelen, opt, i; + int startchip = 0, chipcount = 0, option_index = 0, force = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int operation_specified = 0, i, ret = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int dont_verify_it = 0, list_supported = 0, operation_specified = 0; + int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; static const struct option long_options[] = { Index: flashrom-revert_r1397_partially/dmi.c =================================================================== --- flashrom-revert_r1397_partially/dmi.c (Revision 1402) +++ flashrom-revert_r1397_partially/dmi.c (Arbeitskopie) @@ -196,7 +196,8 @@ */ static int dmi_compare(const char *value, const char *pattern) { - int anchored = 0, patternlen; + int anchored = 0; + int patternlen; msg_pspew("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ Index: flashrom-revert_r1397_partially/dediprog.c =================================================================== --- flashrom-revert_r1397_partially/dediprog.c (Revision 1402) +++ flashrom-revert_r1397_partially/dediprog.c (Arbeitskopie) @@ -496,7 +496,8 @@ static int parse_voltage(char *voltage) { char *tmp = NULL; - int i, millivolt, fraction = 0; + int i; + int millivolt = 0, fraction = 0; if (!voltage || !strlen(voltage)) { msg_perr("Empty voltage= specified.\n"); @@ -574,7 +575,8 @@ { struct usb_device *dev; char *voltage; - int millivolt = 3500, ret; + int millivolt = 3500; + int ret; msg_pspew("%s\n", __func__); Index: flashrom-revert_r1397_partially/it85spi.c =================================================================== --- flashrom-revert_r1397_partially/it85spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/it85spi.c (Arbeitskopie) @@ -84,15 +84,15 @@ static int it85xx_scratch_rom_reenter = 0; /* This function will poll the keyboard status register until either - * an expected value shows up, or - * timeout reaches. + * an expected value shows up, or the timeout is reached. + * timeout is in usec. * - * Returns: 0 -- the expected value has shown. - * 1 -- timeout reached. + * Returns: 0 -- the expected value showed up. + * 1 -- timeout. */ static int wait_for(const unsigned int mask, const unsigned int expected_value, - const int timeout /* in usec */, const char *error_message, - const char *function_name, const int lineno) + const int timeout, const char * error_message, + const char * function_name, const int lineno) { int time_passed; @@ -317,8 +317,9 @@ int i; it85xx_enter_scratch_rom(); - /* exit scratch ROM ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt EC. */ + /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt the EC. + */ #ifdef LPC_IO INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); Index: flashrom-revert_r1397_partially/buspirate_spi.c =================================================================== --- flashrom-revert_r1397_partially/buspirate_spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/buspirate_spi.c (Arbeitskopie) @@ -109,7 +109,7 @@ {"2.6M", 0x5}, {"4M", 0x6}, {"8M", 0x7}, - {NULL, 0x0}, + {NULL, 0x0} }; static int buspirate_spi_shutdown(void *data) @@ -150,9 +150,11 @@ int buspirate_spi_init(void) { unsigned char buf[512]; - int ret = 0, i, spispeed = 0x7; char *dev = NULL; char *speed = NULL; + int spispeed = 0x7; + int ret = 0; + int i; dev = extract_programmer_param("dev"); if (!dev || !strlen(dev)) { Index: flashrom-revert_r1397_partially/physmap.c =================================================================== --- flashrom-revert_r1397_partially/physmap.c (Revision 1402) +++ flashrom-revert_r1397_partially/physmap.c (Arbeitskopie) @@ -76,7 +76,7 @@ mi.address = phys_addr; mi.size = len; - ret = __dpmi_physical_address_mapping (&mi); + ret = __dpmi_physical_address_mapping(&mi); if (ret != 0) return ERROR_PTR; Index: flashrom-revert_r1397_partially/ft2232_spi.c =================================================================== --- flashrom-revert_r1397_partially/ft2232_spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/ft2232_spi.c (Arbeitskopie) @@ -246,17 +246,21 @@ ftdic->error_str); } - if (ftdi_usb_reset(ftdic) < 0) + if (ftdi_usb_reset(ftdic) < 0) { msg_perr("Unable to reset FTDI device\n"); + } - if (ftdi_set_latency_timer(ftdic, 2) < 0) + if (ftdi_set_latency_timer(ftdic, 2) < 0) { msg_perr("Unable to set latency timer\n"); + } - if (ftdi_write_data_set_chunksize(ftdic, 256)) + if (ftdi_write_data_set_chunksize(ftdic, 256)) { msg_perr("Unable to set chunk size\n"); + } - if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { msg_perr("Unable to set bitmode to SPI\n"); + } if (clock_5x) { msg_pdbg("Disable divide-by-5 front stage\n"); @@ -323,7 +327,8 @@ struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0, bufsize; + int i = 0, ret = 0, failed = 0; + int bufsize; static int oldbufsize = 0; if (writecnt > 65536 || readcnt > 65536) Index: flashrom-revert_r1397_partially/chipset_enable.c =================================================================== --- flashrom-revert_r1397_partially/chipset_enable.c (Revision 1402) +++ flashrom-revert_r1397_partially/chipset_enable.c (Arbeitskopie) @@ -309,8 +309,9 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { uint32_t fwh_conf; + int i, tmp; char *idsel = NULL; - int i, tmp, max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; + int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; idsel = extract_programmer_param("fwh_idsel"); @@ -1028,8 +1029,8 @@ flashbase = parx << 12; } } else { - msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. " - "Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming " + "flash at 4G.\n"); } /* 4. Clean up */ Index: flashrom-revert_r1397_partially/flashrom.c =================================================================== --- flashrom-revert_r1397_partially/flashrom.c (Revision 1402) +++ flashrom-revert_r1397_partially/flashrom.c (Arbeitskopie) @@ -600,8 +600,7 @@ size_t size = flash->total_size * 1024; /* Flash registers live 4 MByte below the flash. */ /* FIXME: This is incorrect for nonstandard flashbase. */ - flash->virtual_registers = (chipaddr)programmer_map_flash_region( - "flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); + flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) @@ -753,8 +752,9 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message) { - int i, ret = 0, failcount = 0; + int i; uint8_t *readbuf = malloc(len); + int ret = 0, failcount = 0; if (!len) goto out_free; @@ -832,7 +832,8 @@ */ int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran) { - int result = 0, i, j, limit; + int result = 0; + int i, j, limit; switch (gran) { case write_gran_1bit: @@ -898,7 +899,8 @@ static int get_next_write(uint8_t *have, uint8_t *want, int len, int *first_start, enum write_granularity gran) { - int need_write = 0, rel_start = 0, first_len = 0, i, limit, stride; + int need_write = 0, rel_start = 0, first_len = 0; + int i, limit, stride; switch (gran) { case write_gran_1bit: @@ -1326,7 +1328,8 @@ */ static int selfcheck_eraseblocks(const struct flashchip *flash) { - int i, j, k, ret = 0; + int i, j, k; + int ret = 0; for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; @@ -1451,7 +1454,8 @@ void *param1, void *param2) { int i, j; - unsigned int start = 0, len; + unsigned int start = 0; + unsigned int len; struct block_eraser eraser = flash->block_erasers[erasefunction]; for (i = 0; i < NUM_ERASEREGIONS; i++) { @@ -1603,8 +1607,10 @@ void list_programmers_linebreak(int startcol, int cols, int paren) { const char *pname; - int pnamelen, remaining = 0, firstline = 1, i; + int pnamelen; + int remaining = 0, firstline = 1; enum programmer p; + int i; for (p = 0; p < PROGRAMMER_INVALID; p++) { pname = programmer_table[p].name; @@ -1737,7 +1743,7 @@ msg_gerr("Known laptops table does not exist!\n"); ret = 1; } -#endif +#endif // CONFIG_INTERNAL == 1 return ret; } Index: flashrom-revert_r1397_partially/board_enable.c =================================================================== --- flashrom-revert_r1397_partially/board_enable.c (Revision 1402) +++ flashrom-revert_r1397_partially/board_enable.c (Arbeitskopie) @@ -179,7 +179,7 @@ static const struct winbond_port w83627hf[3] = { UNIMPLEMENTED_PORT, {w83627hf_port2_mux, 0x08, 0, 0xF0}, - UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT }; static const struct winbond_mux w83627ehf_port2_mux[8] = { @@ -190,7 +190,7 @@ {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */ {0x2A, 0x01, 0x01}, {0x2A, 0x01, 0x01}, - {0x2A, 0x01, 0x01}, + {0x2A, 0x01, 0x01} }; static const struct winbond_port w83627ehf[6] = { @@ -199,7 +199,7 @@ UNIMPLEMENTED_PORT, UNIMPLEMENTED_PORT, UNIMPLEMENTED_PORT, - UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT }; static const struct winbond_mux w83627thf_port4_mux[8] = { @@ -210,7 +210,7 @@ {0x2D, 0x10, 0x10}, /* or PWROK */ {0x2D, 0x20, 0x20}, /* or suspend LED */ {0x2D, 0x40, 0x40}, /* or panel switch input */ - {0x2D, 0x80, 0x80}, /* or panel switch output */ + {0x2D, 0x80, 0x80} /* or panel switch output */ }; static const struct winbond_port w83627thf[5] = { @@ -218,7 +218,7 @@ UNIMPLEMENTED_PORT, /* GPIO2 */ UNIMPLEMENTED_PORT, /* GPIO3 */ {w83627thf_port4_mux, 0x09, 1, 0xF4}, - UNIMPLEMENTED_PORT, /* GPIO5 */ + UNIMPLEMENTED_PORT /* GPIO5 */ }; static const struct winbond_chip winbond_chips[] = { @@ -812,7 +812,7 @@ { struct pci_dev *dev; - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */ + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; @@ -860,7 +860,7 @@ return -1; } - /* First, check the ISA bridge */ + /* First, check the ISA Bridge */ dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ @@ -1101,7 +1101,7 @@ struct pci_dev *dev; uint32_t reg; - dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */ + dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */ if (!dev) { msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); return -1; @@ -1128,8 +1128,8 @@ struct pci_dev *dev; uint32_t tmp, base; - /* GPPO {0,8,27,28,30} are always available */ - static const uint32_t nonmuxed_gpos = 0x58000101; + /* GPO{0,8,27,28,30} are always available. */ + static const uint32_t nonmuxed_gpos = 0x58000101; static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { {0}, @@ -1178,10 +1178,9 @@ } if ((((1 << gpo) & nonmuxed_gpos) == 0) && - (pci_read_word(dev, piix4_gpo[gpo].reg) - & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value) { - msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", - gpo); + ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != + piix4_gpo[gpo].value)) { + msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo); return -1; } @@ -1317,7 +1316,7 @@ /* libpci before version 2.2.4 does not store class info. */ device_class = pci_read_word(dev, PCI_CLASS_DEVICE); if ((dev->vendor_id == 0x8086) && - (device_class == 0x0601)) { /* ISA bridge */ + (device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id) @@ -1329,7 +1328,7 @@ } if (!dev) { - msg_perr("\nERROR: No known Intel LPC bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } @@ -1349,12 +1348,12 @@ allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - msg_perr("\nERROR: This Intel LPC bridge does not allow" - " setting GPIO%02d\n", gpio); + msg_perr("\nERROR: This Intel LPC Bridge does not allow" + " setting GPIO%02d\n", gpio); return -1; } - msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { @@ -1373,7 +1372,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; @@ -1405,7 +1404,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; @@ -1434,7 +1433,7 @@ tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } @@ -2091,8 +2090,8 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static const struct board_pciid_enable *board_match_coreboot_name( - const char *vendor, const char *part) +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, + const char *part) { const struct board_pciid_enable *board = board_pciid_enables; const struct board_pciid_enable *partmatch = NULL; @@ -2144,8 +2143,7 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -const static struct board_pciid_enable *board_match_pci_card_ids( - enum board_match_phase phase) +const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase) { const struct board_pciid_enable *board = board_pciid_enables; -- http://www.hailfinger.org/

2 12

[commit] r1424 - trunk
by repository service 31 Aug '11

31 Aug '11

Author: hailfinger Date: Wed Aug 31 18:19:50 2011 New Revision: 1424 URL: http://flashrom.org/trac/flashrom/changeset/1424 Log: Shorten some board enable related function names Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/board_enable.c Wed Aug 31 18:19:50 2011 (r1424) @@ -1974,7 +1974,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -const struct board_pciid_enable board_pciid_enables[] = { +const struct board_match board_matches[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -2102,11 +2102,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static const struct board_pciid_enable *board_match_coreboot_name( - const char *vendor, const char *part) +static const struct board_match *board_match_cbname(const char *vendor, + const char *part) { - const struct board_pciid_enable *board = board_pciid_enables; - const struct board_pciid_enable *partmatch = NULL; + const struct board_match *board = board_matches; + const struct board_match *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -2153,12 +2153,11 @@ /* * Match boards on PCI IDs and subsystem IDs. - * Second set of IDs can be main only or missing completely. + * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs. */ -const static struct board_pciid_enable *board_match_pci_card_ids( - enum board_match_phase phase) +const static struct board_match *board_match_pci_ids(enum board_match_phase phase) { - const struct board_pciid_enable *board = board_pciid_enables; + const struct board_match *board = board_matches; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -2204,7 +2203,7 @@ return NULL; } -static int unsafe_board_handler(const struct board_pciid_enable *board) +static int unsafe_board_handler(const struct board_match *board) { if (!board) return 1; @@ -2231,9 +2230,9 @@ /* FIXME: Should this be identical to board_flash_enable? */ static int board_handle_phase(enum board_match_phase phase) { - const struct board_pciid_enable *board = NULL; + const struct board_match *board = NULL; - board = board_match_pci_card_ids(phase); + board = board_match_pci_ids(phase); if (unsafe_board_handler(board)) board = NULL; @@ -2262,14 +2261,14 @@ int board_flash_enable(const char *vendor, const char *part) { - const struct board_pciid_enable *board = NULL; + const struct board_match *board = NULL; int ret = 0; if (part) - board = board_match_coreboot_name(vendor, part); + board = board_match_cbname(vendor, part); if (!board) - board = board_match_pci_card_ids(P3); + board = board_match_pci_ids(P3); if (unsafe_board_handler(board)) board = NULL; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/flashrom.c Wed Aug 31 18:19:50 2011 (r1424) @@ -1731,7 +1731,7 @@ msg_gerr("Chipset enables table does not exist!\n"); ret = 1; } - if (board_pciid_enables == NULL) { + if (board_matches == NULL) { msg_gerr("Board enables table does not exist!\n"); ret = 1; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/print.c Wed Aug 31 18:19:50 2011 (r1424) @@ -203,7 +203,7 @@ const char *devicetype) { int i, boardcount_good = 0, boardcount_bad = 0; - const struct board_pciid_enable *e = board_pciid_enables; + const struct board_match *e = board_matches; const struct board_info *b = boards; int maxvendorlen = strlen("Vendor") + 1; int maxboardlen = strlen("Board") + 1; @@ -241,7 +241,7 @@ msg_ginfo(" "); msg_ginfo((b->working) ? "OK " : "BAD "); - for (e = board_pciid_enables; e->vendor_name != NULL; e++) { + for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) || strcmp(e->board_name, b->name)) continue; Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/print_wiki.c Wed Aug 31 18:19:50 2011 (r1424) @@ -125,7 +125,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - const struct board_pciid_enable *b = board_pciid_enables; + const struct board_match *b = board_matches; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/programmer.h Wed Aug 31 18:19:50 2011 (r1424) @@ -158,7 +158,7 @@ P3 }; -struct board_pciid_enable { +struct board_match { /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; uint16_t first_device; @@ -190,7 +190,7 @@ int (*enable) (void); /* May be NULL. */ }; -extern const struct board_pciid_enable board_pciid_enables[]; +extern const struct board_match board_matches[]; struct board_info { const char *vendor;

1 0

[PATCH] add SPI interface support for Tunnel Creek chipset
by Feldschmid, Ingo 30 Aug '11

30 Aug '11

The Intel Tunnel Creek chipset supports both an SPI and an LPC bus. Set chipset table entry for Tunnel Creek to new function "enable_flash_tunnelcreek", which will read the hardware straps and return support for the bus that has been used for booting. This function uses "ich_init_spi" with ich_generation set to 7 for initializing the SPI bus if necessary. SPI functionality tested on actual hardware (see attached file flashrom.log), Tunnel Creek LPC interface not tested yet (missing hardware for that). Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> <<tunnelcreek.patch>> <<flashrom.log>> Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

2 1

Re: [flashrom] alix2d13, AMD CS5536: problem report with v0.9.2-r1141
by Paul Menzel 30 Aug '11

30 Aug '11

Dear Bill, thank you for report. Am Montag, den 29.08.2011, 14:36 -0700 schrieb Bill Larson: > Here is the message I get when running flashrom. > > root@voyage:~# flashrom > flashrom v0.9.2-r1141 on Linux 2.6.33.7-rt29-voyage (i586), built with libpci 3. > 1.7, GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org Please try a newer version like 0.9.4 or directly from SVN [1]. > Calibrating delay loop... OK. > No coreboot table found. > sh: dmidecode: not found > dmidecode execution unsucessfull - continuing without DMI info > Found chipset "AMD CS5536", enabling flash write... OK. > WARNING: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom(a)flashrom.org! > This chipset supports the following protocols: Non-SPI. > Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. > No operations were specified. > > I'm running it on a PC Engines alix2d13 board. > > http://pcengines.ch/alix2d13.htm > > And the lspci results > > 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host > Bridge (rev 33) > 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX A > ES Security Block > 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (r > ev 03) > 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE > (rev 01) > 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OH > C (rev 02) > 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EH > C (rev 02) Please turn off line wrapping when inserting stuff. Thanks, Paul [1] http://flashrom.org/Downloads

1 0

problem report
by Bill Larson 29 Aug '11

29 Aug '11

Here is the message I get when running flashrom. root@voyage:~# flashrom flashrom v0.9.2-r1141 on Linux 2.6.33.7-rt29-voyage (i586), built with libpci 3. 1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. sh: dmidecode: not found dmidecode execution unsucessfull - continuing without DMI info Found chipset "AMD CS5536", enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org! This chipset supports the following protocols: Non-SPI. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. No operations were specified. I'm running it on a PC Engines alix2d13 board. http://pcengines.ch/alix2d13.htm And the lspci results 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX A ES Security Block 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (r ev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OH C (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EH C (rev 02)

1 0

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 29 Aug '11

29 Aug '11

On Fri, 26 Aug 2011 11:25:27 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > Now I loaded the Revision 1421 from SVN repository, patched it and tried to compile - nope :-( > > Output of GCC: > ---snip--- > Checking for a C compiler... found. > ARCH is "x86" > Checking for libpci headers... found. > Checking if libpci is present and sufficient... yes. > Checking for FTDI support... not found. > Checking for utsname support... found. > cc -MMD -Os -Wall -Wshadow -Werror -D'CONFIG_INTERNAL=1' -D'CONFIG_SERPROG=1' -D'CONFIG_RAYER_SPI=1' -D'CONFIG_BITBANG_SPI=1' -D'CONFIG_NIC3COM=1' -D'CONFIG_GFXNVIDIA=1' -D'CONFIG_SATASII=1' -D'CONFIG_DUMMY=1' -D'CONFIG_DRKAISER=1' -D'CONFIG_NICREALTEK=1' -D'CONFIG_NICINTEL=1' -D'CONFIG_NICINTEL_SPI=1' -D'CONFIG_OGP_SPI=1' -D'CONFIG_BUSPIRATE_SPI=1' -D'CONFIG_SATAMV=1' -D'NEED_PCI=1' -D'HAVE_UTSNAME=1' -D'FLASHROM_VERSION="0.9.4-r1421"' -o layout.o -c layout.c > layout.c:43:20: error: expected â€˜=â€™, â€˜,â€™, â€˜;â€™, â€˜asmâ€™ or â€˜__attribute__â€™ before â€˜rom_entriesâ€™ > layout.c: In function â€˜read_romlayoutâ€™: > layout.c:161:50: error: â€˜rom_entriesâ€™ undeclared (first use in this function) > layout.c:161:50: note: each undeclared identifier is reported only once for each function it appears in > layout.c: At top level: > layout.c:214:12: error: static declaration of â€˜find_romentryâ€™ follows non-static declaration > flash.h:256:5: note: previous declaration of â€˜find_romentryâ€™ was here > layout.c: In function â€˜find_romentryâ€™: > layout.c:230:15: error: â€˜rom_entriesâ€™ undeclared (first use in this function) > layout.c: At top level: > layout.c:279:13: error: expected â€˜=â€™, â€˜,â€™, â€˜;â€™, â€˜asmâ€™ or â€˜__attribute__â€™ before â€˜*â€™ token > layout.c:309:47: error: expected â€˜)â€™ before â€˜*â€™ token > layout.c: In function â€˜build_new_imageâ€™: > layout.c:355:2: error: â€˜romlayout_tâ€™ undeclared (first use in this function) > layout.c:355:15: error: â€˜entryâ€™ undeclared (first use in this function) > cc1: warnings being treated as errors > layout.c:368:3: error: implicit declaration of function â€˜get_next_included_romentryâ€™ > layout.c:381:3: error: implicit declaration of function â€˜read_content_from_fileâ€™ > make: *** [layout.o] Error 1 > ---snip--- > ??? > > Please help. > hello the output was probably mangled in the mail transfer, but besides that it certainly does not look as it should either. i have tried to reproduce the behavior by checking out r1421 and applying the patches i have sent you. after each application of a patch i have run make clean; make and got no errors whatsoever. please assure that you have a clean checkout of r1421 without any remains of previous trials etc. and that the patches apply cleanly. if they dont, you have either started with the wrong sources or something is broken. in that case please tell us the exact command sequence (and the outputs respectively) that leads to the error. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] flashrom works with H67 Chip
by Stefan Tauner 29 Aug '11

29 Aug '11

On Sat, 27 Aug 2011 23:39:18 -0500 Dr Lawrence M Fox <drfox(a)chicagovet.net> wrote: > carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -w SH67H000.114 > flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci > 3.1.7, GCC 4.5.2, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel H67". > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK. > This chipset supports the following protocols: FWH, SPI. > Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFIED. Hello, Thanks for your report! I have marked the chipset as tested and will commit that later. > carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -V -w SH67H000.114 > flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci > 3.1.7, GCC 4.5.2, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 3360M loops per > second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 991 us, 10000 myus = > 9922 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Shuttle" > DMI string system-product-name: "SH67H3" > DMI string system-version: "1.0" > DMI string baseboard-manufacturer: "Shuttle" > DMI string baseboard-product-name: "FH67" > DMI string baseboard-version: "1.0" > DMI string chassis-type: "Desktop" I have also added your mainboard (FH67) used in your barebone to our list of supported boards, thank you. > Found ITE Super I/O, ID 0x8772 on port 0x2e > Found chipset "Intel H67" with PCI ID 8086:1c4a. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... > […] > Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 > 0x4016 > Chip status register is 00 > Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address > 0xffc00000. > […] > Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, > id2 0x15 > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, > […] > 0x3ff000-0x3fffff:S all those :S tokens indicate that the erase+write cycle for this block was skipped, because the content of the flash chip was equal to the file. this is of course expected because you have written the same file just before. i just mention it because this makes this log less informative. writing it in verbose mode the first time, would have been better for us. not a big deal though at all. > Erase/write done. > Verifying flash... VERIFIED. > Restoring MMIO space at 0x7f3670ff48a0 > Restoring MMIO space at 0x7f3670ff489c > Restoring MMIO space at 0x7f3670ff4898 > Restoring MMIO space at 0x7f3670ff4896 > Restoring MMIO space at 0x7f3670ff4894 > Restoring PCI config space for 00:1f:0 reg 0xdc -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Testing nicintel with SB82558B
by Andrew Morgan 28 Aug '11

28 Aug '11

Probe and read work. Erase fails and write requires erase to test. The problems could be to do with the (soldered) flash chip requiring VPP to write. I haven't tested the hardware any further yet, but I thought you might like this log to show that it does work this much. :) I have two of these cards, this one has a soldered flash chip, the other has a socket. I haven't tested the socketed one yet... -- Andrew.

2 1

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flashrom August 2011