flashrom June 2011

flashrom@flashrom.org

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297 discussions

[commit] r1330 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 11:53:22 2011 New Revision: 1330 URL: http://flashrom.org/trac/flashrom/changeset/1330 Log: ichspi.c: add macros and pretty printing for HSFS and HSFC Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Jun 11 11:53:16 2011 (r1329) +++ trunk/ichspi.c Sat Jun 11 11:53:22 2011 (r1330) @@ -43,6 +43,37 @@ #include "spi.h" /* ICH9 controller register definition */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -268,6 +299,28 @@ #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1213,14 +1266,15 @@ case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1267,10 +1321,6 @@ ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default:

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[commit] r1329 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 11:53:16 2011 New Revision: 1329 URL: http://flashrom.org/trac/flashrom/changeset/1329 Log: ichspi.c: add pretty printing for SSFS+SSFC and the OPCODE struct Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Jun 11 11:53:09 2011 (r1328) +++ trunk/ichspi.c Sat Jun 11 11:53:16 2011 (r1329) @@ -245,6 +245,50 @@ static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], + ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", + i, + oc.opcode, + oc.spi_type, + oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) + +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -521,6 +565,8 @@ } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); + msg_pdbg("\n"); return 0; } } @@ -796,6 +842,8 @@ temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1198,16 +1246,13 @@ tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94));

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[commit] r1328 - trunk
by repository service 11 Jun '11

11 Jun '11

Author: stefanct Date: Sat Jun 11 11:53:09 2011 New Revision: 1328 URL: http://flashrom.org/trac/flashrom/changeset/1328 Log: ichspi.c: improve macros for SSFS and SSFC bits - introduce offset macros and use them to (re)define the existing mask macros - fix masks of SSFC_COP, SSFC_DBC, SSFC_SCF (were single-bit masks erroneously) - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet; not in SSFS but HSFS) - use those for refactoring and magic number elemination. following patch uses them for pretty printing. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Jun 9 22:59:30 2011 (r1327) +++ trunk/ichspi.c Sat Jun 11 11:53:09 2011 (r1328) @@ -47,27 +47,41 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) /* The following bits are reserved in SSFS: 1,5-7. */ #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, - * therefore SSFC bits are off by 8. - * The following bits are reserved in SSFC: 23-19,7,0. */ + * therefore SSFC bits are off by 8. */ + /* 0: reserved */ +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) + /* 7: reserved */ +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 + /* 19-23: reserved */ #define SSFC_RESERVED_MASK 0xf8008100 #define ICH9_REG_PREOP 0x94 /* 16 Bits */ @@ -567,7 +581,7 @@ /* keep reserved bits */ temp16 &= SPIS_RESERVED_MASK; /* clear error status registers */ - temp16 |= (SPIS_CDS + SPIS_FCERR); + temp16 |= (SPIS_CDS | SPIS_FCERR); REGWRITE16(ICH7_REG_SPIS, temp16); /* Assemble SPIC */ @@ -709,8 +723,8 @@ temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE | SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -720,7 +734,8 @@ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) & + SSFC_DBC); temp32 |= datatemp; } @@ -767,7 +782,7 @@ REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); }

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[Patch] + RFC: Use shutdown callback mechanism to shutdown programmers
by David Hendricks 10 Jun '11

10 Jun '11

Hi everyone, Lately we've been looking into reverse PCI<http://flashrom.org/trac/flashrom/changeset/1232>and MMIO <http://patchwork.coreboot.org/patch/2331/> writes, along with the shutdown callback mechanism. The main usage case for Flashrom makes this a pretty simple matter, since most users only worry about a single programmer being used. However, when external devices are used which depend on internal programmer settings, things can get messy. Consider the case of a laptop with an x86 southbridge and an EC -- To communicate with the EC thru the LPC/FWH interface, some register settings in the southbridge might need to be changed. The code flow should be: 1. Set up SB, use rpci_* and rmmio_* to register reverse PCI and MMIO callbacks wherever necessary. 2. Set up EC. 3. Run code. 4. Call EC shutdown routine. 5. Reverse SB PCI/MMIO writes. However, the current code calls the programmer shutdown routine in step 4 * after* doing all shutdown callbacks in step 5. This causes southbridge registers to be reverted before the EC's shutdown routine is called, potentially making the EC unreachable. The attached patch addresses this by using programmer shutdown functions the same as any other shutdown callback. The internal_shutdown function is registered early in the internal_init() function so that newly discovered external programmers (ie SuperIO/EC LPC -> SPI bridges) can be discovered and have their shutdown callbacks added in the correct order. If this seems useful, we should make necessary changes to other programmers as well before committing this patch. Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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MSI 848P Neo-V (MS-6788-040) flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686)
by Melroy van den Berg 09 Jun '11

09 Jun '11

Hi, After this patch applied: http://patchwork.coreboot.org/patch/2452/ And finnaly added " -p internal:boardenable=force" to the command line. It says VERIFIED, I think everything went well using the MSI 848P Neo-V motherboard. server-pc:/home/melroy# flashrom -p internal:boardenable=force -w A6788IMS.610 flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom(a)flashrom.org with your board name and SUCCESS or FAILURE in the subject. Disabling flash write protection for board "MSI MS-6788-040 (848P NeoV)"... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. The (latest) BIOS can be found at the MSI website. -- Kind regards, Melroy van den Berg

2 1

Board enable for MSI MS-6788-040 (848P Neo-V)
by Maciej Pijanka 09 Jun '11

09 Jun '11

Hello Its a boardenable patch based on Michael's work for MSI MS-6788-04. -- Maciej Pijanka I don't fear computers, I fear lack of them -- Isaac Asimov

4 4

[commit] r1327 - trunk
by repository service 09 Jun '11

09 Jun '11

Author: hailfinger Date: Thu Jun 9 22:59:30 2011 New Revision: 1327 URL: http://flashrom.org/trac/flashrom/changeset/1327 Log: Add board enable for MSI MS-6788-040 (848P Neo-V). Based on reverse engineering by Michael Karcher. Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Tested-by: Melroy van den Berg http://www.flashrom.org/pipermail/flashrom/2010-December/005642.html Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jun 9 22:06:34 2011 (r1326) +++ trunk/board_enable.c Thu Jun 9 22:59:30 2011 (r1327) @@ -1572,6 +1572,7 @@ * Suited for: * - P4SD-LA (HP OEM): i865 + ICH5 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4 + * - MSI MS-6788-40 (aka 848P Neo-V) */ static int intel_ich_gpio32_raise(void) { @@ -2037,6 +2038,7 @@ {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},

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[PATCH] Fix compilation for CONFIG_INTERNAL=no
by Carl-Daniel Hailfinger 09 Jun '11

09 Jun '11

Fix compilation for CONFIG_INTERNAL=no CONFIG_INTERNAL implies Super I/O support and NEED_PCI. NEED_PCI is only used to guard PCI stuff which may be needed for external PCI-based programmers. That way, using #if NEED_PCI can be avoided inside -if CONFIG_INTERNAL. Please note that the patch seems to be nonsensical in some hunks, but if you look at the patched file you'll notice it's OK. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-compilefixes/buspirate_spi.c =================================================================== --- flashrom-compilefixes/buspirate_spi.c (Revision 1325) +++ flashrom-compilefixes/buspirate_spi.c (Arbeitskopie) @@ -30,6 +30,11 @@ /* Change this to #define if you want to test without a serial implementation */ #undef FAKE_COMMUNICATION +struct buspirate_spispeeds { + const char *name; + const int speed; +}; + #ifndef FAKE_COMMUNICATION static int buspirate_serialport_setup(char *dev) { Index: flashrom-compilefixes/programmer.h =================================================================== --- flashrom-compilefixes/programmer.h (Revision 1325) +++ flashrom-compilefixes/programmer.h (Arbeitskopie) @@ -239,7 +239,7 @@ void print_supported_pcidevs(const struct pcidev_status *devs); #endif -#if CONFIG_INTERNAL +#if CONFIG_INTERNAL == 1 /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); @@ -262,6 +262,7 @@ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); +#if CONFIG_INTERNAL == 1 int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); @@ -277,7 +278,6 @@ int dmi_match(const char *pattern); /* internal.c */ -#if NEED_PCI == 1 struct superio { uint16_t vendor; uint16_t port; @@ -287,6 +287,8 @@ extern int superio_count; #define SUPERIO_VENDOR_NONE 0x0 #define SUPERIO_VENDOR_ITE 0x1 +#endif +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -491,28 +493,21 @@ int rayer_spi_init(void); #endif -/* mcp6x_spi.c */ -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) -int mcp6x_spi_init(int want_spi); -#endif -#endif - /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); /* buspirate_spi.c */ -struct buspirate_spispeeds { - const char *name; - const int speed; -}; +#if CONFIG_BUSPIRATE_SPI == 1 int buspirate_spi_init(void); int buspirate_spi_shutdown(void); +#endif /* dediprog.c */ +#if CONFIG_DEDIPROG == 1 int dediprog_init(void); int dediprog_shutdown(void); +#endif /* flashrom.c */ struct decode_sizes { @@ -593,7 +588,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); int via_init_spi(struct pci_dev *dev); -#endif /* it85spi.c */ int it85xx_spi_init(struct superio s); @@ -605,23 +599,25 @@ void probe_superio_ite(void); int init_superio_ite(void); +/* mcp6x_spi.c */ +int mcp6x_spi_init(int want_spi); + /* sb600spi.c */ -#if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); -#endif /* wbsio_spi.c */ -#if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); #endif /* serprog.c */ +#if CONFIG_SERPROG == 1 int serprog_init(void); int serprog_shutdown(void); void serprog_chip_writeb(uint8_t val, chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int delay); +#endif /* serial.c */ #if _WIN32 -- http://www.hailfinger.org/

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[commit] r1326 - trunk
by repository service 09 Jun '11

09 Jun '11

Author: hailfinger Date: Thu Jun 9 22:06:34 2011 New Revision: 1326 URL: http://flashrom.org/trac/flashrom/changeset/1326 Log: Fix compilation for CONFIG_INTERNAL=no CONFIG_INTERNAL implies Super I/O support and NEED_PCI. NEED_PCI is only used to guard PCI stuff which may be needed for external PCI-based programmers. That way, using #if NEED_PCI can be avoided inside #if CONFIG_INTERNAL. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/buspirate_spi.c trunk/programmer.h Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Mon Jun 6 19:50:20 2011 (r1325) +++ trunk/buspirate_spi.c Thu Jun 9 22:06:34 2011 (r1326) @@ -30,6 +30,11 @@ /* Change this to #define if you want to test without a serial implementation */ #undef FAKE_COMMUNICATION +struct buspirate_spispeeds { + const char *name; + const int speed; +}; + #ifndef FAKE_COMMUNICATION static int buspirate_serialport_setup(char *dev) { Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Mon Jun 6 19:50:20 2011 (r1325) +++ trunk/programmer.h Thu Jun 9 22:06:34 2011 (r1326) @@ -239,7 +239,7 @@ void print_supported_pcidevs(const struct pcidev_status *devs); #endif -#if CONFIG_INTERNAL +#if CONFIG_INTERNAL == 1 /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); @@ -262,6 +262,7 @@ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); +#if CONFIG_INTERNAL == 1 int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); @@ -277,7 +278,6 @@ int dmi_match(const char *pattern); /* internal.c */ -#if NEED_PCI == 1 struct superio { uint16_t vendor; uint16_t port; @@ -287,6 +287,8 @@ extern int superio_count; #define SUPERIO_VENDOR_NONE 0x0 #define SUPERIO_VENDOR_ITE 0x1 +#endif +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -491,28 +493,21 @@ int rayer_spi_init(void); #endif -/* mcp6x_spi.c */ -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) -int mcp6x_spi_init(int want_spi); -#endif -#endif - /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); /* buspirate_spi.c */ -struct buspirate_spispeeds { - const char *name; - const int speed; -}; +#if CONFIG_BUSPIRATE_SPI == 1 int buspirate_spi_init(void); int buspirate_spi_shutdown(void); +#endif /* dediprog.c */ +#if CONFIG_DEDIPROG == 1 int dediprog_init(void); int dediprog_shutdown(void); +#endif /* flashrom.c */ struct decode_sizes { @@ -593,7 +588,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); int via_init_spi(struct pci_dev *dev); -#endif /* it85spi.c */ int it85xx_spi_init(struct superio s); @@ -605,23 +599,25 @@ void probe_superio_ite(void); int init_superio_ite(void); +/* mcp6x_spi.c */ +int mcp6x_spi_init(int want_spi); + /* sb600spi.c */ -#if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); -#endif /* wbsio_spi.c */ -#if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); #endif /* serprog.c */ +#if CONFIG_SERPROG == 1 int serprog_init(void); int serprog_shutdown(void); void serprog_chip_writeb(uint8_t val, chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int delay); +#endif /* serial.c */ #if _WIN32

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Re: [flashrom] [PATCH 01/12] improve macros for SSFS and SSFC bits
by Carl-Daniel Hailfinger 08 Jun '11

08 Jun '11

Am 08.06.2011 04:55 schrieb Stefan Tauner: > - introduce offset macros and use them to (re)define the existing mask macros > - add comments > - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) > - use those for refactoring and magic number elemination. > - following patch uses them for pretty printing > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ > 1 files changed, 30 insertions(+), 18 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 299cbf3..676b93a 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -47,24 +47,36 @@ > #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ > > #define ICH9_REG_SSFS 0x90 /* 08 Bits */ > -#define SSFS_SCIP 0x00000001 > -#define SSFS_CDS 0x00000004 > -#define SSFS_FCERR 0x00000008 > -#define SSFS_AEL 0x00000010 > +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ > +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) > +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ > +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) > +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ > +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) > +#define SSFS_AEL_OFF 4 /* Access Error Log */ > +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) > /* The following bits are reserved in SSFS: 1,5-7. */ > #define SSFS_RESERVED_MASK 0x000000e2 > > #define ICH9_REG_SSFC 0x91 /* 24 Bits */ > -#define SSFC_SCGO 0x00000200 > -#define SSFC_ACS 0x00000400 > -#define SSFC_SPOP 0x00000800 > -#define SSFC_COP 0x00001000 > -#define SSFC_DBC 0x00010000 > -#define SSFC_DS 0x00400000 > -#define SSFC_SME 0x00800000 > -#define SSFC_SCF 0x01000000 > -#define SSFC_SCF_20MHZ 0x00000000 > -#define SSFC_SCF_33MHZ 0x01000000 > +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ > +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) > +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ > +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) > +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ > +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) > +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ > +#define SSFC_COP (0x7 << SSFC_COP_OFF) > This is a code change. Can you mention it in the changelog, please? Some generic statement like "fix masks for register definitions SSFC_COP, ..." would suffice and help others to understand what you were doing. Please recheck that the changes were intentional, though. > +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ > +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) > Code change, see above. > +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ > +#define SSFC_DS (0x1 << SSFC_DS_OFF) > +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ > +#define SSFC_SME (0x1 << SSFC_SME_OFF) > +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ > +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) > Code change, see above. > +#define SSFC_SCF_20MHZ 0x00000000 > +#define SSFC_SCF_33MHZ 0x01000000 > /* We combine SSFS and SSFC to one 32-bit word, > * therefore SSFC bits are off by 8. > * The following bits are reserved in SSFC: 23-19,7,0. */ > > @@ -720,7 +732,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > if (datalength != 0) { > uint32_t datatemp; > temp32 |= SSFC_DS; > - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); > + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); > Please change this to datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); > temp32 |= datatemp; > } > > I'm still not entirely happy with "duplicating" all those definitions, once with _OFF and once without. That said, I see where you're going with that, so this patch is (with the casting change) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> No need to resend, just change the commit message and the cast before you commit. Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom June 2011