flashrom May 2011

flashrom@flashrom.org

55 participants
236 discussions

Supermicro success (X8DT3) and failure/bricking (X8SIE).
by Bill Broadley 12 Jun '11

12 Jun '11

First the success. I upgraded the BIOS on a Supermicro X8DT3 without problem. I upgraded it to version 2.0a of the BIOS with a release date of 09/14/2010. I was asked to send a flashrom -V, attached. The bad news, my Supermicro X8SIE completely bricked. During the flash: # flashrom -w x8sie0.527 flashrom v0.9.2-r1141 on Linux 2.6.38-8-generic (x86_64), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel 3420", enabling flash write... OK. This chipset supports the following protocols: FWH,SPI. Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address 0xffc00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... spi_block_erase_20 failed during command execution at address 0x0 spi_block_erase_52 failed during command execution at address 0x0 Verification impossible because read failed at 0x1000 (len 0x100) ERASE FAILED! spi_chip_erase_60 failed during command execution Verification impossible because read failed at 0x1000 (len 0x100) ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! I tried to read the image to see if I could tell if it was either the old ROM or the new: flashrom -r old-unknown.rom Reading flash... Read operation failed! FAILED. Found chipset "Intel 3420", enabling flash write... OK. This chipset supports the following protocols: FWH,SPI. Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address 0xffc00000. I found a rather promising mention in the manual of taking a USB key and copying the BIOS image (x8sie0.527 in this case) to super.rom then hold down <Ctrl> and <Home> simultaneously during bootup. Said system turns on, network lights come on, motherboard controlled fans come up. The USB's devices LEDs however never light. I suspect it's a loss, but I'm open to suggestions. If I do replace it I'll get another LGA1156 single socket server motherboard. Any motherboard that's known to work with flashrom would be a bonus.

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Success: Intel 82802AB on Supermicro X5DP8-G2 (chipset Intel ICH3-S/Intel E7501)
by Gerard Krol 12 Jun '11

12 Jun '11

Just a quick note to report success in flashing my bios using flashrom. Mainboard: Supermicro X5DP8-G2 Chipset: Intel E7501 (Intel ICH3-S) Flash Chip (reported by flashrom): Intel 82802AB I had to cut the rom to the correct size using dd if=ORIGNAL.ROM of=new.rom bs=512k count=1 I did a -r and then a -w, no errors. No other options were used. The bios complained about a wrong CMOS checksum after reboot so it loaded default settings. Regards, Gerard

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Re: [flashrom] [PATCH 05/11] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Carl-Daniel Hailfinger 11 Jun '11

11 Jun '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > With minor changes: Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > --- > chipset_enable.c | 11 ++++++++++- > 1 files changed, 10 insertions(+), 1 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 83b49ad..1f6f74c 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -264,8 +264,17 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > (old & (1 << 0)) ? "en" : "dis"); > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > - new = old | 1; > + /* > + * Quote from the 6 Series datasheet: > Please include a datasheet number so others can find it easily. > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > Maybe "Bit 5: SMM..." > + * 1 = BIOS region SMM protection is enabled. > + * The BIOS Region is not writable unless all processors are in SMM." > + * In earlier chipsets this bit is reserved. */ > + if (old & (1 << 5)) { > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > + } > > + new = old | 1; > if (new == old) > return 0; > > Regards, Carl-Daniel -- http://www.hailfinger.org/

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[Patch] + RFC: Use shutdown callback mechanism to shutdown programmers
by David Hendricks 10 Jun '11

10 Jun '11

Hi everyone, Lately we've been looking into reverse PCI<http://flashrom.org/trac/flashrom/changeset/1232>and MMIO <http://patchwork.coreboot.org/patch/2331/> writes, along with the shutdown callback mechanism. The main usage case for Flashrom makes this a pretty simple matter, since most users only worry about a single programmer being used. However, when external devices are used which depend on internal programmer settings, things can get messy. Consider the case of a laptop with an x86 southbridge and an EC -- To communicate with the EC thru the LPC/FWH interface, some register settings in the southbridge might need to be changed. The code flow should be: 1. Set up SB, use rpci_* and rmmio_* to register reverse PCI and MMIO callbacks wherever necessary. 2. Set up EC. 3. Run code. 4. Call EC shutdown routine. 5. Reverse SB PCI/MMIO writes. However, the current code calls the programmer shutdown routine in step 4 * after* doing all shutdown callbacks in step 5. This causes southbridge registers to be reverted before the EC's shutdown routine is called, potentially making the EC unreachable. The attached patch addresses this by using programmer shutdown functions the same as any other shutdown callback. The internal_shutdown function is registered early in the internal_init() function so that newly discovered external programmers (ie SuperIO/EC LPC -> SPI bridges) can be discovered and have their shutdown callbacks added in the correct order. If this seems useful, we should make necessary changes to other programmers as well before committing this patch. Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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MSI 848P Neo-V (MS-6788-040) flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686)
by Melroy van den Berg 09 Jun '11

09 Jun '11

Hi, After this patch applied: http://patchwork.coreboot.org/patch/2452/ And finnaly added " -p internal:boardenable=force" to the command line. It says VERIFIED, I think everything went well using the MSI 848P Neo-V motherboard. server-pc:/home/melroy# flashrom -p internal:boardenable=force -w A6788IMS.610 flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom(a)flashrom.org with your board name and SUCCESS or FAILURE in the subject. Disabling flash write protection for board "MSI MS-6788-040 (848P NeoV)"... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. The (latest) BIOS can be found at the MSI website. -- Kind regards, Melroy van den Berg

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Board enable for MSI MS-6788-040 (848P Neo-V)
by Maciej Pijanka 09 Jun '11

09 Jun '11

Hello Its a boardenable patch based on Michael's work for MSI MS-6788-04. -- Maciej Pijanka I don't fear computers, I fear lack of them -- Isaac Asimov

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Voltage & form-factor spreadsheet
by Steven Zakulec 04 Jun '11

04 Jun '11

Hello, some weeks ago I asked carldani what I could do to help the flashrom project, and he mentioned that they could really use someone to go thru all the chips in flashchips.c and get the voltage range and form factor(s) for each chip listed there. This is the result of that project: a spreadsheet with the chip name, voltage range, form factors, connector type (pins, leads, etc). This covers all the chips as of v1143. If anyone else is interested, I also have a short text file with all of the form factor acronyms I came across and what they mean (I grabbed the definition from the datasheet). There's a few missing chips, and some values that I wasn't quite sure about. Comments would be greatly appreciated.

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hi
by garrraaahyyy＠gmail.com 31 May '11

31 May '11

hey, you'll never see another opportunity like this http://g.msn.com.br/BR9/1369.0?http://cnbc7.com/news

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asus p4p800 error while flashing
by Yura I 31 May '11

31 May '11

Hi. I got an error while flashing asus p4p800 motherboard on ubuntu 10.04: $ sudo flashrom -w P4C800-ASUS-Entry-1021.005 flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x00000fff: 0x4fb ERASE FAILED! ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x0000ffff: 0xf419 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Old bios is saved. Computer isnt rebooted. Can you help me? Yuri

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Re: [flashrom] asus p4p800 error while flashing
by Paul Menzel 31 May '11

31 May '11

Dear Yuri, please always reply to the list and use interleaved quoting style [3]. I put your address into CC not being sure if you are following the list. Am Dienstag, den 31.05.2011, 13:22 +0400 schrieb Yura I: > Thaks for answer. I have compiled the latest version from snv. And got > still same error: Strange. > $ sudo flashrom -w P4P81019.rom > flashrom v0.9.3-r1322 on Linux 2.6.32-32-generic-pae (i686), built with > libpci 3.0.0, GCC 4.4.3, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. > This chipset supports the following protocols: FWH. > WARNING: Your mainboard is ASUS P4P800, but the mainboard-specific > code has not been tested, and thus will not be executed by default. > Depending on your hardware environment, erasing, writing or even probing > can fail without running the board specific code. > > Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection > "internal programmer") for details. > Found chip "SST SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Erasing and writing flash chip... ERASE FAILED at 0x00000ae8! > Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x00000fff: > 0x4fb > ERASE FAILED! > ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count > from 0x00000000-0x0000ffff: 0xf419 > ERASE FAILED! > Ошибка сегментирования > > Last translated message is "Segmentation fault". It should definitely not segfault. But this is where my knowledge stops and I have no time to look into this. You should definitely join the IRC channel. I do not know how scared you are but probably nothing fatal happened since no write was allowed or took place. But you should wait for the experts to tell you what to do. Thanks, Paul [3] http://en.opensuse.org/openSUSE:Mailing_list_netiquette

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flashrom May 2011