November 2011 - flashrom - mail.coreboot.org

External programmers
by Carl-Daniel Hailfinger 25 Dec '15

25 Dec '15

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Re: [flashrom] flashrom on PowerPC
by Stefan Tauner 20 Nov '15

20 Nov '15

On Wed, 27 Jul 2011 18:20:19 +0200 Mattias Mattsson <vitplister(a)gmail.com> wrote: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > i am resending this patch (unchanged) because patchwork did not pick it up correctly. please do send one patch per mail only in the future until we have something really working. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

[PATCH] Unlock ST M50FW002 correctly
by Carl-Daniel Hailfinger 29 May '14

29 May '14

Unlock ST M50FW002 correctly Refactor ST M50 family unlocking TODO: Unify write_lockbits_49fl00x() and unlock_block_stm50() and unlock_w39_fwh_block() and unlock_82802ab() and write_lockbits_block_49lfxxxc(). They all use exactly the same mechanism, but they don't share any code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-stm50fw002_unlock/flashchips.c =================================================================== --- flashrom-stm50fw002_unlock/flashchips.c (Revision 1437) +++ flashrom-stm50fw002_unlock/flashchips.c (Arbeitskopie) @@ -7523,9 +7523,9 @@ .total_size = 256, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ + .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = { { @@ -7536,9 +7536,12 @@ {16 * 1024, 1}, }, .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {256 * 1024, 1}, }, + .block_erase = NULL, /* Only in A/A mux mode */ } }, - .unlock = unlock_stm50flw0x0x, + .unlock = unlock_stm50fw002, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ Index: flashrom-stm50fw002_unlock/stm50flw0x0x.c =================================================================== --- flashrom-stm50fw002_unlock/stm50flw0x0x.c (Revision 1437) +++ flashrom-stm50fw002_unlock/stm50flw0x0x.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,21 @@ #include "flashchips.h" #include "chipdrivers.h" +#define STM50_UNLOCKED 0x00 + +static int unlock_block_stm50(struct flashchip *flash, int offset) +{ + chipaddr lock = flash->virtual_registers + offset + 2; + + msg_cdbg("Unlocking at 0x%x\n", offset); + chip_writeb(STM50_UNLOCKED, lock); + if (chip_readb(lock) != STM50_UNLOCKED) { + msg_cerr("Cannot unlock at 0x%x\n", offset); + return -1; + } + return 0; +} + /* * claus.gindhart(a)kontron.com * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, @@ -38,8 +54,6 @@ */ static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { - chipaddr wrprotect = flash->virtual_registers + 2; - static const uint8_t unlock_sector = 0x00; int j; /* @@ -58,22 +72,12 @@ || (offset == 0xF0000)) { // unlock each 4k-sector - for (j = 0; j < 0x10000; j += 0x1000) { - msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", - offset + j); + for (j = 0; j < 0x10000; j += 0x1000) + if (unlock_block_stm50(flash, offset + j)) return -1; - } - } } else { - msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", offset); + if (unlock_block_stm50(flash, offset)) return -1; - } } return 0; @@ -93,6 +97,27 @@ return 0; } +/* FIXME: Should this be moved to a generic walk_unlockregions()? */ +int unlock_stm50fw002(struct flashchip *flash) +{ + static const struct eraseblock unlockregions[4] = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}}; + int i, j; + int addr = 0; + + for (i = 0; i < 4; i++) { + for (j = 0; j < unlockregions[i].count; j++) { + if (unlock_block_stm50(flash, addr)) + return 1; + addr += unlockregions[i].size; + } + } + return 0; +} + /* This function is unused. */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) { Index: flashrom-stm50fw002_unlock/chipdrivers.h =================================================================== --- flashrom-stm50fw002_unlock/chipdrivers.h (Revision 1437) +++ flashrom-stm50fw002_unlock/chipdrivers.h (Arbeitskopie) @@ -146,5 +146,6 @@ /* stm50flw0x0x.c */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int unlock_stm50flw0x0x(struct flashchip *flash); +int unlock_stm50fw002(struct flashchip *flash); #endif /* !__CHIPDRIVERS_H__ */ -- http://www.hailfinger.org/

3 3

Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Carl-Daniel Hailfinger 09 May '14

09 May '14

Am 21.07.2011 17:54 schrieb Stefan Tauner: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Does the following not work for you? dd if=/dev/urandom bs=1k count=4k of=oldimage.bin flashrom -p dummy:emulate=SST25VF032B,image=oldimage.bin -w newimage.bin Regards, Carl-Daniel -- http://www.hailfinger.org/

5 8

Add timeout check to SPI bitbang bus request
by Carl-Daniel Hailfinger 29 Apr '14

29 Apr '14

Hi Iain, your Intel 82540EM which hangs on a flashrom run should spew "Timeout!" messages with this patch. It would be nice if you could tell us how long it waits for each chip probe so I can adjust the timeout value. Please note that this patch will _not_ fix the underlying issue, but I believe that an endless loop on possibly broken hardware is worse than aborting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_timeout/flash.h =================================================================== --- flashrom-bitbang_timeout/flash.h (Revision 1185) +++ flashrom-bitbang_timeout/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define TIMEOUT_ERROR -101 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-bitbang_timeout/bitbang_spi.c =================================================================== --- flashrom-bitbang_timeout/bitbang_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/bitbang_spi.c (Arbeitskopie) @@ -53,10 +53,11 @@ return bitbang_spi_master->get_miso(); } -static void bitbang_spi_request_bus(void) +static int bitbang_spi_request_bus(void) { if (bitbang_spi_master->request_bus) - bitbang_spi_master->request_bus(); + return bitbang_spi_master->request_bus(); + return 0; } static void bitbang_spi_release_bus(void) @@ -86,7 +87,7 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ + /* FIXME: Run bitbang_spi_request_bus here or per command? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); @@ -131,13 +132,15 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int i; + int i, ret; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the * programmer to use its own SPI engine for native accesses. */ - bitbang_spi_request_bus(); + ret = bitbang_spi_request_bus(); + if (ret) + return ret; bitbang_spi_set_cs(0); for (i = 0; i < writecnt; i++) bitbang_spi_readwrite_byte(writearr[i]); Index: flashrom-bitbang_timeout/nicintel_spi.c =================================================================== --- flashrom-bitbang_timeout/nicintel_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/nicintel_spi.c (Arbeitskopie) @@ -58,6 +58,8 @@ // #define FL_BUSY 30 // #define FL_ER 31 +#define MAX_REQUEST_LOOPS 10000 + uint8_t *nicintel_spibar; const struct pcidev_status nics_intel_spi[] = { @@ -68,16 +70,27 @@ {}, }; -static void nicintel_request_spibus(void) +static void nicintel_release_spibus(void); + +static int nicintel_request_spibus(void) { uint32_t tmp; + int i = 0; tmp = pci_mmio_readl(nicintel_spibar + FLA); tmp |= 1 << FL_REQ; pci_mmio_writel(tmp, nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ; + while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) { + if (i++ > MAX_REQUEST_LOOPS) { + nicintel_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } + + return 0; } static void nicintel_release_spibus(void) Index: flashrom-bitbang_timeout/mcp6x_spi.c =================================================================== --- flashrom-bitbang_timeout/mcp6x_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/mcp6x_spi.c (Arbeitskopie) @@ -40,22 +40,37 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 +#define MAX_REQUEST_LOOPS 10000 + void *mcp6x_spibar = NULL; /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; -static void mcp6x_request_spibus(void) +static void mcp6x_release_spibus(void); + +static int mcp6x_request_spibus(void) { + int i = 0; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) { + if (i++ > MAX_REQUEST_LOOPS) { + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp6x_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } /* Update the cache. */ mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return 0; } static void mcp6x_release_spibus(void) Index: flashrom-bitbang_timeout/programmer.h =================================================================== --- flashrom-bitbang_timeout/programmer.h (Revision 1185) +++ flashrom-bitbang_timeout/programmer.h (Arbeitskopie) @@ -131,7 +131,7 @@ void (*set_sck) (int val); void (*set_mosi) (int val); int (*get_miso) (void); - void (*request_bus) (void); + int (*request_bus) (void); void (*release_bus) (void); }; -- http://www.hailfinger.org/

4 15

Flashrom stuck using 100% cpu while probing for a chip
by GatoLoko 28 Apr '14

28 Apr '14

I've tried to run flashrom -V to see if it could identify the chip on my new board (AsRock M3A-GLAN), and it got stuck while probing for the first chip. I've tried commenting out that specific chip (AMIC A25L05PT) and then it gets stuck on the next one. Then commented out all AMIC chips, and it got stuck on the next one (the first ATMEL on the list) I've tried with an older flashrom (0.9.2-r1141). It skipped some AMD chips, then got stuck on AMIC again. Talked with "tlt" and "stefanct" on irc and they asked for a strace and a gdb backtrace. Strace produced no results. Gdb log is attached. "stefanct" tried and reproduced it on a machine with nicintel_spi, but warned it was with an unsupported nic: http://paste.flashrom.org/view.php?id=738 -- GatoLoko

4 11

[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger 21 Aug '13

21 Aug '13

flashrom relies on svn to export tarballs and only prints the last svn revision in the version message even if flashrom is in a git tree. Print extended version information (version, svn revision, git hash, repository URL). Allow exporting from git trees. This should make git users first-class citizens like svn users. Side note: If anyone has an idea how to make the export target more beautiful (80 column limit etc.), please tell me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-gitfriendly/Makefile =================================================================== --- flashrom-gitfriendly/Makefile (Revision 1145) +++ flashrom-gitfriendly/Makefile (Arbeitskopie) @@ -97,13 +97,15 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/') +SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown ) RELEASE := 0.9.2 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION) RELEASENAME ?= $(VERSION) -SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"' # Always enable internal/onboard support for now. CONFIG_INTERNAL ?= yes @@ -310,7 +312,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. @@ -420,9 +422,12 @@ export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) - @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) - @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile - @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/ + @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode + @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile + @# ChangeLog should be in English, but we want UTF-8 for names. + @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules @echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/ tarball: export Index: flashrom-gitfriendly/flashrom.c =================================================================== --- flashrom-gitfriendly/flashrom.c (Revision 1145) +++ flashrom-gitfriendly/flashrom.c (Arbeitskopie) @@ -1355,6 +1355,7 @@ void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo(" from " FLASHROM_SCMURL ","); print_sysinfo(); } @@ -1362,7 +1363,6 @@ { msg_ginfo("flashrom is free software, get the source code at " "http://www.flashrom.org\n"); - msg_ginfo("\n"); } int selfcheck(void) -- http://www.hailfinger.org/

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Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[RFC] Layout handling...
by Carl-Daniel Hailfinger 12 Jul '13

12 Jul '13

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] automatically round address ranges requested from physmap_common to page boundaries
by Stefan Tauner 31 Dec '12

31 Dec '12

On Mon, 30 May 2011 02:45:44 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > this patch also changes the display width of all addresses in physmap.c to 16 hex characters. > > FIXME: what about unmappings? > munmap is safe. > djgpp's __dpmi_free_physical_address_mapping: unknown. > DirectHW's unmap_physical: unknown. > > FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable FIXME: in the case we can not map and 'mayfail' is true we should return ERROR_PTR instead of ERROR_PTR + diff -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

[PATCH] Enable VX855 chipset
by John Schmerge 21 Oct '12

21 Oct '12

This patch adds support for the Via VX855 chipset

4 8

VIA VT6421A
by Magyar Szabolcs 30 Sep '12

30 Sep '12

Hi, I post a success story about a VIA VT6421A based SATA/PATA PCI controller. The flashrom can probe/read/write successfully the onboard PMC Pm49FL004 chip. I downloaded the patch from http://patchwork.coreboot.org/patch/3214/. Just one thing... "BAR type unknown..." I don't known the meaning, but it worked for me without errors. Please add the patch from above to the trunk. I attached a verbose probe output too. flashrom v0.9.3-r1362 on Linux 2.6.38-std220-i586 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found "VIA VT6421A" (1106:3249, BDF 00:0a.0). BAR type unknown, please report a bug at flashrom(a)flashrom.org === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Please add the name of your PCI device to the subject. Thank you for your help! === Found chip "PMC Pm49FL004" (512 kB, LPC, FWH) on atavia. Reading flash... done. Best regards, Szabolcs Magyar P.S.: Sorry for my english.

3 5

2 flashes on SPI bus
by Andrei Dolnikov 23 Sep '12

23 Sep '12

Hello folks, I would like to use a flashrom utility to access 2 serial flashes on the SPI bus of my x86 board, but I'm struggling with the second one. So I'm looking for any help, hints or advices which can help me to solve this issue. I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2 serial flashes installed on it. The first one is SST25VF016B and the second one is Numonyx M45PE16. The M45PE16 is pretty the similar to the M25PE16. Both this chips are connected to the SPI bus of the ICH8M chipset, the CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and the CS signal of the M45PE16 is routed to the SPI_CS1. I can successfully read, erase and write the SST flash. Trying to figure out if flashrom utility can find the second Numonyx flash I've added the proper description for it to the flashchips.c (actually I've leaved it the same as for M25PE16 but changed model_id field). Unfortunately it didn't help me at all. So I'm wondering if flashrom can't find M45PE16 flash because of cleared SPI_CS1 signal and how can I enable it? Does flashrom utility support such kind of configurations or does it simply searching for the flash on CS0? Probably some of you have some ideas on enabling SPI_CS1 or even some useful links etc. Unfortunately the official Intel ICH8M documentation looks kind of complicated and no so clear to me. I'll of course digg into it but any help, hints or advices are highly appreciated! Thanks in advance, xborodax.

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#5: Winbond W25Q128 for ICH
by flashrom 18 Sep '12

18 Sep '12

#5: Winbond W25Q128 for ICH ----------------------------------+--------------------------- Reporter: rheneus.paul@… | Owner: hailfinger Type: defect | Status: new Priority: critical | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patch Status: there is no patch | ----------------------------------+--------------------------- I could not use flashrom 0.9.3 -r1205 to detect Winbond W25Q128 to program BIOS. Attached the read log Just by adding WINBOND_NEX_W25Q128 0x4018 in flashchips.c for W25Q128, similar to W25Q64 throws run Opcode 0x3 error for read. Attached Verbose log of read -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/5> flashrom <http://www.flashrom.org/>

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Add support for unlock and write to Atmel AT26F040
by tim＠buttersideup.com 18 Sep '12

18 Sep '12

Add support for unlock and write to Atmel AT26F040 SPI 512k chips. Tested using a bus pirate only. I'm unavailble for a couple of weeks imminently, but will reply on return if pos... Cheers, Tim. ~# flashrom -c AT26F004 -p buspirate_spi:dev=/dev/ttyUSB0 -Vw rr620WDA-read-rom-image flashrom v0.9.3-r1349 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1088M loops per second, 10 myus = 10 us, 100 myus = 95 us, 1000 myus = 945 us, 10000 myus = 9495 us, 4 myus = 5 us, OK. Initializing buspirate_spi programmer SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x400 Chip status register is 1c Found chip "Atmel AT26F004" (512 kB, SPI) on buspirate_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Some block protection in effect, disabling All write protection disabled! Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:EW, 0x001000-0x001fff:W, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:W, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:EW, 0x011000-0x011fff:EW, 0x012000-0x012fff:EW, 0x013000-0x013fff:EW, 0x014000-0x014fff:EW, 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:EW, 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, 0x02a000-0x02aff f:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff: S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:W, 0x05c000-0x05cfff:W, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S Done. Verifying flash... VERIFIED. Raw bitbang mode version 1 Bus Pirate shutdown completed. Signed-off-by: Tim Small <tim(a)seoss.co.uk> Index: at25.c =================================================================== --- at25.c (revision 1349) +++ at25.c (working copy) @@ -215,6 +215,8 @@ /* spi_disable_blockprotect_at25df is not really the right way to do * this, but the side effects of said function work here as well. */ + /* FIXME? This does a global unlock, but at25f don't have this command? + */ return spi_disable_blockprotect_at25df(flash); } @@ -285,3 +287,71 @@ } return 0; } + + +int spi_disable_blockprotect_at26f040(struct flashchip *flash) +{ + uint8_t status; + uint32_t i; + int result; + + /* See Page 19 * + * http://www.atmel.com/dyn/resources/prod_documents/doc3588.pdf */ + + /* Write Protect Pin status: 0 == cannot set SPRL to 0 (unlocked) */ + const uint8_t stat_bit_WPP = (1 << 4); + + /* Software Protection Status: 00 == all sectors unprotected */ + const uint8_t stat_bit_SWP = (3 << 2); + + /* Sector Protection registers locked: 0 == unlocked. * + * Cannot be set to 0 if WPP is 1 (hardware lock). */ + const uint8_t stat_bit_SPRL = (1 << 7); + + /* Page 6 */ + const uint8_t at26f004_unprotect_sector = 0x39; + + status = spi_read_status_register(); + /* If block protection is disabled, OK to go ahead, stop here. */ + if ((status & stat_bit_SWP) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & stat_bit_SPRL) { + msg_cdbg("Need to disable Sector Protection Register Lock\n"); + if ((status & stat_bit_WPP) == 0) { + msg_cerr("The chips write-protect pin is being " + "asserted (driven low) by external hardware." + "\nWriting is impossible :-(.\n"); + return 1; + } + /* All bits except bit 7 (SPRL) are readonly. */ + /* Unlock sector protection registers. */ + result = spi_write_status_register(flash, status & ~stat_bit_SPRL); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + + } + /* Call unprotect sector on each sector. We need to give an address */ + /* within each sector, and the smallest sector is 8KB. */ + for (i = 0; i < 0x80000; i += 0x1000) { + const unsigned char cmd[4] = { at26f004_unprotect_sector, + (i >> 16) & 0xff, + (i >> 8) & 0xff, + i & 0xff}; + /* set the chip's "WEL" write latch - WREN (Write Enable) */ + spi_write_enable(); + spi_send_command(sizeof(cmd), 0, cmd, NULL); + } + status = spi_read_status_register(); + if ((status & stat_bit_SWP) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } else { + msg_cerr("All write protection disabled!\n"); + } + + return 0; +} Index: spi25.c =================================================================== --- spi25.c (revision 1349) +++ spi25.c (working copy) @@ -1210,3 +1210,94 @@ return 0; } + + +/* This is for Atmel chips only (AT26F004, AT26DF161A etc.) - the 25F004 only + * does either this mode, or byte-at-a-time. */ +int spi_at26_write_sequential(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* ref http://www.atmel.com/dyn/resources/prod_documents/doc3588.pdf + * page 9 etc. */ + const int AT26_SEQ_BYTE_WRITE_OUTSIZE = 5; + const int AT26_SEQ_BYTE_WRITE_CONT_OUTSIZE = 2; + const int AT26_SEQ_BYTE_WRITE_CMD = 0xaf; + uint32_t pos = start; + int result; + unsigned char cmd[4] = { + AT26_SEQ_BYTE_WRITE_CMD + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = AT26_SEQ_BYTE_WRITE_OUTSIZE, + .writearr = (const unsigned char[]){ + AT26_SEQ_BYTE_WRITE_CMD, + (start >> 16) & 0xff, + (start >> 8) & 0xff, + (start & 0xff), + buf[0] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + switch (spi_programmer->type) { +#if CONFIG_INTERNAL == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: + case SPI_CONTROLLER_WBSIO: + msg_perr("%s: impossible with this SPI controller," + " degrading to byte program\n", __func__); + return spi_chip_write_1(flash, buf, start, len); +#endif +#endif + default: + break; + } + + cmds[1].writearr = (const unsigned char[]){ + 0xAF, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[pos - start] + }; + + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); + /* FIXME: Should we send WRDI here as well to make sure the chip + * is not in seuquential wirte mode? + */ + return result; + } + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); + + pos ++; + + while (pos < start + len) { + cmd[1] = buf[pos++ - start]; + spi_send_command(AT26_SEQ_BYTE_WRITE_CONT_OUTSIZE, 0, cmd, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); + } + + /* Use WRDI to exit sequential write mode. This needs to be done before + * issuing any other non-sequential-byte-write commands. + */ + spi_write_disable(); + + return 0; +} Index: flashchips.c =================================================================== --- flashchips.c (revision 1349) +++ flashchips.c (working copy) @@ -1883,6 +1883,7 @@ }, .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, + /* Should support spi_at26_write_sequential too, but it's untested */ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -1914,6 +1915,7 @@ .model_id = ATMEL_AT26F004, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -1936,7 +1938,9 @@ .block_erase = spi_block_erase_c7, } }, - .write = NULL /* Incompatible Page write */, + .unlock = spi_disable_blockprotect_at26f040, + /* also supports spi_chip_write_1, but nothing else */ + .write = spi_at26_write_sequential, .read = spi_chip_read, .voltage = {2700, 3600}, }, Index: chipdrivers.h =================================================================== --- chipdrivers.h (revision 1349) +++ chipdrivers.h (working copy) @@ -55,6 +55,7 @@ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_at26_write_sequential(struct flashchip *flash, uint8_t *buf, int start, int len); /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); @@ -74,6 +75,7 @@ int spi_disable_blockprotect_at25f(struct flashchip *flash); int spi_disable_blockprotect_at25fs010(struct flashchip *flash); int spi_disable_blockprotect_at25fs040(struct flashchip *flash); +int spi_disable_blockprotect_at26f040(struct flashchip *flash); /* 82802ab.c */ uint8_t wait_82802ab(struct flashchip *flash);

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Flashing M/B Bios (Asus P5LD2-VM) goes wrong
by Emil Sirbu 07 Sep '12

07 Sep '12

Hello, I have an ASUS P5LD2-VM, and I try to update bios, first with flashrom v0.9.2-r1028 ( http://paste.flashrom.org/view.php?id=489 ) then with 0.9.3 ( http://paste.flashrom.org/view.php?id=490 also, the ROM is at http://paste.flashrom.org/uploads/491.bin ) but: Writing flash chip... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0xff, 0x004000-0x004fff, 0x005000-0x005fff, ERASE FAILED at 0x00005760! Expected=0xff, Read=0x50, failed byte count from 0x00005000-0x00005fff: 0x87a ERASE FAILED! Can you help whit this? I'm carco on freenode/#flashrom channel Thank you, Emil Sirbu

3 4

Gembird-PCI-VIA VT6421A-W39V040C
by Alexey 05 Sep '12

05 Sep '12

Hi! I'm going to flash Gembird PCI 3SATA+1IDE controller's BIOS, there is W39V040C. I found an excellent professionaly modified ROM for this device. I will try to do it on board of ASUS P4P800E-DELUX. Just let me know, is it possible in the moment or I have to wait for a new version of flashrom.exe? This device have unfriendly relations to Radeon X1600 AGP, on board of ASRock P4i45E MB, so I found only new modified ROM of PCI controller can help. Waiting for Your answer, Alexey.

2 4

[PATCH] Hack libpci not to exit(1) during init if PCI does not work
by Carl-Daniel Hailfinger 05 Sep '12

05 Sep '12

This patch is for testing only, and not for immediate merge. libpci unhelpfully calls exit(1) instead of reporting an error if init fails. Fortunately, that part of libpci has not changed since the year 2000, so we can use a really evil hack to avoid that. We supply an alternative error printing function (which does not exit(1)) and this function detects which error is happening and hacks internal libpci structures in a way that avoids a later segfault due to NULL pointer dereference. We MUST absolutely make sure that pci_init() in libpci will not change or this hack will explode spectacularly. Once we decide that this hack is the way to go, notifying the libpci maintainer is essential. Apply this patch, then compile flashrom with make CONFIG_DUMMY=no CONFIG_INTERNAL=o CONFIG_SERPROG=no CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no CONFIG_GFXNVIDIA=no CONFIG_SATASII=no CONFIG_FT2232_SPI=no CONFIG_DRKAISER=no CONFIG_NICREALTEK=no CONFIG_NICINTEL_SPI=no CONFIG_BUSPIRATE_SPI=no CONFIG_OGP_SPI=no CONFIG_SATAMV=no CONFIG_NICINTEL=yes To check if the hack works, run "flashrom -V" and respond to this mail with the output. You should get a message near the end which says that programmer initialization failed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c =================================================================== --- flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Revision 1362) +++ flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Arbeitskopie) @@ -21,6 +21,8 @@ #include <stdlib.h> #include <string.h> +#include <stdio.h> +#include <stdarg.h> #include "flash.h" #include "programmer.h" @@ -188,6 +190,58 @@ return 0; } +/* Ugliest hack ever in flashrom! Should work for all libpci versions released + * in the year 2000 or later. Checked to make sense until at least version + * 3.1.8-test1. + */ +static void fake_libpci_method_init(struct pci_access *foo) +{ + msg_pinfo("Working around another pcilib crash\n"); + return; +} + +static struct { + char *name; /* name in all libpci versions */ + char *dummy1; /* Only present in some libpci versions */ + void *dummy2; + void (*init1)(struct pci_access *); /* init in older versions */ + void (*init2)(struct pci_access *); /* init in newer versions */ + void *dummy3; + void *dummy4; + void *dummy5; + void *dummy6; + void *dummy7; + void *dummy8; + void *dummy9; + void *dummy10; +} fake_libpci_methods = { + .name = "None", + .init1 = &fake_libpci_method_init, + .init2 = &fake_libpci_method_init, +}; + +static int pci_init_failed = 0; + +static void my_libpci_generic_error(char *msg, ...) +{ + va_list ap; + + msg_pinfo("pcilib: "); + va_start(ap, msg); + vprintf(msg, ap); + va_end(ap); + msg_pinfo("\n"); + if (!strcmp(msg, "Cannot find any working access method.")) { + /* Workaround for crash, very ugly. */ + msg_pinfo("Working around pcilib crash\n"); + pacc->methods = (void *)&fake_libpci_methods; + pci_init_failed = 1; + } else { + /* Any error in libpci would result in exit(1) by default. */ + exit(1); + } +} + uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -198,7 +252,14 @@ uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ + pacc->error = &my_libpci_generic_error; pci_init(pacc); /* Initialize the PCI library */ + /* pci_init returns void, so we have to hack it. */ + if (pci_init_failed) { + /* Yes, technically we would have to free stuff... */ + return 1; + } + pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); -- http://www.hailfinger.org/

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[PATCH] Add Spi interface support for Tunnel Creek chipset (3)
by Feldschmid, Ingo 30 Aug '12

30 Aug '12

Hi, Last changes I submitted have been vs. trunk 1424. Since there is a new version out, I will resubmit the changes built against the new flashrom trunk version: The Intel Tunnel Creek chipset supports both an SPI and an LPC bus. Set chipset table entry for Tunnel Creek to new function "enable_flash_tunnelcreek", which will read the hardware straps and return support for the bus that has been used for booting. This function uses "ich_init_spi" with ich_generation set to 7 for initializing the SPI bus if necessary. SPI functionality tested on actual hardware (see attached file flashrom.log), Tunnel Creek LPC interface not tested yet (missing hardware for that). The attached patch has been created vs. flashrom trunk 1427. Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

3 3

[PATCH] Fix flashrom -L
by Carl-Daniel Hailfinger 27 Aug '12

27 Aug '12

flashrom -L output did not contain a list of programmers nor were all programmers listed. Fix it. (Well, mostly. Some programmers have no devices listed. And formatting on 80 column screens is totally broken for the flash chip list.) Wiki output is unchanged, and will need separate fixups. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> New output from flashrom -L follows: flashrom v0.9.2-r1196 on Linux 2.6.22.19-0.2-default (i686), built with libpci 2.2.6, LLVM Clang 2.8 (trunk 108130), little endian flashrom is free software, get the source code at http://www.flashrom.org Supported flash chips (total: 261): Vendor Device Tested Known Size/KB: Type: OK Broken (P = PROBE, R = READ, E = ERASE, W = WRITE) AMD Am29F010A/B P R E W 128 Parallel AMD Am29F002(N)BB 256 Parallel AMD Am29F002(N)BT 256 Parallel AMD Am29F016D 2048 Parallel AMD Am29F040B 512 Parallel AMD Am29F080B 1024 Parallel AMD Am29LV040B P R E W 512 Parallel AMD Am29LV081B 1024 Parallel AMIC A25L05PT 64 SPI AMIC A25L05PU 64 SPI AMIC A25L10PT 128 SPI AMIC A25L10PU 128 SPI AMIC A25L20PT 256 SPI AMIC A25L20PU 256 SPI AMIC A25L40PT P R W 512 SPI AMIC A25L40PU P R W 512 SPI AMIC A25L80P P R E W 1024 SPI AMIC A25L16PT 2048 SPI AMIC A25L16PU P R W 2048 SPI AMIC A25L512 64 SPI AMIC A25L010 128 SPI AMIC A25L020 256 SPI AMIC A25L040 512 SPI AMIC A25L080 1024 SPI AMIC A25L016 2048 SPI AMIC A25L032 4096 SPI AMIC A25LQ032 4096 SPI AMIC A29002B 256 Parallel AMIC A29002T P R W 256 Parallel AMIC A29040B 512 Parallel AMIC A49LF040A P R E W 512 LPC Atmel AT25DF021 256 SPI Atmel AT25DF041A 512 SPI Atmel AT25DF081 1024 SPI Atmel AT25DF081A 1024 SPI Atmel AT25DF161 2048 SPI Atmel AT25DF321 P R E W 4096 SPI Atmel AT25DF321A 4096 SPI Atmel AT25DF641 8192 SPI Atmel AT25DQ161 2048 SPI Atmel AT25F512B 64 SPI Atmel AT25FS010 128 SPI Atmel AT25FS040 512 SPI Atmel AT26DF041 512 SPI Atmel AT26DF081A P R 1024 SPI Atmel AT26DF161 2048 SPI Atmel AT26DF161A 2048 SPI Atmel AT26F004 512 SPI Atmel AT29C512 64 Parallel Atmel AT29C010A P R E W 128 Parallel Atmel AT29C020 256 Parallel Atmel AT29C040A 512 Parallel Atmel AT45CS1282 R 16896 SPI Atmel AT45DB011D R 128 SPI Atmel AT45DB021D R 256 SPI Atmel AT45DB041D R 512 SPI Atmel AT45DB081D R 1024 SPI Atmel AT45DB161D R 2048 SPI Atmel AT45DB321C R 4224 SPI Atmel AT45DB321D R 4096 SPI Atmel AT45DB642D R 8192 SPI Atmel AT49BV512 64 Parallel Atmel AT49F020 P R E W 256 Parallel Atmel AT49F002(N) 256 Parallel Atmel AT49F002(N)T P R W 256 Parallel Bright BM29F040 P R 512 Parallel EMST F49B002UA 256 Parallel EMST F25L008A 1024 SPI Eon EN25B05 64 SPI Eon EN25B05T 64 SPI Eon EN25B10 128 SPI Eon EN25B10T 128 SPI Eon EN25B20 256 SPI Eon EN25B20T 256 SPI Eon EN25B40 512 SPI Eon EN25B40T 512 SPI Eon EN25B80 1024 SPI Eon EN25B80T 1024 SPI Eon EN25B16 2048 SPI Eon EN25B16T 2048 SPI Eon EN25B32 4096 SPI Eon EN25B32T 4096 SPI Eon EN25B64 8192 SPI Eon EN25B64T 8192 SPI Eon EN25D16 2048 SPI Eon EN25F05 64 SPI Eon EN25F10 128 SPI Eon EN25F20 256 SPI Eon EN25F40 P 512 SPI Eon EN25F80 P R E W 1024 SPI Eon EN25F16 2048 SPI Eon EN25F32 4096 SPI Eon EN29F010 P R E W 128 Parallel Eon EN29F002(A)(N)B P R W 256 Parallel Eon EN29F002(A)(N)T P R W 256 Parallel Fujitsu MBM29F004BC 512 Parallel Fujitsu MBM29F004TC 512 Parallel Fujitsu MBM29F400BC W 512 Parallel Fujitsu MBM29F400TC 512 Parallel Hyundai HY29F002T P R E W 256 Parallel Hyundai HY29F002B 256 Parallel Hyundai HY29F040A 512 Parallel Intel 28F001BN/BX-B 128 Parallel Intel 28F001BN/BX-T 128 Parallel Intel 28F002BC/BL/BV/BX-T P R E W 256 Parallel Intel 28F008S3/S5/SC 512 Parallel Intel 28F004B5/BE/BV/BX-B 512 Parallel Intel 28F004B5/BE/BV/BX-T 512 Parallel Intel 28F400BV/BX/CE/CV-B 512 Parallel Intel 28F400BV/BX/CE/CV-T 512 Parallel Intel 82802AB P R 512 FWH Intel 82802AC P R 1024 FWH Macronix MX25L512 64 SPI Macronix MX25L1005 128 SPI Macronix MX25L2005 256 SPI Macronix MX25L4005 P R W 512 SPI Macronix MX25L8005 P R E W 1024 SPI Macronix MX25L1605 P R W 2048 SPI Macronix MX25L1635D 2048 SPI Macronix MX25L1635E 2048 SPI Macronix MX25L3205 P R W 4096 SPI Macronix MX25L3235D 4096 SPI Macronix MX25L6405 P 8192 SPI Macronix MX25L12805 16384 SPI Macronix MX29F001B 128 Parallel Macronix MX29F001T 128 Parallel Macronix MX29F002B 256 Parallel Macronix MX29F002T P R W 256 Parallel Macronix MX29F040 512 Parallel Macronix MX29LV040 512 Parallel MoselVitelic V29C51000B 64 Parallel MoselVitelic V29C51000T 64 Parallel MoselVitelic V29C51400B 512 Parallel MoselVitelic V29C51400T 512 Parallel MoselVitelic V29LC51000 64 Parallel MoselVitelic V29LC51001 128 Parallel MoselVitelic V29LC51002 256 Parallel Numonyx M25PE10 128 SPI Numonyx M25PE20 256 SPI Numonyx M25PE40 512 SPI Numonyx M25PE80 P R E W 1024 SPI Numonyx M25PE16 2048 SPI PMC Pm25LV010 128 SPI PMC Pm25LV016B 2048 SPI PMC Pm25LV020 256 SPI PMC Pm25LV040 512 SPI PMC Pm25LV080B 1024 SPI PMC Pm25LV512 64 SPI PMC Pm29F002T P R E W 256 Parallel PMC Pm29F002B 256 Parallel PMC Pm39LV010 P R E W 128 Parallel PMC Pm39LV020 256 Parallel PMC Pm39LV040 512 Parallel PMC Pm49FL002 P R E W 256 LPC,FWH PMC Pm49FL004 P R E W 512 LPC,FWH Sanyo LF25FW203A 2048 SPI Sharp LHF00L04 1024 FWH Spansion S25FL008A P R E W 1024 SPI Spansion S25FL016A P R W 2048 SPI SST SST25VF016B P R E W 2048 SPI SST SST25VF032B P R E W 4096 SPI SST SST25VF064C P R E W 8192 SPI SST SST25VF040.REMS P R 512 SPI SST SST25VF040B 512 SPI SST SST25LF040A.RES P 512 SPI SST SST25VF040B.REMS P R 512 SPI SST SST25VF080B P R E W 1024 SPI SST SST28SF040A 512 Parallel SST SST29EE010 P R W 128 Parallel SST SST29LE010 128 Parallel SST SST29EE020A P R E W 256 Parallel SST SST29LE020 P R E W 256 Parallel SST SST39SF512 64 Parallel SST SST39SF010A P R W 128 Parallel SST SST39SF020A P R E W 256 Parallel SST SST39SF040 P R E W 512 Parallel SST SST39VF512 P R E W 64 Parallel SST SST39VF010 P R E W 128 Parallel SST SST39VF020 256 Parallel SST SST39VF040 512 Parallel SST SST39VF080 1024 Parallel SST SST49LF002A/B P R E W 256 FWH SST SST49LF003A/B P R 384 FWH SST SST49LF004A/B P R E W 512 FWH SST SST49LF004C 512 FWH SST SST49LF008A P R E W 1024 FWH SST SST49LF008C 1024 FWH SST SST49LF016C P R W 2048 FWH SST SST49LF020 P R E W 256 LPC SST SST49LF020A P R E W 256 LPC SST SST49LF040 P R E W 512 LPC SST SST49LF040B P R E W 512 LPC SST SST49LF080A P R E W 1024 LPC SST SST49LF160C P R E W 2048 LPC ST M25P05-A 64 SPI ST M25P05.RES 64 SPI ST M25P10-A P R E W 128 SPI ST M25P10.RES 128 SPI ST M25P20 256 SPI ST M25P40 P R W 512 SPI ST M25P40-old 512 SPI ST M25P80 P R W 1024 SPI ST M25P16 P R W 2048 SPI ST M25P32 P R W 4096 SPI ST M25P64 8192 SPI ST M25P128 16384 SPI ST M25PX32 P R E W 4096 SPI ST M25PX64 P R E W 8192 SPI ST M29F002B 256 Parallel ST M29F002T/NT 256 Parallel ST M29F040B 512 Parallel ST M29F400BB W 512 Parallel ST M29F400BT 512 Parallel ST M29W010B 128 Parallel ST M29W040B 512 Parallel ST M29W512B P R E W 64 Parallel ST M50FLW040A 512 LPC,FWH ST M50FLW040B 512 LPC,FWH ST M50FLW080A P R E W 1024 LPC,FWH ST M50FLW080B 1024 LPC,FWH ST M50FW002 256 FWH ST M50FW016 2048 FWH ST M50FW040 P R 512 FWH ST M50FW080 P R 1024 FWH ST M50LPW116 2048 LPC SyncMOS/MoselVitelic {F,S,V}29C51001B 128 Parallel SyncMOS/MoselVitelic {F,S,V}29C51001T 128 Parallel SyncMOS/MoselVitelic {F,S,V}29C51002B 256 Parallel SyncMOS/MoselVitelic {F,S,V}29C51002T P R E W 256 Parallel SyncMOS/MoselVitelic {F,S,V}29C51004B 512 Parallel SyncMOS/MoselVitelic {F,S,V}29C51004T 512 Parallel SyncMOS/MoselVitelic {S,V}29C31004B 512 Parallel SyncMOS/MoselVitelic {S,V}29C31004T 512 Parallel TI TMS29F002RB 256 Parallel TI TMS29F002RT 256 Parallel Winbond W25Q80 P R E W 1024 SPI Winbond W25Q16 2048 SPI Winbond W25Q32 P R E W 4096 SPI Winbond W25Q64 P R W 8192 SPI Winbond W25x10 128 SPI Winbond W25x20 256 SPI Winbond W25x40 P R E W 512 SPI Winbond W25x80 P R E W 1024 SPI Winbond W25x16 P R E W 2048 SPI Winbond W25x32 P 4096 SPI Winbond W25x64 8192 SPI Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 P R W 128 Parallel Winbond W29C020(C)/W29C022 P R E W 256 Parallel Winbond W29C040/P 512 Parallel Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 P R E W 128 Parallel Winbond W39V040A P R W 512 LPC Winbond W39V040(F)B P R E W 512 LPC Winbond W39V040(F)C 512 LPC Winbond W39V040FA P R E W 512 FWH Winbond W39V080A 1024 LPC Winbond W49F002U/N P R E W 256 Parallel Winbond W49F020 P 256 Parallel Winbond W49V002A P R E W 256 LPC Winbond W49V002FA P R W 256 FWH Winbond W39V080FA P R E W 1024 FWH Winbond W39V080FA (dual mode) 512 FWH Supported programmers: internal, dummy, nic3com, nicrealtek, nicsmc1211, nicnatsemi, gfxnvidia, drkaiser, satasii, atahpt, it87spi, ft2232_spi, serprog, buspirate_spi, dediprog, rayer_spi, nicintel_spi Supported devices for the internal programmer: Supported chipsets (total: 152): Vendor: Chipset: PCI IDs: ALi M1533 10b9:1533 AMD AMD-768 1022:7440 AMD AMD8111 1022:7468 AMD CS5530(A) 1078:0100 AMD CS5536 1022:2080 AMD CS5536 1022:2090 AMD Elan SC520 1022:3000 AMD SB600 1002:438d AMD SB700/SB710/SB750 1002:439d AMD SC1100 100b:0510 (untested) ATI SB400 1002:4377 Broadcom OSB4 1166:0200 Broadcom HT-1000 1166:0205 Intel 3400 Desktop 8086:3b00 (untested) Intel 3400 Mobile 8086:3b01 (untested) Intel P55 8086:3b02 (untested) Intel PM55 8086:3b03 (untested) Intel H55 8086:3b06 (untested) Intel QM57 8086:3b07 Intel H57 8086:3b08 (untested) Intel HM55 8086:3b09 (untested) Intel Q57 8086:3b0a (untested) Intel HM57 8086:3b0b (untested) Intel 3400 Mobile SFF 8086:3b0d (untested) Intel B55 8086:3b0e (untested) Intel QS57 8086:3b0f (untested) Intel 3400 8086:3b12 (untested) Intel 3420 8086:3b14 (untested) Intel 3450 8086:3b16 (untested) Intel B55 8086:3b1e (untested) Intel 440MX 8086:7198 Intel 6300ESB 8086:25a1 Intel 631xESB/632xESB/3100 8086:2670 Intel EP80579 8086:5031 Intel ICH0 8086:2420 Intel ICH10 8086:3a18 Intel ICH10D 8086:3a1a Intel ICH10DO 8086:3a14 Intel ICH10R 8086:3a16 Intel ICH2 8086:2440 Intel ICH2-M 8086:244c Intel ICH3-M 8086:248c Intel ICH3-S 8086:2480 Intel ICH4/ICH4-L 8086:24c0 Intel ICH4-M 8086:24cc Intel ICH5/ICH5R 8086:24d0 Intel ICH6/ICH6R 8086:2640 Intel ICH6-M 8086:2641 Intel ICH7DH 8086:27b0 Intel ICH7/ICH7R 8086:27b8 Intel ICH7M 8086:27b9 Intel ICH7MDH 8086:27bd Intel NM10 8086:27bc Intel ICH 8086:2410 Intel ICH8DH 8086:2812 Intel ICH8DO 8086:2814 Intel ICH8/ICH8R 8086:2810 Intel ICH8M 8086:2815 Intel ICH8M-E 8086:2811 Intel ICH9 8086:2918 Intel ICH9DH 8086:2912 Intel ICH9DO 8086:2914 Intel ICH9M 8086:2919 Intel ICH9M-E 8086:2917 Intel ICH9R 8086:2916 Intel ICH9 Engineering Sample 8086:2910 Intel MPIIX 8086:1234 (untested) Intel PIIX3 8086:7000 Intel PIIX4/4E/4M 8086:7110 Intel PIIX 8086:122e Intel Poulsbo 8086:8119 NVIDIA nForce4/MCP4 10de:0030 NVIDIA CK804 10de:0050 NVIDIA CK804 10de:0051 NVIDIA NForce2 10de:0060 NVIDIA NForce3 10de:00e0 NVIDIA CK804 10de:00d3 NVIDIA MCP51 10de:0260 (untested) NVIDIA MCP51 10de:0261 (untested) NVIDIA MCP51 10de:0262 (untested) NVIDIA MCP51 10de:0263 (untested) NVIDIA MCP55 10de:0360 NVIDIA MCP55 10de:0362 NVIDIA MCP55 10de:0363 NVIDIA MCP55 10de:0364 NVIDIA MCP55 10de:0365 NVIDIA MCP55 10de:0366 NVIDIA MCP55 10de:0367 NVIDIA MCP61 10de:03e0 (untested) NVIDIA MCP61 10de:03e1 (untested) NVIDIA MCP61 10de:03e2 (untested) NVIDIA MCP61 10de:03e3 (untested) NVIDIA MCP65 10de:0440 (untested) NVIDIA MCP65 10de:0441 (untested) NVIDIA MCP65 10de:0442 (untested) NVIDIA MCP65 10de:0443 (untested) NVIDIA MCP67 10de:0548 NVIDIA MCP78S 10de:075c (untested) NVIDIA MCP78S 10de:075d (untested) NVIDIA MCP73 10de:07d7 (untested) NVIDIA MCP79 10de:0aac (untested) NVIDIA MCP79 10de:0aad (untested) NVIDIA MCP79 10de:0aae (untested) NVIDIA MCP79 10de:0aaf (untested) SiS 85C496+497 1039:0496 (untested) SiS 501/5101/5501 1039:0406 (untested) SiS 5511 1039:5511 (untested) SiS 5596 1039:5596 (untested) SiS 5571 1039:5571 (untested) SiS 5591/5592 1039:5591 (untested) SiS 5597/5598/5581/5120 1039:5597 (untested) SiS 530 1039:0530 (untested) SiS 600 1039:5600 (untested) SiS 620 1039:0620 (untested) SiS 540 1039:0540 (untested) SiS 630 1039:0630 (untested) SiS 635 1039:0635 (untested) SiS 640 1039:0640 (untested) SiS 645 1039:0645 (untested) SiS 645DX 1039:0646 (untested) SiS 648 1039:0648 (untested) SiS 650 1039:0650 (untested) SiS 651 1039:0651 (untested) SiS 655 1039:0655 (untested) SiS 661 1039:0661 SiS 730 1039:0730 (untested) SiS 733 1039:0733 (untested) SiS 735 1039:0735 SiS 740 1039:0740 (untested) SiS 741 1039:0741 SiS 745 1039:0745 SiS 746 1039:0746 (untested) SiS 748 1039:0748 (untested) SiS 755 1039:0755 (untested) VIA VT82C585VPX 1106:0585 (untested) VIA VT82C595 1106:0595 (untested) VIA VT82C597 1106:0597 (untested) VIA VT82C69x 1106:0691 (untested) VIA VT8601/VT8601A 1106:0601 (untested) VIA VT8601T 1106:8601 (untested) VIA CX700 1106:8324 VIA VT8231 1106:8231 (untested) VIA VT8233 1106:3074 (untested) VIA VT8233A 1106:3147 VIA VT8235 1106:3177 VIA VT8237 1106:3227 VIA VT8237A 1106:3337 VIA VT8237S 1106:3372 VIA VX800 1106:8353 VIA VT82C596 1106:0596 VIA VT82C586A/B 1106:0586 VIA VT82C686A/B 1106:0686 (untested) Known boards (good: 259, bad: 18): Vendor: Board: Status: Required option: A-Trend ATC-6220 OK abit AN-M2 OK (autodetected) abit AX8 OK abit BM6 OK (autodetected) abit Fatal1ty F-I90HD OK abit IC7 OK (autodetected) abit IP35 OK (autodetected) abit IP35 Pro OK (autodetected) abit IS-10 BAD abit KN8 Ultra OK (autodetected) abit NF-M2 nView OK (autodetected) abit NF7-S OK (autodetected) abit VA6 OK (autodetected) abit VT6X4 OK -m abit:vt6x4 Acorp 6A815EPD OK (autodetected) Advantech PCM-5820 OK agami Aruma OK -m AGAMI:ARUMA Albatron PM266A Pro OK (autodetected) AOpen vKM400Am-S OK Artec Group DBE61 OK -m artecgroup:dbe61 Artec Group DBE62 OK -m artecgroup:dbe62 ASI MB-5BLMP OK ASRock 775i65G OK (autodetected) ASRock 939A785GMH/128M OK ASRock A330GC OK ASRock A770CrossFire OK ASRock ALiveNF6G-DVI OK ASRock K7S41 OK (autodetected) ASRock K7VT4A+ BAD ASRock K8S8X OK ASRock M3A790GXH/128M OK ASRock P4i65GV OK (autodetected) ASUS A7N8X Deluxe OK ASUS A7N8X-E Deluxe OK ASUS A7V133 OK ASUS A7V333 OK (autodetected) ASUS A7V400-MX OK ASUS A7V600-X OK (autodetected) ASUS A7V8X OK (autodetected) ASUS A7V8X-MX OK ASUS A7V8X-MX SE OK (autodetected) ASUS A7V8X-X OK (autodetected) ASUS A8Jm OK (autodetected) ASUS A8N OK (autodetected) ASUS A8N-E OK ASUS A8N-LA (Nagami-GL8E) OK (autodetected) ASUS A8N-SLI OK ASUS A8N-SLI Premium OK ASUS A8N-VM CSM OK (autodetected) ASUS A8NE-FM/S OK ASUS A8V Deluxe OK ASUS A8V-E Deluxe OK ASUS A8V-E SE OK ASUS K8V OK ASUS K8V SE Deluxe OK ASUS K8V-X SE OK ASUS M2A-MX OK ASUS M2A-VM OK ASUS M2N32-SLI Deluxe OK ASUS M2N-E OK ASUS M2N-SLI Deluxe OK ASUS M2NBP-VM CSM OK (autodetected) ASUS M2NPV-VM OK ASUS M2V OK ASUS M2V-MX OK (autodetected) ASUS M3A76-CM OK ASUS M3A78-EM OK ASUS M4A785TD-M EVO OK ASUS M4A79T Deluxe OK ASUS M4A87TD/USB3 OK ASUS MEW-AM BAD ASUS MEW-VM BAD ASUS P2B OK ASUS P2B-D OK ASUS P2B-DS OK ASUS P2B-F OK ASUS P2B-N OK (autodetected) ASUS P2E-M OK ASUS P2L97-S OK ASUS P3B-F BAD ASUS P4B266 OK (autodetected) ASUS P4B266-LM OK (autodetected) ASUS P4B533-E OK (autodetected) ASUS P4C800-E Deluxe OK (autodetected) ASUS P4P800 OK (autodetected) ASUS P4P800-E Deluxe OK (autodetected) ASUS P4SC-E OK (autodetected) ASUS P4SD-LA OK (autodetected) ASUS P4S800-MX OK (autodetected) ASUS P5A OK -m asus:p5a ASUS P5B OK ASUS P5B-Deluxe OK ASUS P5BV-M BAD ASUS P5GC-MX/1333 OK ASUS P5GDC Deluxe OK (autodetected) ASUS P5KC OK ASUS P5L-MX OK ASUS P5GD1 Pro OK (autodetected) ASUS P5ND2-SLI Deluxe OK (autodetected) ASUS P5PE-VM OK (autodetected) ASUS P6T SE OK ASUS P6T Deluxe OK ASUS P6T Deluxe V2 OK ASUS Z8NA-D6C OK BCOM WinNET100 OK Biostar M6TBA BAD Biostar M7NCD Pro OK Biostar P4M80-M4 OK Biostar TA780G M2+ OK Boser HS-6637 BAD Congatec conga-X852 OK Dell OptiPlex GX1 OK (autodetected) Dell PowerEdge 1850 OK (autodetected) DFI 855GME-MGF BAD DFI Blood-Iron P35 T2RL OK Elitegroup GeForce6100SM-M OK Elitegroup K7S5A OK Elitegroup K7S6A OK Elitegroup K7VTA3 OK (autodetected) Elitegroup P6IWP-Fe OK Elitegroup P6VAP-A+ OK Elitegroup RS485M-M OK Emerson ATCA-7360 OK EPoX EP-8K5A2 OK (autodetected) EPoX EP-8RDA3+ OK (autodetected) EPoX EP-BX3 OK -m epox:ep-bx3 FIC VA-502 BAD Foxconn A6VMX OK Fujitsu-Siemens ESPRIMO P5915 OK GIGABYTE GA-2761GXDK OK GIGABYTE GA-6BXC OK GIGABYTE GA-6BXDU OK GIGABYTE GA-6IEM OK (autodetected) GIGABYTE GA-6ZMA OK GIGABYTE GA-MA785GMT-UD2H OK GIGABYTE GA-770TA-UD3 OK GIGABYTE GA-7DXR OK GIGABYTE GA-7VT600 OK GIGABYTE GA-7ZM OK (autodetected) GIGABYTE GA-8IRML OK (autodetected) GIGABYTE GA-8PE667 Ultra 2 OK (autodetected) GIGABYTE GA-965P-DS4 OK GIGABYTE GA-EP35-DS3L OK GIGABYTE GA-EX58-UD4P OK GIGABYTE GA-K8N-SLI OK (autodetected) GIGABYTE GA-K8N51GMF-9 OK (autodetected) GIGABYTE GA-M57SLI-S4 OK GIGABYTE GA-M61P-S3 OK GIGABYTE GA-MA69VM-S2 OK GIGABYTE GA-MA74GM-S2H (rev. 3.0) OK GIGABYTE GA-MA770T-UD3P OK GIGABYTE GA-MA78G-DS3H OK GIGABYTE GA-MA78GM-S2H OK GIGABYTE GA-MA78GPM-DS2H OK GIGABYTE GA-MA790FX-DQ6 OK GIGABYTE GA-MA790GP-DS4H OK HP ProLiant DL145 G3 OK -m hp:dl145_g3 HP ProLiant DL165 G6 OK -m hp:dl165_g6 HP Puffer2-UL8E OK (autodetected) HP Vectra VL400 OK (autodetected) HP Vectra VL420 SFF OK (autodetected) HP xw9400 OK (autodetected) IBASE MB899 OK -m ibase:mb899 IBM x3455 OK (autodetected) IEI PICOe-9452 OK Intel D201GLY OK (autodetected) Intel EP80759 OK Intel Foxhollow OK Intel Greencity OK Intel SE440BX-2 BAD (autodetected) IWILL DK8-HTX OK -m iwill:dk8_htx Jetway J7F4K1G5D-PB OK Kontron 986LCD-M OK -m kontron:986lcd-m Lex CV700A OK Mitac 6513WU OK (autodetected) MSI MS-6153 OK MSI MS-6156 OK MSI MS-6163 (MS-6163 Pro) OK (autodetected) MSI MS-6178 BAD MSI MS-6330 (K7T Turbo) OK MSI MS-6561 (745 Ultra) OK (autodetected) MSI MS-6570 (K7N2) OK MSI MS-6577 (Xenon) OK (autodetected) MSI MS-6590 (KT4 Ultra) OK (autodetected) MSI MS-6702E (K8T Neo2-F) OK (autodetected) MSI MS-6712 (KT4V) OK (autodetected) MSI MS-6787 (P4MAM-V/P4MAM-L) OK -m msi:ms6787 MSI MS-7005 (651M-L) OK (autodetected) MSI MS-7025 (K8N Neo2 Platinum) OK (autodetected) MSI MS-7046 OK (autodetected) MSI MS-7061 (KM4M-V/KM4AM-V) OK (autodetected) MSI MS-7065 OK MSI MS-7135 (K8N Neo3) OK -m msi:k8n-neo3 MSI MS-7168 (Orion) OK MSI MS-7207 (K8NGM2-L) OK (autodetected) MSI MS-7211 (PM8M3-V) OK MSI MS-7236 (945PL Neo3) OK MSI MS-7253 (K9VGM-V) OK MSI MS-7255 (P4M890M) OK MSI MS-7260, (K9N Neo) BAD MSI MS-7312 (K9MM-V) OK MSI MS-7345 (P35 Neo2-FIR) OK MSI MS-7368 (K9AG Neo2-Digital) OK MSI MS-7376 (K9A2 Platinum) OK MSI MS-7642 (890GXM-G65) OK NEC PowerMate 2000 OK Nokia IP530 OK (autodetected) PC Engines Alix.1c OK PC Engines Alix.2c2 OK PC Engines Alix.2c3 OK PC Engines Alix.3c3 OK PC Engines Alix.3d3 OK PC Engines WRAP.2E OK Portwell PEB-4700VLA OK RCA RM4100 OK Samsung Polaris 32 OK (autodetected) Shuttle AK31 OK -m shuttle:ak31 Shuttle AK38N OK (autodetected) Shuttle AV11V30 OK Shuttle FD37 OK Shuttle FN25 OK (autodetected) Shuttle X50/X50(B) OK Soyo SY-5VD BAD Soyo SY-6BA+ III OK Soyo SY-7VCA OK (autodetected) Sun Blade x6250 OK Sun Fire x4150 BAD Sun Fire x4200 BAD Sun Fire x4540 BAD Sun Fire x4600 BAD Supermicro H8QC8 OK Supermicro X8DTT-F OK T-Online S-100 OK Tekram P6Pro-A5 OK (autodetected) Termtek TK-3370 (Rev:2.5B) OK (autodetected) Thomson IP1000 OK TriGem Lomita OK Tyan S5375-1U (Tempest i5100X) OK Tyan S1846 (Tsunami ATX) OK Tyan S2466 (Tiger MPX) OK Tyan S2498 (Tomcat K7M) OK (autodetected) Tyan S2881 (Thunder K8SR) OK Tyan S2882 (Thunder K8S Pro) OK Tyan S2882-D (Thunder K8SD Pro) OK Tyan S2891 (Thunder K8SRE) OK Tyan S2892 (Thunder K8SE) OK Tyan S2895 (Thunder K8WE) OK Tyan S2915 (Thunder n6650W) OK Tyan S2915-E (Thunder n6650W) OK Tyan S2933 (Thunder n3600S) OK Tyan S3095 (Tomcat i945GM) OK Tyan S3992 (Thunder h2000M) OK Tyan S5180 (Toledo i965R) OK Tyan S5191 (Toledo i3000R) OK Tyan S5197 (Toledo i3010W) OK Tyan S5211 (Toledo i3210W) OK Tyan S5211-1U (Toledo i3200R) OK Tyan S5220 (Toledo q35T) OK Tyan S5375 (Tempest i5100X) OK Tyan S5376 (Tempest i5100W) OK Tyan S5377 (Tempest i5100T) OK Tyan S5382 (Tempest i5000PW) OK Tyan S5397 (Tempest i5400PW) OK VIA EPIA M/MII/... OK (autodetected) VIA EPIA SP OK VIA EPIA-CN OK VIA EPIA EK OK (autodetected) VIA EPIA-EX15000G OK VIA EPIA-LN OK VIA EPIA-M700 OK VIA EPIA-N/NL OK (autodetected) VIA EPIA-NX15000G OK VIA NAB74X0 OK VIA pc2500e OK VIA PC3500G OK VIA VB700X OK ZOTAC ZBOX HD-ID11 OK Known laptops (good: 2, bad: 7): Vendor: Board: Status: Required option: Acer Aspire 1520 OK Acer Aspire One BAD ASUS Eee PC 701 4G BAD Dell Latitude CPi A366XT BAD HP/Compaq nx9005 BAD HP/Compaq nx9010 BAD IBM/Lenovo Thinkpad T40p BAD IBM/Lenovo 240 BAD Lenovo 3000 V100 TF05Cxx OK Supported devices for the dummy programmer: Supported devices for the nic3com programmer: PCI devices: 3COM 3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX [10b7:9055] 3COM 3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4 [10b7:9001] (untested) 3COM 3C90xB: PCI 10BASE-T (TPO) [10b7:9004] 3COM 3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO) [10b7:9005] (untested) 3COM 3C90xB: PCI 10BASE-T/10BASE2 (TPC) [10b7:9006] (untested) 3COM 3C90xB: PCI 10BASE-FL [10b7:900a] (untested) 3COM 3C90xB: PCI 10BASE-FX [10b7:905a] (untested) 3COM 3C905B: Cyclone 10/100/BNC [10b7:9058] 3COM 3C905C: EtherLink 10/100 PCI (TX) [10b7:9200] 3COM 3C980C: EtherLink Server 10/100 PCI (TX) [10b7:9805] (untested) Supported devices for the nicrealtek programmer: PCI devices: Realtek RTL8139/8139C/8139C+ [10ec:8139] Supported devices for the nicsmc1211 programmer: PCI devices: SMC2 1211TX [1113:1211] Supported devices for the nicnatsemi programmer: PCI devices: National Semiconductor DP83815/DP83816 [100b:20] (untested) National Semiconductor DP83820 [100b:22] (untested) Supported devices for the gfxnvidia programmer: PCI devices: NVIDIA Mutara V08 [NV2] [10de:10] (untested) NVIDIA RIVA 128 [10de:18] (untested) NVIDIA RIVA TNT [10de:20] (untested) NVIDIA RIVA TNT2/TNT2 Pro [10de:28] (untested) NVIDIA RIVA TNT2 Ultra [10de:29] (untested) NVIDIA Vanta/Vanta LT [10de:2c] (untested) NVIDIA RIVA TNT2 Model 64/Model 64 Pro [10de:2d] NVIDIA Aladdin TNT2 [10de:a0] (untested) NVIDIA GeForce 256 [10de:100] (untested) NVIDIA GeForce DDR [10de:101] (untested) NVIDIA Quadro [10de:103] (untested) NVIDIA GeForce2 MX [10de:110] (untested) NVIDIA GeForce2 MX [10de:111] (untested) NVIDIA GeForce2 GO [10de:112] (untested) NVIDIA Quadro2 MXR [10de:113] (untested) NVIDIA GeForce2 GTS/Pro [10de:150] (untested) NVIDIA GeForce2 GTS [10de:151] (untested) NVIDIA GeForce2 Ultra [10de:152] (untested) NVIDIA Quadro2 Pro [10de:153] (untested) NVIDIA GeForce 3 nFX [10de:200] (untested) NVIDIA GeForce 3 nFX [10de:201] (untested) NVIDIA GeForce 3 nFX Ultra [10de:202] (untested) NVIDIA Quadro 3 DDC [10de:203] (untested) Supported devices for the drkaiser programmer: PCI devices: Dr. Kaiser PC-Waechter (Actel FPGA) [1803:5057] Supported devices for the satasii programmer: PCI devices: Silicon Image PCI0680 Ultra ATA-133 Host Ctrl [1095:680] Silicon Image SiI 3112 [SATALink/SATARaid] SATA Ctrl [1095:3112] Silicon Image SiI 3114 [SATALink/SATARaid] SATA Ctrl [1095:3114] Silicon Image SiI 3124 PCI-X SATA Ctrl [1095:3124] Silicon Image SiI 3132 SATA Raid II Ctrl [1095:3132] Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl [1095:3512] Supported devices for the atahpt programmer: PCI devices: Highpoint HPT366/368/370/370A/372/372N [1103:04] (untested) Highpoint HPT372A/372N [1103:05] (untested) Highpoint HPT302/302N [1103:06] (untested) Supported devices for the ft2232_spi programmer: USB devices: FTDI FT2232H [0403:6010] FTDI FT4232H [0403:6011] Amontec JTAGkey [0403:cff8] Supported devices for the serprog programmer: Supported devices for the buspirate_spi programmer: Supported devices for the dediprog programmer: Supported devices for the rayer_spi programmer: Supported devices for the nicintel_spi programmer: PCI devices: Intel 82571EB Gigabit Ethernet Controller [8086:105e] Intel 82541PI Gigabit Ethernet Controller [8086:107c] Intel 82572EI Gigabit Ethernet Controller [8086:10b9] Patch: Index: flashrom-list_supported_programmers/flash.h =================================================================== --- flashrom-list_supported_programmers/flash.h (Revision 1196) +++ flashrom-list_supported_programmers/flash.h (Arbeitskopie) @@ -200,6 +200,7 @@ char *strcat_realloc(char *dest, const char *src); void print_version(void); void print_banner(void); +void list_programmers_linebreak(int startcol, int cols, int paren); int selfcheck(void); int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it); Index: flashrom-list_supported_programmers/pcidev.c =================================================================== --- flashrom-list_supported_programmers/pcidev.c (Revision 1196) +++ flashrom-list_supported_programmers/pcidev.c (Arbeitskopie) @@ -132,6 +132,7 @@ { int i; + msg_pinfo("PCI devices:\n"); for (i = 0; devs[i].vendor_name != NULL; i++) { msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, Index: flashrom-list_supported_programmers/cli_classic.c =================================================================== --- flashrom-list_supported_programmers/cli_classic.c (Revision 1196) +++ flashrom-list_supported_programmers/cli_classic.c (Arbeitskopie) @@ -33,11 +33,6 @@ static void cli_classic_usage(const char *name) { - const char *pname; - int pnamelen; - int remaining = 0; - enum programmer p; - printf("Usage: flashrom [-n] [-V] [-f] [-h|-R|-L|" #if CONFIG_PRINT_WIKI == 1 "-z|" @@ -83,32 +78,9 @@ "in wiki syntax\n" #endif " -p | --programmer <name>[:<param>] specify the programmer " - "device"); + "device\n"); - for (p = 0; p < PROGRAMMER_INVALID; p++) { - pname = programmer_table[p].name; - pnamelen = strlen(pname); - if (remaining - pnamelen - 2 < 0) { - printf("\n "); - remaining = 43; - } else { - printf(" "); - remaining--; - } - if (p == 0) { - printf("("); - remaining--; - } - printf("%s", pname); - remaining -= pnamelen; - if (p < PROGRAMMER_INVALID - 1) { - printf(","); - remaining--; - } else { - printf(")\n"); - } - } - + list_programmers_linebreak(37, 80, 1); printf("\nYou can specify one of -h, -R, -L, " #if CONFIG_PRINT_WIKI == 1 "-z, " Index: flashrom-list_supported_programmers/atahpt.c =================================================================== --- flashrom-list_supported_programmers/atahpt.c (Revision 1196) +++ flashrom-list_supported_programmers/atahpt.c (Arbeitskopie) @@ -30,7 +30,7 @@ #define PCI_VENDOR_ID_HPT 0x1103 -struct pcidev_status ata_hpt[] = { +const struct pcidev_status ata_hpt[] = { {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, Index: flashrom-list_supported_programmers/ft2232_spi.c =================================================================== --- flashrom-list_supported_programmers/ft2232_spi.c (Revision 1196) +++ flashrom-list_supported_programmers/ft2232_spi.c (Arbeitskopie) @@ -346,6 +346,7 @@ { int i; + msg_pinfo("USB devices:\n"); for (i = 0; devs[i].vendor_name != NULL; i++) { msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, Index: flashrom-list_supported_programmers/flashrom.c =================================================================== --- flashrom-list_supported_programmers/flashrom.c (Revision 1196) +++ flashrom-list_supported_programmers/flashrom.c (Arbeitskopie) @@ -1332,6 +1332,46 @@ msg_ginfo("\n"); } +void list_programmers_linebreak(int startcol, int cols, int paren) +{ + const char *pname; + int pnamelen; + int remaining = 0; + int firstline = 1; + enum programmer p; + + for (p = 0; p < PROGRAMMER_INVALID; p++) { + pname = programmer_table[p].name; + pnamelen = strlen(pname); + if (remaining - pnamelen - 2 < 0) { + if (firstline) + firstline = 0; + else + printf("\n"); + for (int i = 0; i < startcol; i++) + printf(" "); + remaining = cols - startcol; + } else { + printf(" "); + remaining--; + } + if (paren && (p == 0)) { + printf("("); + remaining--; + } + printf("%s", pname); + remaining -= pnamelen; + if (p < PROGRAMMER_INVALID - 1) { + printf(","); + remaining--; + } else { + if (paren) + printf(")"); + printf("\n"); + } + } +} + void print_sysinfo(void) { #if HAVE_UTSNAME == 1 Index: flashrom-list_supported_programmers/print.c =================================================================== --- flashrom-list_supported_programmers/print.c (Revision 1196) +++ flashrom-list_supported_programmers/print.c (Arbeitskopie) @@ -223,50 +223,90 @@ void print_supported(void) { - print_supported_chips(); + print_supported_chips(); + + printf("\nSupported programmers:\n"); + list_programmers_linebreak(0, 80, 0); #if CONFIG_INTERNAL == 1 - print_supported_chipsets(); - print_supported_boards_helper(boards_known, "boards"); - print_supported_boards_helper(laptops_known, "laptops"); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_INTERNAL].name); + print_supported_chipsets(); + print_supported_boards_helper(boards_known, "boards"); + print_supported_boards_helper(laptops_known, "laptops"); #endif -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); +#if CONFIG_DUMMY == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DUMMY].name); + /* FIXME */ #endif #if CONFIG_NIC3COM == 1 - print_supported_pcidevs(nics_3com); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NIC3COM].name); + print_supported_pcidevs(nics_3com); #endif #if CONFIG_NICREALTEK == 1 - print_supported_pcidevs(nics_realtek); - print_supported_pcidevs(nics_realteksmc1211); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICREALTEK].name); + print_supported_pcidevs(nics_realtek); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICREALTEK2].name); + print_supported_pcidevs(nics_realteksmc1211); #endif #if CONFIG_NICNATSEMI == 1 - print_supported_pcidevs(nics_natsemi); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICNATSEMI].name); + print_supported_pcidevs(nics_natsemi); #endif #if CONFIG_GFXNVIDIA == 1 - print_supported_pcidevs(gfx_nvidia); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_GFXNVIDIA].name); + print_supported_pcidevs(gfx_nvidia); #endif #if CONFIG_DRKAISER == 1 - print_supported_pcidevs(drkaiser_pcidev); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DRKAISER].name); + print_supported_pcidevs(drkaiser_pcidev); #endif #if CONFIG_SATASII == 1 - print_supported_pcidevs(satas_sii); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATASII].name); + print_supported_pcidevs(satas_sii); #endif #if CONFIG_ATAHPT == 1 - print_supported_pcidevs(ata_hpt); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_ATAHPT].name); + print_supported_pcidevs(ata_hpt); #endif -#if CONFIG_NICINTEL_SPI == 1 - print_supported_pcidevs(nics_intel_spi); +#if CONFIG_FT2232_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_FT2232_SPI].name); + print_supported_usbdevs(devs_ft2232spi); #endif - -#if CONFIG_FT2232_SPI+CONFIG_DEDIPROG >= 1 - printf("\nSupported USB devices flashrom can use " - "as programmer:\n\n"); +#if CONFIG_SERPROG == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SERPROG].name); + /* FIXME */ #endif - -#if CONFIG_FT2232_SPI == 1 - print_supported_usbdevs(devs_ft2232spi); +#if CONFIG_BUSPIRATE_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_BUSPIRATE_SPI].name); + /* FIXME */ #endif +#if CONFIG_DEDIPROG == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DEDIPROG].name); + /* FIXME */ +#endif +#if CONFIG_RAYER_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_RAYER_SPI].name); + /* FIXME */ +#endif +#if CONFIG_NICINTEL_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICINTEL_SPI].name); + print_supported_pcidevs(nics_intel_spi); +#endif } #if CONFIG_INTERNAL == 1 -- http://www.hailfinger.org/

4 8

Re: [flashrom] [PATCH 6/8] use getpagesize() to determine physmap's length in nicintel_spi.c
by Carl-Daniel Hailfinger 26 Aug '12

26 Aug '12

Am 15.03.2011 16:29 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > Right, this is a really good idea. Could you patch physmap instead to round down the requested address and round up the end of the range? Then we could just request the amount we need without having to care in each programmer driver about page size. I think somewhere in flashrom we even have rounding code for physmap, it just needs to be moved from a driver to the generic physmap. Your code looks solid. > --- > nicintel_spi.c | 7 +++++-- > 1 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/nicintel_spi.c b/nicintel_spi.c > index 5a6e04d..811ed6e 100644 > --- a/nicintel_spi.c > +++ b/nicintel_spi.c > @@ -26,11 +26,14 @@ > */ > > #include<stdlib.h> > +#include<unistd.h> > #include "flash.h" > #include "programmer.h" > > #define PCI_VENDOR_ID_INTEL 0x8086 > > +#define MEMMAP_SIZE getpagesize() > + > #define EECD 0x10 > #define FLA 0x1c > > @@ -148,7 +151,7 @@ int nicintel_spi_init(void) > io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); > > nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", > - io_base_addr, 4096); > + io_base_addr, MEMMAP_SIZE); > tmp = pci_mmio_readl(nicintel_spibar + EECD); > tmp&= ~FLASH_WRITES_DISABLED; > tmp |= FLASH_WRITES_ENABLED; > @@ -173,7 +176,7 @@ int nicintel_spi_shutdown(void) > tmp |= FLASH_WRITES_DISABLED; > pci_mmio_writel(tmp, nicintel_spibar + EECD); > > - physunmap(nicintel_spibar, 4096); > + physunmap(nicintel_spibar, MEMMAP_SIZE); > pci_cleanup(pacc); > release_io_perms(); > > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 8

[PATCH 1/1] Simplify hwaccess.c
by Peter Lemenkov 26 Aug '12

26 Aug '12

This file is saturated with superfluous ifdefs arranged into several nested levels. This in turn adds additional complexity to process of adding another architecture. I re-arranged all ifdef blocks and killed duplicated function definitions. Also I added define(__amd64) to the list of x86-arches. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.c | 85 +++++++++++++++++++++-------------------------------------- 1 files changed, 30 insertions(+), 55 deletions(-) diff --git a/hwaccess.c b/hwaccess.c index 3a61e60..4e87642 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -29,30 +29,47 @@ #endif #include "flash.h" +#if !( defined(__i386__) || \ + defined(__x86_64__) || defined(__amd64) || \ + defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \ + defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)) +#error Unknown architecture +#endif + #if defined(__i386__) || defined(__x86_64__) +#if defined(__FreeBSD__) || defined(__DragonFly__) +int io_fd; +#endif +#endif -/* sync primitive is not needed because x86 uses uncached accesses - * which have a strongly ordered memory model. - */ static inline void sync_primitive(void) { -} - -#if defined(__FreeBSD__) || defined(__DragonFly__) -int io_fd; +/* sync primitive is needed only on PowerPC because + * x86 uses uncached accesses which have a strongly ordered memory model + * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model. + */ +#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); #endif +} void get_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__DJGPP__) /* We have full permissions by default. */ return; #else -#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#if defined (__sun) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#else +#else if (iopl(3) != 0) { #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" @@ -65,60 +82,18 @@ void get_io_perms(void) exit(1); } #endif +#endif } void release_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__FreeBSD__) || defined(__DragonFly__) close(io_fd); #endif -} - -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) - -static inline void sync_primitive(void) -{ - /* Prevent reordering and/or merging of reads/writes to hardware. - * Such reordering and/or merging would break device accesses which - * depend on the exact access order. - */ - asm("eieio" : : : "memory"); -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void release_io_perms(void) -{ -} - -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) - -/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses - * in mode 2 which has a strongly ordered memory model. - */ -static inline void sync_primitive(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void release_io_perms(void) -{ -} - -#else - -#error Unknown architecture - #endif +} void mmio_writeb(uint8_t val, void *addr) { -- 1.7.2.3

2 1

Re: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Reinauer 26 Aug '12

26 Aug '12

On 5/23/11 4:23 PM, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > chipset_enable.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 83b49ad..339c6bb 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > (old& (1<< 0)) ? "en" : "dis"); > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > - new = old | 1; > + /* > + * Quote from the 6 Series datasheet: > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > + * 1 = BIOS region SMM protection is enabled. > + * The BIOS Region is not writable unless all processors are in SMM." > + * In earlier chipsets this bit is reserved. */ > + if (old& (5<< 1)) { > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > + return -1; You might still be successful doing the write, in case the SMM handler does not enforce the protection, so maybe you should just print a warning but not return here? > + } > > + new = old | 1; > if (new == old) > return 0; >

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rtl8169 support - Final
by Jon Shadow 25 Aug '12

25 Aug '12

Fixed a few things. Still need someone to test it. Signed-off-by: Sergey Lichack <shadowpilot34(a)gmail.com>

4 3

[PATCH] board enable for DFI AD77
by Tadas Slotkus 25 Aug '12

25 Aug '12

Hello, Thank you people on the IRC for helping with assembler :) Happy Easter!

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flashrom November 2011