flashrom October 2011

flashrom@flashrom.org

49 participants
148 discussions

Flashrom report
by Piotr Czepek 27 Oct '11

27 Oct '11

Hello, I tried to re-flash VIA Epia mb with flashrom. Chipset is marked as untested, so I attached report for you. Just for test - I read flash image to file and I wrote it back. After reboot system is alive, so I think flasrom works fine with this mb ;) -- best regards piotr czepek

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[PATCH/bios_extract] Add support for Phoenix FFV layouts
by Joshua Roys 26 Oct '11

26 Oct '11

Hello, This patch was developed through some guesswork and by examining the debug output of "official" tools. Expected output looks like: Using file "../882.bin" (1024kB) Found Phoenix BIOS "PhoenixBIOS 4.0 Release 6.1 " Version "DEVEL972", created on 07/07/08 at 15:37:46. BCPSYS module offset is NULL. FFV modules: 5 [ 0]: (00000000-00080000) FED91FBA-D37B-4EEA-8729-2EF29FB37A78 _R00 (00000000-0000819A) 0000819A 00 02 oprom_00.rom _R01 (0000819A-0000FA31) 00007897 00 02 oprom_01.rom _H00 (0000FA31-00014EC3) 00005492 00 02 tcpa_H_00.rom _Q00 (00014EC3-000193B3) 000044F0 00 02 tcpa_Q_00.rom _A00 (000193B3-0001B034) 00001C81 00 02 acpi_00.rom _C00 (0001B038-0001C860) 00001828 02 01 update_00.rom _B05 (0001C860-00027F12) 0000B6B2 00 02 bioscode_05.rom _B02 (00027F12-00031351) 0000943F 00 02 bioscode_02.rom _B03 (00031351-00039238) 00007EE7 00 02 bioscode_03.rom _B00 (00039238-0003E135) 00004EFD 00 02 bioscode_00.rom _K00 (0003E135-00042B33) 000049FE 00 02 tcpa_K_00.rom _T00 (00042B33-000471A2) 0000466F 00 02 template_00.rom _E00 (000471A2-0004B1F0) 0000404E 00 02 setup_00.rom _S00 (0004B1F0-0004EE85) 00003C95 00 02 strings_00.rom _L01 (0004EE85-0005212D) 000032A8 00 02 logo_01.rom _B04 (0005212D-00054DDE) 00002CB1 00 02 bioscode_04.rom _B06 (00054DDE-00057826) 00002A48 00 02 bioscode_06.rom _B01 (00057826-000598EE) 000020C8 00 02 bioscode_01.rom _M00 (000598EE-0005AC93) 000013A5 00 02 miser_00.rom _D00 (0005AC93-0005B82E) 00000B9B 00 02 display_00.rom _Y00 (0005B82E-0005C1E2) 000009B4 00 02 _Y00.rom _L00 (0005C1E2-0005CAA3) 000008C1 00 02 logo_00.rom _G00 (0005CAA3-0005CF07) 00000464 00 02 decompcode_00.rom _A01 (0005CF07-0005CF7F) 00000078 00 02 acpi_01.rom _A02 (0005CF7F-0005CFD1) 00000052 00 02 acpi_02.rom volumeinfo.bin (0005CFD1-0005D031) 00000060 00 01 volumeinfo.bin GAP (0005D031-00080000) 00022FCF 00 F0 [ 1]: (00080000-00082000) FD21E8FD-2525-4A95-BB90-47EC5763FF9E ESCD [ 2]: (00082000-00090000) F6AE0F63-5F8C-4316-A2EA-76B9AF762756 Hole (raw code) [ 3]: (00090000-000F7000) FED91FBA-D37B-4EEA-8729-2EF29FB37A78 volumedir.bin2 (00090008-00090190) 00000188 42 01 volumedir.bin2 volumeinfo.bin (00090190-000901F0) 00000060 00 01 volumeinfo.bin GAP (000901F0-000DFFE8) 0004FDF8 00 F0 _$00 (000DFFE8-000E0004) 0000001C 40 01 _$00.rom _X01 (000E0008-000E9750) 00009748 40 01 romexec_01.rom GAP (000E9750-000ED6E8) 00003F98 00 F0 _X00 (000ED6E8-000F6000) 00008918 40 01 romexec_00.rom GAP (000F6000-000F7000) 00001000 00 F0 [ 4]: (000F7000-00100000) F6AE0F63-5F8C-4316-A2EA-76B9AF762756 Hole (raw code) Note that many newer Phoenix BIOSes have a trailer containing flash enable information, etc. which must be stripped off for this code to work. ESCD seems to be "Extended System Configuration Data" (dumped to ESCD.bin) and all holes are dumped to hole_%02x.bin. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com>

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[PATCH 2/2] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 26 Oct '11

26 Oct '11

Based on the new opaque programmer framework this patch adds support for Intel Hardware Sequencing on ICH8 and its successors. By default (or when setting the ich_spi_mode option to auto) the module tries to use swseq and only activates hwseq if need be: - if important opcodes are inaccessible due to lockdown - if more than one flash chip is attached. The other options (swseq, hwseq) select the respective mode (if possible). A general description of Hardware Sequencing can be found in this blog entry: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ TODO: adding real documentation when we have a directory for it Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 20 +++++ ichspi.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 283 insertions(+), 5 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index a8f4660..66cde4f 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -303,6 +303,26 @@ is the I/O port number (must be a multiple of 8). In the unlikely case flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug report so we can diagnose the problem. .sp +If you have an Intel chipset with an ICH8 or later southbridge with SPI flash +attached, and if a valid descriptor was written to it (e.g. by the vendor), the +chipset provides an alternative way to access the flash chip(s) named +.BR "Hardware Sequencing" . +It is much simpler than the normal access method (called +.BR "Software Sequencing" ")," +but does not allow the software to choose the SPI commands to be sent. +You can use the +.sp +.B " flashrom \-p internal:ich_spi_mode=value" +.sp +syntax where value can be +.BR auto ", " swseq " or " hwseq . +By default +.RB "(or when setting " ich_spi_mode=auto ) +the module tries to use swseq and only activates hwseq if need be (e.g. if +important opcodes are inaccessible due to lockdown; or if more than one flash +chip is attached). The other options (swseq, hwseq) select the respective mode +(if possible). +.sp If you have an Intel chipset with an ICH6 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the diff --git a/ichspi.c b/ichspi.c index bc03554..1d5dd34 100644 --- a/ichspi.c +++ b/ichspi.c @@ -575,6 +575,25 @@ static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) return 0; } +/* Returns true if the most important opcodes are accessible. */ +static int ich_check_opcodes() +{ + uint8_t ops[] = { + JEDEC_READ, + JEDEC_BYTE_PROGRAM, + JEDEC_RDSR, + 0 + }; + int i = 0; + while (ops[i] != 0) { + msg_pspew("checking for opcode 0x%02x\n", ops[i]); + if (find_opcode(curopcodes, ops[i]) == -1) + return 0; + i++; + } + return 1; +} + /* * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. @@ -1091,7 +1110,11 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -#if 0 +static struct hwseq_data { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq_data; + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { @@ -1160,7 +1183,184 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } return 0; } -#endif + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq_data.size_comp1 != 0) ? 2 : 1); + if (hwseq_data.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + flash->tested = TEST_OK_PREW; + return 1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, opaque_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, opaque_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} static int ich_spi_send_multicommand(struct spi_command *cmds) { @@ -1325,6 +1525,14 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct opaque_programmer opaque_programmer_ich_hwseq = { + .max_data_read = 64, + .max_data_write = 64, + .probe = ich_hwseq_probe, + .read = ich_hwseq_read, + .write = ich_hwseq_write, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1332,7 +1540,14 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int desc_valid = 0; + struct ich_descriptors desc = {{ 0 }}; + enum ich_spi_mode { + ich_auto, + ich_hwseq, + ich_swseq + } ich_spi_mode = ich_auto; switch (ich_generation) { case 7: @@ -1399,6 +1614,22 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case 9: case 10: default: /* Future version might behave the same */ + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for ich_spi_mode.\n"); + else if (arg) + msg_pinfo("Unknown argument for ich_spi_mode: %s\n", arg); + free(arg); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1484,14 +1715,41 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); if (desc_valid) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + !ich_check_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcodes are locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return 1; + } + hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); + hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + register_opaque_programmer(&opaque_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); } - register_spi_programmer(&spi_programmer_ich9); - ich_init_opcodes(); break; } -- 1.7.1

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[PATCH 1/2] ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes
by Stefan Tauner 26 Oct '11

26 Oct '11

This allows them to be called before programmer registration. --- i think it might be a good idea to get rid of the whole switch(spi_programmer->type) pattern and create a file-scope static ich_generation variable instead of using the type member and the ich_generation parameters everywhere. the type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar) - only available after registration, which we want to delay till the end of init. - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 44 +++++++++++++++++++++++++++----------------- 1 files changed, 27 insertions(+), 17 deletions(-) diff --git a/ichspi.c b/ichspi.c index afa420b..bc03554 100644 --- a/ichspi.c +++ b/ichspi.c @@ -225,8 +225,8 @@ static uint16_t REGREAD8(int X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); static int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(OPCODES * op); -static int program_opcodes(OPCODES *op, int enable_undo); +static int generate_opcodes(int ich_generation, OPCODES * op); +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); @@ -410,7 +410,18 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un int oppos=2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0); + switch (spi_programmer->type) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_VIA: + program_opcodes(7, curopcodes, 0); + break; + case SPI_CONTROLLER_ICH9: + program_opcodes(9, curopcodes, 0); + break; + default: + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } oppos = find_opcode(curopcodes, opcode); msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -443,7 +454,7 @@ static int find_preop(OPCODES *op, uint8_t preop) } /* Create a struct OPCODES based on what we find in the locked down chipset. */ -static int generate_opcodes(OPCODES * op) +static int generate_opcodes(int ich_generation, OPCODES * op) { int a; uint16_t preop, optype; @@ -498,7 +509,7 @@ static int generate_opcodes(OPCODES * op) return 0; } -static int program_opcodes(OPCODES *op, int enable_undo) +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) { uint8_t a; uint16_t preop, optype; @@ -529,9 +540,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case 7: /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH7_REG_PREOP); @@ -544,7 +554,10 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { rmmio_valw(ich_spibar + ICH9_REG_PREOP); @@ -557,9 +570,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; - default: - msg_perr("%s: unsupported chipset\n", __func__); - return -1; } return 0; @@ -652,7 +662,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) * * It should be called before ICH sends any spi command. */ -static int ich_init_opcodes(void) +static int ich_init_opcodes(int ich_generation) { int rc = 0; OPCODES *curopcodes_done; @@ -663,11 +673,11 @@ static int ich_init_opcodes(void) if (ichspi_lock) { msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(curopcodes_done); + rc = generate_opcodes(ich_generation, curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; - rc = program_opcodes(curopcodes_done, 1); + rc = program_opcodes(ich_generation, curopcodes_done, 1); } if (rc) { @@ -1343,6 +1353,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; + ich_init_opcodes(ich_generation); switch (ich_generation) { case 7: @@ -1383,7 +1394,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, } ich_set_bbar(ich_generation, 0); register_spi_programmer(&spi_programmer_ich7); - ich_init_opcodes(); break; case 8: case 9: @@ -1557,7 +1567,7 @@ int via_init_spi(struct pci_dev *dev) } ich_set_bbar(7, 0); - ich_init_opcodes(); + ich_init_opcodes(7); return 0; } -- 1.7.1

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[PATCH 0/2] ichspi 9.2
by Stefan Tauner 26 Oct '11

26 Oct '11

this requires the opaque programmer framework. i have also left out further but unchanged patches. please see the first patch for some discussion. Stefan Tauner (2): ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes ichspi: add support for Intel Hardware Sequencing flashrom.8 | 20 ++++ ichspi.c | 312 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 310 insertions(+), 22 deletions(-)

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Flashrom fails to write - Sun Ultra 40 M2
by Nick 25 Oct '11

25 Oct '11

DMI string system-manufacturer: "Sun Microsystems" DMI string system-product-name: "Sun Ultra 40 M2 Workstation" DMI string system-version: "11" DMI string baseboard-manufacturer: "Sun Microsystems" DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" DMI string baseboard-version: "50" nForce Pro 3600 / MCP55, SMSC SuperIO Verbose output when flashing coreboot - http://paste.flashrom.org/view.php?id=880 Verbose output when flashing original Sun BIOS image - http://paste.flashrom.org/view.php?id=881 lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 superiotool -deV output - http://paste.flashrom.org/view.php?id=884 Original Sun Ultra 40 M2 BIOS image - http://paste.flashrom.org/view.php?id=882

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Re: [flashrom] flashrom on NVIDIA MCP61 chipset
by Stefan Tauner 24 Oct '11

24 Oct '11

On Mon, 24 Oct 2011 21:57:07 +0700 Nurul Ikhsan <nurixx(a)gmail.com> wrote: > Dear Flashrom developer, > > I got messages that my chipset is untested, but I'm successfully > upgrade my BIOS using flashrom. > Thank you for your hardwork and this great tool. I really appreciate it. > Within this email I also attach Verbose output. > Hello, Thanks for your report! I have marked the abit NF-M2S as supported and will commit that later together with other small changes. I am not entirely sure about the chipset so i left it alone for now... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] `flashrom -V' for ASUS M5A99X EVO
by Stefan Tauner 24 Oct '11

24 Oct '11

On Sun, 23 Oct 2011 19:27:13 +0200 Bernhard Urban <lewurm(a)gmail.com> wrote: > Hi, > > I successfully upgraded the firmware of my ASUS M5A99X EVO board [1] > to version 0705 with flashrom. > > > Thanks, > Bernhard > > [1]: http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ Hello Bernhard, Thanks for your report! I have marked the board as support and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom on NVIDIA MCP61 chipset
by Nurul Ikhsan 24 Oct '11

24 Oct '11

Dear Flashrom developer, I got messages that my chipset is untested, but I'm successfully upgrade my BIOS using flashrom. Thank you for your hardwork and this great tool. I really appreciate it. Within this email I also attach Verbose output. Thanks, Regards, Ikhsan.

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Re: [flashrom] [PATCH 1/5] Add opaque programmer registration infrastructure.
by Carl-Daniel Hailfinger 23 Oct '11

23 Oct '11

Am 21.10.2011 00:39 schrieb Stefan Tauner: > An opaque programmer does not allow direct flash access and only > offers abstract probe/read/erase/write methods. > Examples are ICH Hardware Sequencing and direct firmware uploads. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Thanks to Stefan for posting this while I had no mail access. This is indeed my patch, and I hereby confirm authorship. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom October 2011