flashrom January 2011

flashrom@flashrom.org

55 participants
135 discussions

[PATCH] Revert MMIO space writes on shutdown as needed.
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Revert MMIO space writes on shutdown as needed. Reversible MMIO space writes now use rmmio_write*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mmio_shutdown_restore/hwaccess.c =================================================================== --- flashrom-mmio_shutdown_restore/hwaccess.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/hwaccess.c (Arbeitskopie) @@ -184,3 +184,71 @@ { return le_to_cpu32(mmio_readl(addr)); } + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +void undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writeb(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writeb(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} Index: flashrom-mmio_shutdown_restore/ichspi.c =================================================================== --- flashrom-mmio_shutdown_restore/ichspi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/ichspi.c (Arbeitskopie) @@ -382,16 +382,16 @@ switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - REGWRITE16(ICH7_REG_PREOP, preop); - REGWRITE16(ICH7_REG_OPTYPE, optype); - REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH7_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH7_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: - REGWRITE16(ICH9_REG_PREOP, preop); - REGWRITE16(ICH9_REG_OPTYPE, optype); - REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH9_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH9_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; default: msg_perr("%s: unsupported chipset\n", __func__); @@ -409,16 +409,20 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, ich_spibar + 0x50); + rmmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, ich_spibar + 0xA0); + rmmio_writel(minaddr, ich_spibar + 0xA0); ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; Index: flashrom-mmio_shutdown_restore/nicintel_spi.c =================================================================== --- flashrom-mmio_shutdown_restore/nicintel_spi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/nicintel_spi.c (Arbeitskopie) @@ -149,6 +149,7 @@ nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -168,6 +169,7 @@ { uint32_t tmp; + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; Index: flashrom-mmio_shutdown_restore/programmer.h =================================================================== --- flashrom-mmio_shutdown_restore/programmer.h (Revision 1234) +++ flashrom-mmio_shutdown_restore/programmer.h (Arbeitskopie) @@ -311,6 +311,9 @@ #define pci_mmio_readb mmio_le_readb #define pci_mmio_readw mmio_le_readw #define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); /* programmer.c */ int noop_shutdown(void); -- http://www.hailfinger.org/

2 4

[PATCH] ICH SPI paranoid error handling
by Carl-Daniel Hailfinger 24 Apr '11

24 Apr '11

Some people have reported that running flashrom on Ibex Peak (after patching in the PCI ID 0x8086:0x3b02) will not only hang flashrom during the first RES/REMS command issued, it may even cause the machine to lock up or issue a hard reset. We suspect this is because RES/REMS are commands with an address, whereas RDID does not take an address and works fine. Our current ICH SPI code doesn't really follow the datasheets and uses lots of hope instead of error checking in the wrong places. This patch will fail early and fail often if something is odd. As such, merge is not recommended, but running it should definitely generating interesting results on all Intel chipsets with SPI, and especially on Ibex Peak. It probably won't fix the hang, but it should be pretty good at spewing an error before the machine dies. Untested. Highly likely to explode on VIA chipsets which use the same interface but have docs only under NDA. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c =================================================================== --- flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c (Revision 1052) +++ flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c (Arbeitskopie) @@ -579,8 +579,20 @@ mmio_readl(spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + + tmp = mmio_readl(spibar + 0x90); + msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + msg_pdbg("AEL %i, ", (tmp >> 4) & 1); + msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); + msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); + msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + if (tmp & (1 << 3)) { + msg_pdbg("Clearing SSFS.FCERR\n"); + mmio_writeb(1 << 3, spibar + 0x90); + } + tmp >>= 8; + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", Index: flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c =================================================================== --- flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c (Revision 1052) +++ flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c (Arbeitskopie) @@ -413,6 +413,12 @@ write_cmd = 1; } + /* FIXME: This should be a time-limited while loop. */ + if (REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) { + msg_perr("Error: Totally unhandled SCIP condition!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -486,18 +492,22 @@ /* write it */ REGWRITE16(ICH7_REG_SPIC, temp16); - /* wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { msg_perr("timeout\n"); + return 1; } /* FIXME: make sure we do not needlessly cause transaction errors. */ - if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + if (REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + REGWRITE16(ICH7_REG_SPIS, SPIS_FCERR); return 1; } @@ -532,6 +542,12 @@ write_cmd = 1; } + /* FIXME: This should be a time-limited while loop. */ + if (REGREAD16(ICH9_REG_SSFS) & SSFS_SCIP) { + msg_perr("Error: Totally unhandled SCIP condition!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -605,18 +621,23 @@ /* write it */ REGWRITE32(ICH9_REG_SSFS, temp32); - /*wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { msg_perr("timeout\n"); + return 1; } /* FIXME make sure we do not needlessly cause transaction errors. */ - if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + if (REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + //FIXME: Really REGWRITE8? + REGWRITE8(ICH9_REG_SSFS, SSFS_FCERR); return 1; } -- http://www.hailfinger.org/

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#4: pciutils-dev and Mac OSX
by flashrom 22 Apr '11

22 Apr '11

#4: pciutils-dev and Mac OSX -------------------------------------+------------------------------- Reporter: roufignouf@… | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: flashrom 0.9.2 Component: flashrom | Version: Keywords: | Dependencies: Patch Status: there is no patch | -------------------------------------+------------------------------- Hi, I try to build flashrom on my macbook but i can't find pciutils-dev for it could you help me ? {{{ Checking for a C compiler... ld: warning: in /System/Library/Frameworks//DirectIO.framework/DirectIO, file was built for i386 which is not the architecture being linked (x86_64) found. Checking for libpci headers... not found. Please install libpci headers (package pciutils-devel). See README for more information. make: *** [pciutils] Error 1 }}} -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/4> flashrom <http://www.flashrom.org/>

1 1

[PATCH] Initial ITE IT8500 EC support (second try)
by David Hendricks 08 Mar '11

08 Mar '11

A few months ago, ITE open sourced the initial IT8500 EC patch on this mailing list ( http://www.flashrom.org/pipermail/flashrom/2010-August/004382.html) so that we could check it in to the Chromium OS branch. It didn't quite make it upstream, and has been updated since then. The attached patch basically does the same thing and has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the attached "select_bbs.sh" script (Install iotools ( http://code.google.com/p/iotools/) before using select_bbs). We worked around this in the Chromium OS branch by adding a bus argument to the programmer option, ie "flashrom -p internal:bus=lpc". - It is very important to disable power management daemons before running Flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. - Carl-Daniel pointed out that the code might ignore the result of it87 init code. I've attempted to mitigate this in the patch (see internal.c), but I think it's just the symptom of a larger problem with how we detect and initialize IO bridges, and should probably be dealt with in a separate patch. *Here is the text from the original patch submission: The attached patch adds generalized support for IT8500/IT8502 embedded controllers. The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc.* Signed-off-by: David Hendricks <dhendrix(a)google.com> (The original patch also included a sign-off from Yung-chieh Lo @ Google and Donald Huang @ ITE). -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] rtl8169 support - Final
by Mathias Krause 07 Mar '11

07 Mar '11

On 05.01.2011 18:36, Jon Shadow wrote: > I stole that static from nic3com.c file I suppose. > But there its used in nic3com_init() and nic3com_shutdown(), so needs to be a global variable. Regards, Mathias

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[PATCH] Add Asus P4P800-VM board to board_enable.c table.
by Diego Elio Pettenò 06 Mar '11

06 Mar '11

Only list the memory controller PCI IDs because the only other subsystem mentioned is used by network and sound interfaces both of which can be turned off in BIOS. Tested on a board rev 1.85. Signed-off-by: Diego Elio Pettenò <flameeyes(a)gmail.com> --- flashrom v0.9.3-runknown on Linux 2.6.35-std161-i386 (i686), built with libpci 3.1.4, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1327M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 869 us, 10000 myus = 7692 us, 4 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M. by More String" DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P4P800-VM" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found chipset "Intel ICH5/ICH5R", enabling flash write... chipset PCI ID is 8086:24d0, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Disabling flash write protection for board "ASUS P4P800-VM"... Intel ICH LPC Bridge: Raising GPIO21. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. 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Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for Spansion S25FL032A, 4096 KB: skipped. Probing for Spansion S25FL064A, 8192 KB: skipped. Probing for SST SST25VF010.REMS, 128 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xc8, id2 0x51, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. Restoring PCI config space for 00:1f:0 reg 0x4e --- board_enable.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index d09923a..c63669c 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1452,6 +1452,7 @@ static int intel_ich_gpio19_raise(void) * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R + * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R @@ -1917,6 +1918,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0, 0, 0, 0, NULL, NULL, NULL, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, -- 1.7.3.4

5 8

Success: Gigabyte GA-MA780G-UD3H
by Bernhard Geier 06 Mar '11

06 Mar '11

I was able to upgrade a Gigabyte GA-MA780G-UD3H with flashrom 0.9.2+r114 (from Debian Testing, AM64) to the newest BIOS. No additional options were required, everything worked as it should.

4 4

[PATCH] Add support for "ST M25PX16" chip.
by Carl Worth 06 Mar '11

06 Mar '11

This was created by simply copying the M25PX32 block and verifying with the M25PX16 datasheet which values needed to be changed. (The only changes are the model_id and the 4 size-related fields). Also, this commit sets the new M25PX16 as having write support tested, (where the M25PX32 does not). This is after running successful write and verify operations to 4 different M25PX16 chips with a Dediprog SF100. Signed-off-by: Carl Worth <carl.d.worth(a)intel.com> --- flashchips.c | 29 +++++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/flashchips.c b/flashchips.c index e7a2223..0b84ae1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6269,6 +6269,35 @@ struct flashchip flashchips[] = { { .vendor = "ST", + .name = "M25PX16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25PX16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 512 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "ST", .name = "M25PX32", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 6504edf..bbdb5ae 100644 --- a/flashchips.h +++ b/flashchips.h @@ -531,6 +531,7 @@ #define ST_M25P32 0x2016 #define ST_M25P64 0x2017 #define ST_M25P128 0x2018 +#define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 #define ST_M25PX64 0x7117 #define ST_M25PE10 0x8011 -- 1.7.2.3

3 2

[patch] make EPoX EP-8NPA7I board enable actually work
by Jonathan A. Kollasch 27 Feb '11

27 Feb '11

The OEM BIOS on the EPoX EP-8PA7I clears byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

3 2

Re: [flashrom] [PATCH] Initial ITE IT8500 EC support
by Carl-Daniel Hailfinger 22 Feb '11

22 Feb '11

Dear Donald, thanks a lot for your patch. I will review it as soon as possible, and I will work with you to ensure a speedy integration of the patch. Right now we are in the process of finalizing the flashrom 0.9.3 release, and such a big new feature needs to be reviewed in depth before being merged, so it won't be part of 0.9.3. I'm very confident this patch will be fully integrated before flashrom 0.9.4. On 09.08.2010 05:06, Donald.Huang(a)ite.com.tw wrote: > The attached patch adds generalized support for IT8500/IT8502 embedded controllers. > The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. > It was tested for IT8500E on a Chrome OS platform and may require modification > depending on ODM/OEM customization and EC firmware version. > > Signed-off by: Donald Huang (donald.huang(a)ite.com.tw) > Signed-off by: Yung-chieh Lo (yjlou(a)google.com) > Signed-off by: David Hendricks (dhendrix(a)google.com) > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

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flashrom January 2011