Hi all,
I have figured out how to enable flashing on the ASUS TUSI-M board as
the first step to porting coreboot to it. The reverse engineering
guide worked very well here. After poring through the disassembled
listing, I found the below command to be the missing piece of the
puzzle. flashrom already have most of the board enable sequence
covered.
# i2cset 0 0x77 0 0xed
(0xed is found by issuing "i2cdump 0 0x77". Only byte 0 matters.)
After issuing this command, flashrom found my flash chip.
There are also two additional operations done by the factory BIOS board enable:
Clear the CPU cache and set 0xF8000 to 0xFFFFF to uncacheable by
tweaking the MTRR.
Disable read shadowing of 0xE0000 to 0xFFFFF in the SIS630 chipset.
I am not sure if these should be included when writing the board enable code.
Command line log follows at end of this email. flashrom -V after
issuing this command attached.
After P5A and P3B-F, this is the third ASUS board that needs SMBus
access to enable flashing. Yet I'm finding SMBus read/write support
kind of lacking. How should we go about improving this?
Thanks
Keith
---
root@sissy:/usr/src/flashrom-0.9.3# i2cset 0 0x77 0 0xef
Warning: no size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will write to device file /dev/i2c-0, chip address 0x77, data address
0x00, data 0xef, mode byte.
You have five seconds to reconsider and press CTRL-C!
Value 0xef written, readback matched
root@sissy:/usr/src/flashrom-0.9.3# ./flashrom
flashrom v0.9.3-r1205 on Linux 2.6.36 (i686), built with libpci 3.1.3,
GCC 4.3.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found ITE Super I/O, ID 0x8705.
Found chipset "SiS 630", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
root@sissy:/usr/src/flashrom-0.9.3# i2cset 0 0x77 0 0xed
Warning: no size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will write to device file /dev/i2c-0, chip address 0x77, data address
0x00, data 0xed, mode byte.
You have five seconds to reconsider and press CTRL-C!
Value 0xed written, readback matched
root@sissy:/usr/src/flashrom-0.9.3# ./flashrom
flashrom v0.9.3-r1205 on Linux 2.6.36 (i686), built with libpci 3.1.3,
GCC 4.3.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found ITE Super I/O, ID 0x8705.
Found chipset "SiS 630", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
Found chip "SST SST39SF020A" (256 KB, Parallel) at physical address 0xfffc0000.
No operations were specified.
root@sissy:/usr/src/flashrom-0.9.3#
Allow setting delay loop speed from the command line.
This can speed up delay loop calibration somewhat (some time is lost to
delay loop verification).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-specifydelayloop/cli_classic.c
===================================================================
--- flashrom-specifydelayloop/cli_classic.c (Revision 1250)
+++ flashrom-specifydelayloop/cli_classic.c (Arbeitskopie)
@@ -351,9 +351,6 @@
flash = NULL;
}
- /* FIXME: Delay calibration should happen in programmer code. */
- myusec_calibrate_delay();
-
if (programmer_init(pparam)) {
fprintf(stderr, "Error: Programmer initialization failed.\n");
exit(1);
Index: flashrom-specifydelayloop/flashrom.8
===================================================================
--- flashrom-specifydelayloop/flashrom.8 (Revision 1250)
+++ flashrom-specifydelayloop/flashrom.8 (Arbeitskopie)
@@ -220,6 +220,21 @@
programmers use a key/value interface in which the key and value is separated
by an equal sign and different pairs are separated by a comma or a colon.
.TP
+.B Common parameters for all programmers
+The initial delay loop calibration of flashrom usually takes more than one
+second, and in case of a machine with high system load or variable CPU speed
+flashrom may repeat the delay loop calibration a few times until it is satisfied
+with the precision or until it gives up. You can speed up the delay loop
+calibration using
+.sp
+.B " flashrom \-p programmername:delayloops=value"
+.sp
+where value is the number of loops per microsecond (Mloops per second) reported
+during the last flashrom run in verbose mode. flashrom will use the specified
+value as basis for the delay loop calibration, so do not worry if it is not the
+exact value. You can expect an 1 GHz CPU to have delayloop values between 250
+and 2000.
+.TP
.BR "internal " programmer
Some mainboards require to run mainboard specific code to enable flash erase
and write support (and probe support on old systems with parallel flash).
Index: flashrom-specifydelayloop/flashrom.c
===================================================================
--- flashrom-specifydelayloop/flashrom.c (Revision 1250)
+++ flashrom-specifydelayloop/flashrom.c (Arbeitskopie)
@@ -527,6 +527,10 @@
programmer_param = param;
msg_pdbg("Initializing %s programmer\n",
programmer_table[programmer].name);
+
+ /* FIXME: Delay calibration should be programmer specific. */
+ myusec_calibrate_delay();
+
ret = programmer_table[programmer].init();
if (programmer_param && strlen(programmer_param)) {
msg_perr("Unhandled programmer parameters: %s\n",
Index: flashrom-specifydelayloop/udelay.c
===================================================================
--- flashrom-specifydelayloop/udelay.c (Revision 1250)
+++ flashrom-specifydelayloop/udelay.c (Arbeitskopie)
@@ -26,6 +26,7 @@
#include <stdlib.h>
#include <limits.h>
#include "flash.h"
+#include "programmer.h"
/* loops per microsecond */
static unsigned long micro = 1;
@@ -89,6 +90,7 @@
unsigned long count = 1000;
unsigned long timeusec, resolution;
int i, tries = 0;
+ char *delayloops;
msg_pinfo("Calibrating delay loop... ");
resolution = measure_os_delay_resolution();
@@ -98,6 +100,18 @@
msg_pinfo("OS timer resolution is unusable. ");
}
+ delayloops = extract_programmer_param("delayloops");
+ if (delayloops) {
+ micro = strtoul(delayloops, NULL, 0);
+ free(delayloops);
+ if (micro == 0) {
+ /* The delay calibration function is void, we have to
+ * recover instead of throwing an error.
+ */
+ micro = 1;
+ }
+ }
+
recalibrate:
count = 1000;
while (1) {
--
http://www.hailfinger.org/
Hello! Need Help!
BIOS: ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5P800/P5P80014.zip
flashrom -w P5P80014.ROM
flashrom v0.9.3-r1205 on FreeBSD 7.4-PRERELEASE (i386), built with libpci 3.1.7, GCC 4.2.1 20070719 [FreeBSD], little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000.
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00004560! Expected=0xff, Read=0x4c, failed byte count from 0x00004000-0x00004fff: 0xa7f
ERASE FAILED!
ERASE FAILED at 0x00004560! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0000ffff: 0xb9df
ERASE FAILED!
ERASE FAILED at 0x00004560! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0007ffff: 0x78040
ERASE FAILED!
FAILED!
ERASE FAILED!
FAILED!
Your flash chip is in an unknown state.
Get help on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom(a)flashrom.org with FAILED: your board name in the subject line!
-------------------------------------------------------------------------------
DO NOT REBOOT OR POWEROFF!
Hi Shane,
thanks for your report.
Auf 12.01.2011 21:58, sdbarnes(a)rockwellcollins.com schrieb:
> I can read succcessfully read the flash ROM contents:
> [...]
> I can also successfully write the same flash ROM contents:
> [...]
> However, when I try to write a new flash ROM (provided by the motherboard
> manufacturer), the erase function fails:
>
> [root]#./flashrom -w i3700n1t.bin
>
> flashrom v0.9.3-r1250 on Linux 2.6.24.7 (i686), built with libpci 2.2.9,
> GCC 4.1.2 20070925 (Red Hat 4.1.2-33), little endian
> Calibrating delay loop... OK.
> No coreboot table found.
> Invalid string keyword: chassis-type
>
That is very odd. Maybe your dmidecode is too old. Could you upgrade it
so we have a chance to get a better log?
> dmidecode execution unsucessfull - continuing without DMI info
> Found chipset "Intel ICH7M", enabling flash write... OK.
> This chipset supports the following protocols: FWH.
> Found chip "Winbond W39V040FC" (512 KB, FWH) at physical address
> 0xfff80000.
> ===
> This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
>
Hm OK, so at least PROBE works.
> Erasing and writing flash chip...
> ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x3ec
> ERASE FAILED!
> ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0007ffff: 0x5437e
> ERASE FAILED!
> Done.
> Verifying flash... VERIFY FAILED at 0x00000000! Expected=0xed, Read=0x49,
> failed byte count from 0x00000000-0x0007ffff: 0x13ea
> Your flash chip is in an unknown state.
>
This part of the log is very strange. Can you run "make distclean",
rebuild flashrom, and retry the write in verbose mode? AFAICS the
messages above can not be triggered in that combination if you try to
write, but they may happen if you try to erase.
To rule out a bug in flashrom, the verbose write log would be very
appreciated.
Oh, and please try to write the old image again to make sure the machine
still comes up after a reboot.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
localhost2 bios # flashrom -w /home/roger/src/coreboot-tyan_s1832dl/coreboot/build/coreboot.rom
flashrom v0.9.3-r1205 on Linux 2.6.37-gentoo (i686), built with libpci 3.1.4, GCC 4.4.4, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK.
This chipset supports the following protocols: Parallel.
Found chip "SST SST39SF040" (512 KB, Parallel) at physical address 0xfff80000.
Note: If the following flash access fails, try -m <vendor>:<mainboard>.
Writing flash chip... Erasing flash chip... SUCCESS.
Programming page: DONE!ss: 0x0007f000
COMPLETE.
Verifying flash... VERIFY FAILED at 0x0003fc9e! Expected=0xff, Read=0x4f, failed byte count from 0x00000000-0x0007ffff: 0x231f7
Your flash chip is in an unknown state.
Get help on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom(a)flashrom.org with FAILED: your board name in the subject line!
-------------------------------------------------------------------------------
DO NOT REBOOT OR POWEROFF!
DIGI-KEY Part No. SST39SF040-70-4C-PHE
IC FLASH MPF 4MBIT (512KBYTES) 70NS 32DIP
This is flashing using a Tyan S1832DL board
00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03)
...
00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02)
(... am I getting this right, flashrom uses the ISA bridge to write to flash part?)
--
Roger
http://rogerx.freeshell.org/
Hi,
you reported a flashrom issue on IRC and uploaded your logs to
http://paste.flashrom.org/view.php?id=299
Could you please retry with current flashrom (at least 0.9.3, preferably
0.9.3-r1250) and report success or failure? The flashrom version you
were using is extremely old, it does not even have a version number.
Current flashrom should detect the chipset without problems, and verbose
mode should tell you a lot about the flash read/write permissions of
your mainboard.
Please reply with the output of
"flashrom -V"
from a current flashrom binary or upload the output to
http://paste.flashrom.org/ and include the link in your mail.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Dear,
I need help in the following:
I wanted to update my flash with a bitmap fullscreen logo.
The system runs ubuntu 10.04 with real-time rtai.
I red the flash with flashrom (attached: originalflash.bin) and copy
file to a windows PC.
(Reading flash completed successfully)
I run Award Bios editor 1.0, which successfully realized all
parameters of flash file.
I modified bios with a bitmap used CBROM196 (attached: modifiedflash.bin).
I run Award Bios editor, which realized valid the new flash file as well.
I tried to download the modified file, but got the messages bellow.
I red the flash out, checked with Award bios editor, and flash file
was the old one (originalflash.bin).
I downloaded originalflash.bin, and got the same message bellow. I red
out, checked with Award bios editor, and it was the old flash file
again (originalflash.bin).
Verify to originalflash.bin works as well.
It seems, that read works properly, and write does nothing.
But still, Im a bit afraid to restart the computer.
What do you thing? (I leave computer on until answer)
(Less important question: How should I modify flash? )
Thank you for help,
Bence Kovacs
generalmechatronics@generalmechatronics-desktop:~$ sudo flashrom -r
"originalflash.bin"
flashrom v0.9.1-r946
No coreboot table found.
Found chipset "Intel ICH6/ICH6R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Calibrating delay loop... OK.
Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)flashrom.org if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Reading flash... done.
generalmechatronics@generalmechatronics-desktop:~$ sudo flashrom -w
"modifiedflash.bin"
flashrom v0.9.1-r946
No coreboot table found.
Found chipset "Intel ICH6/ICH6R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Calibrating delay loop... OK.
Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)flashrom.org if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash chip... ERASE FAILED at
0x00000000! Expected=0xff, Read=0x49, failed byte count from
0x00000000-0x00000fff: 0x4ab
ERASE FAILED!
ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte
count from 0x00000000-0x0000ffff: 0xca1
ERASE FAILED!
ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte
count from 0x00000000-0x0007ffff: 0x65f4b
ERASE FAILED!
FAILED!
ERASE FAILED!
FAILED!
Your flash chip is in an unknown state.
Get help on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom(a)flashrom.org!
A non-text attachment has been removed: originalflash.bin
It is available at http://paste.flashrom.org/view.php?id=297
A non-text attachment has been removed: modifiedflash.bin
It is available at http://paste.flashrom.org/view.php?id=298