REPORT: ASUS TUSI-M - flashrom

8 Jan 2011


      Hi all,
I have figured out how to enable flashing on the ASUS TUSI-M board as
the first step to porting coreboot to it. The reverse engineering
guide worked very well here. After poring through the disassembled
listing, I found the below command to be the missing piece of the
puzzle. flashrom already have most of the board enable sequence
covered.
# i2cset 0 0x77 0 0xed
(0xed is found by issuing "i2cdump 0 0x77". Only byte 0 matters.)
After issuing this command, flashrom found my flash chip.
There are also two additional operations done by the factory BIOS board enable:
Clear the CPU cache and set 0xF8000 to 0xFFFFF to uncacheable by
tweaking the MTRR.
Disable read shadowing of 0xE0000 to 0xFFFFF in the SIS630 chipset.
I am not sure if these should be included when writing the board enable code.
Command line log follows at end of this email. flashrom -V after
issuing this command attached.
After P5A and P3B-F, this is the third ASUS board that needs SMBus
access to enable flashing. Yet I'm finding SMBus read/write support
kind of lacking. How should we go about improving this?
Thanks
Keith
---
root@sissy:/usr/src/flashrom-0.9.3# i2cset 0 0x77 0 0xef
Warning: no size specified (using byte-data access)
  WARNING! This program can confuse your I2C bus, cause data loss and worse!
  I will write to device file /dev/i2c-0, chip address 0x77, data address
  0x00, data 0xef, mode byte.
  You have five seconds to reconsider and press CTRL-C!
Value 0xef written, readback matched
root@sissy:/usr/src/flashrom-0.9.3# ./flashrom
flashrom v0.9.3-r1205 on Linux 2.6.36 (i686), built with libpci 3.1.3,
GCC 4.3.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found ITE Super I/O, ID 0x8705.
Found chipset "SiS 630", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
root@sissy:/usr/src/flashrom-0.9.3# i2cset 0 0x77 0 0xed
Warning: no size specified (using byte-data access)
  WARNING! This program can confuse your I2C bus, cause data loss and worse!
  I will write to device file /dev/i2c-0, chip address 0x77, data address
  0x00, data 0xed, mode byte.
  You have five seconds to reconsider and press CTRL-C!
Value 0xed written, readback matched
root@sissy:/usr/src/flashrom-0.9.3# ./flashrom
flashrom v0.9.3-r1205 on Linux 2.6.36 (i686), built with libpci 3.1.3,
GCC 4.3.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
No coreboot table found.
Found ITE Super I/O, ID 0x8705.
Found chipset "SiS 630", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
Found chip "SST SST39SF020A" (256 KB, Parallel) at physical address 0xfffc0000.
No operations were specified.
root@sissy:/usr/src/flashrom-0.9.3#