flashrom August 2010

flashrom@flashrom.org

77 participants
209 discussions

[patch] update README
by Idwer Vollering 05 Oct '10

05 Oct '10

Update README to list al the needed rpm files [1] and update the download location of csdpmi. [1]: http://www.flashrom.org/pipermail/flashrom/2010-May/003116.html --- Index: README =================================================================== --- README (revision 1022) +++ README (working copy) @@ -85,8 +85,8 @@ Get RPMs of the cross compiler from the DJGPP site and install them: djcross-binutils-2.19.1-10ap.i386.rpm - djcross-gcc-tools-4.4.1-1ap.i686.rpm djcross-gcc-4.3.2-8ap.i686.rpm + djcrx-2.04pre_20090725-13ap.i386.rpm Download pciutils 3.1.5 and apply http://assembler.cz/flashrom/pciutils.patch Download and compile http://assembler.cz/flashrom/libgetopt/ Compile pciutils, see README.DJGPP for instructions. @@ -98,7 +98,7 @@ or (above settings hardcoded) make djgpp-dos You might have to add WARNERROR=no to the make command line. - To run flashrom.exe, download http://clio.rice.edu/djgpp/csdpmi7b.zip and + To run flashrom.exe, download http://homer.rice.edu/~sandmann/cwsdpmi/csdpmi7b.zip and make sure CWSDPMI.EXE is in the current directory. Installation

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[PATCH] Make Bus Pirate init more robust, speed up flashing
by Carl-Daniel Hailfinger 05 Oct '10

05 Oct '10

This is a combination of two patches. Patch 1: Thanks to Johannes Sjölund for reporting that the Bus Pirate init could not deal with a Bus Pirate which is already in binary Bitbang mode. This is caused by a combination of the slowness of the Bus Pirate, the slowness of USB and a fast serial port flush routine which just flushes the buffer contents and does not wait until data arrival stops. Make the Bus Pirate init more robust by running the flush command 10 times with 1.5 ms delay in between. This code development was sponsored by Mattias Mattsson. Thanks! Tested a few dozen times, should work reliably. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Patch 2: Thanks to Ian Lesnet for adding a new SPI mode to the Bus Pirate which is specifically designed for flashrom. It has the potential to speed up reads and writes a lot. This patch implements flashrom support for the new SPI mode in a hopefully backward compatible way. Not for merge. The Bus Pirate interface has not been finalized yet, and this patch should help testing if the interface works as designed. No significant speedups expected yet because the code still uses the old small block sizes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-buspirate_newcommands/buspirate_spi.c =================================================================== --- flashrom-buspirate_newcommands/buspirate_spi.c (Revision 1130) +++ flashrom-buspirate_newcommands/buspirate_spi.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <string.h> #include <stdlib.h> #include <ctype.h> +#include <unistd.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -45,6 +46,8 @@ #define sp_flush_incoming(...) 0 #endif +static int buspirate_interface_version; + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -130,7 +133,13 @@ return ret; free(dev); - /* This is the brute force version, but it should work. */ + /* This is the brute force version, but it should work. + * It is guaranteed to fail if a previous flashrom run was aborted + * during a write with the new SPI commands in firmware v4.6 because + * that firmware may wait for up to 4096 bytes of input before + * responding to 0x00 again. The obvious workaround may cause startup + * penalties of more than one second. + */ for (i = 0; i < 19; i++) { /* Enter raw bitbang mode */ buf[0] = 0x00; @@ -141,6 +150,20 @@ /* Read any response and discard it. */ sp_flush_incoming(); } + /* USB is slow. The Bus Pirate is even slower. Apparently the flush + * action above is too fast or too early. Some stuff still remains in + * the pipe after the flush above, and one additional flush is not + * sufficient either. Use a 1.5 ms delay inside the loop to make + * mostly sure that at least one USB frame had time to arrive. + * Looping only 5 times is not sufficient and causes the + * ocassional failure. + * Folding the delay into the loop above is not reliable either. + */ + for (i = 0; i < 10; i++) { + usleep(1500); + /* Read any response and discard it. */ + sp_flush_incoming(); + } /* Enter raw bitbang mode */ buf[0] = 0x00; ret = buspirate_sendrecv(buf, 1, 5); @@ -148,6 +171,8 @@ return ret; if (memcmp(buf, "BBIO", 4)) { msg_perr("Entering raw bitbang mode failed!\n"); + msg_pdbg("Got %02x%02x%02x%02x%02x\n", + buf[0], buf[1], buf[2], buf[3], buf[4]); return 1; } msg_pdbg("Raw bitbang mode version %c\n", buf[4]); @@ -159,8 +184,12 @@ /* Enter raw SPI mode */ buf[0] = 0x01; ret = buspirate_sendrecv(buf, 1, 4); + if (ret) + return ret; if (memcmp(buf, "SPI", 3)) { msg_perr("Entering raw SPI mode failed!\n"); + msg_pdbg("Got %02x%02x%02x%02x\n", + buf[0], buf[1], buf[2], buf[3]); return 1; } msg_pdbg("Raw SPI mode version %c\n", buf[3]); @@ -210,6 +239,34 @@ return 1; } + /* Test combined SPI write/read, length 0. */ + buf[0] = 0x04; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + buf[4] = 0; + ret = buspirate_sendrecv(buf, 5, 1); + if (ret) + return 1; + if (buf[0] != 0x01) { + msg_pdbg("SPI command set v2 not available, using old commands " + "present in firmware vX.Y or later\n"); + + /* FIXME: Check the error code? */ + /* We sent 4 bytes of 0x00, so we expect 4 BBIO1 responses. */ + buspirate_sendrecv(buf, 0, 4 * 5); + + /* Enter raw SPI mode again. */ + buf[0] = 0x01; + /* FIXME: Check the error code? */ + buspirate_sendrecv(buf, 1, 4); + + buspirate_interface_version = 1; + } else { + msg_pdbg("Using SPI command set v2.\n"); + buspirate_interface_version = 2; + } + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_BUSPIRATE; @@ -251,12 +308,56 @@ return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +int buspirate_spi_send_command_v2(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; int i = 0, ret = 0; + if (writecnt > 4096 || readcnt > 4096 || (readcnt + writecnt) > 4096) + return SPI_INVALID_LENGTH; + + /* 5 bytes extra for command, writelen, readlen. + * 1 byte extra for Ack/Nack. + */ + buf = realloc(buf, max(writecnt + 5, readcnt + 1)); + if (!buf) { + msg_perr("Out of memory!\n"); + exit(1); // -1 + } + + /* Combined SPI write/read. */ + buf[i++] = 0x04; + buf[i++] = (writecnt >> 8) & 0xff; + buf[i++] = writecnt & 0xff; + buf[i++] = (readcnt >> 8) & 0xff; + buf[i++] = readcnt & 0xff; + memcpy(buf + i, writearr, writecnt); + + ret = buspirate_sendrecv(buf, i + writecnt, 1 + readcnt); + + if (ret) { + msg_perr("Bus Pirate communication error!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[0] != 0x01) { + msg_perr("Protocol error while sending SPI write/read!\n"); + return SPI_GENERIC_ERROR; + } + + /* Skip Ack. */ + memcpy(readarr, buf + 1, readcnt); + + return ret; +} + +int buspirate_spi_send_command_v1(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *buf = NULL; + int i = 0, ret = 0; + if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) return SPI_INVALID_LENGTH; @@ -307,6 +408,17 @@ return ret; } +int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + switch (buspirate_interface_version) { + case 2: + return buspirate_spi_send_command_v2(writecnt, readcnt, writearr, readarr); + default: + return buspirate_spi_send_command_v1(writecnt, readcnt, writearr, readarr); + } +} + int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_read_chunked(flash, buf, start, len, 12); Index: flashrom-buspirate_newcommands/serial.c =================================================================== --- flashrom-buspirate_newcommands/serial.c (Revision 1130) +++ flashrom-buspirate_newcommands/serial.c (Arbeitskopie) @@ -200,8 +200,10 @@ #else tmp = write(sp_fd, buf, writecnt); #endif - if (tmp == -1) + if (tmp == -1) { + msg_perr("Serial port write error!\n"); return 1; + } if (!tmp) msg_pdbg("Empty write\n"); writecnt -= tmp; @@ -221,8 +223,10 @@ #else tmp = read(sp_fd, buf, readcnt); #endif - if (tmp == -1) + if (tmp == -1) { + msg_perr("Serial port read error!\n"); return 1; + } if (!tmp) msg_pdbg("Empty read\n"); readcnt -= tmp; -- http://www.hailfinger.org/

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[PATCH] Add Nvidia nForce MCP6x/MCP7x series SPI flashing support
by Carl-Daniel Hailfinger 27 Sep '10

27 Sep '10

Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashing support. This code is totally untested and may fry your flash chip, explode mysteriously and abduct your dog. Do NOT try to read/write/erase with this code until we know that it behaves correctly. Logs from "flashrom -V" on all newer Nvidia nForce chipsets appreciated. This patch depends on my RayeR SPIPGM patch I sent a few minutes ago, Message-ID: <4BFDBD86.1020100(a)gmx.net> and available at http://patchwork.coreboot.org/patch/1401/ The code will be compiled in automatically if the internal programmer is enabled (which is the default). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> diff generated by interdiff diff -u flashrom-bitbang_spi_rayer/flash.h flashrom-bitbang_spi_nvidia_mcp/flash.h --- flashrom-bitbang_spi_rayer/flash.h (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/flash.h (Arbeitskopie) @@ -132,6 +132,11 @@ #if RAYER_BITBANG_SPI_SUPPORT == 1 BITBANG_SPI_MASTER_RAYER, #endif +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + BITBANG_SPI_MASTER_MCP, +#endif +#endif BITBANG_SPI_INVALID /* This must always be the last entry. */ }; @@ -527,6 +532,18 @@ int rayer_bitbang_get_miso(void); #endif +/* mcp6x_spi.c */ +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) +extern void *mcp6x_spibar; +int mcp6x_spi_init(void); +void mcp6x_bitbang_set_cs(int val); +void mcp6x_bitbang_set_sck(int val); +void mcp6x_bitbang_set_mosi(int val); +int mcp6x_bitbang_get_miso(void); +#endif +#endif + /* bitbang_spi.c */ extern int bitbang_spi_half_period; extern const struct bitbang_spi_master_entry bitbang_spi_master_table[]; @@ -633,6 +650,7 @@ SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, + SPI_CONTROLLER_MCP6X_BITBANG, #endif #endif #if FT2232_SPI_SUPPORT == 1 diff -u flashrom-bitbang_spi_rayer/spi25.c flashrom-bitbang_spi_nvidia_mcp/spi25.c --- flashrom-bitbang_spi_rayer/spi25.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/spi25.c (Arbeitskopie) @@ -178,6 +178,7 @@ case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: + case SPI_CONTROLLER_MCP6X_BITBANG: #endif #endif #if FT2232_SPI_SUPPORT == 1 diff -u flashrom-bitbang_spi_rayer/bitbang_spi.c flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c --- flashrom-bitbang_spi_rayer/bitbang_spi.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/bitbang_spi.c (Arbeitskopie) @@ -40,6 +40,18 @@ .get_miso = rayer_bitbang_get_miso, }, #endif + +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + { + .set_cs = mcp6x_bitbang_set_cs, + .set_sck = mcp6x_bitbang_set_sck, + .set_mosi = mcp6x_bitbang_set_mosi, + .get_miso = mcp6x_bitbang_get_miso, + }, +#endif +#endif + {}, /* This entry corresponds to SPI_BITBANG_INVALID. */ }; diff -u flashrom-bitbang_spi_rayer/spi.c flashrom-bitbang_spi_nvidia_mcp/spi.c --- flashrom-bitbang_spi_rayer/spi.c (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/spi.c (Arbeitskopie) @@ -84,6 +84,13 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, + + { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, #endif #endif diff -u flashrom-bitbang_spi_rayer/Makefile flashrom-bitbang_spi_nvidia_mcp/Makefile --- flashrom-bitbang_spi_rayer/Makefile (Arbeitskopie) +++ flashrom-bitbang_spi_nvidia_mcp/Makefile (Arbeitskopie) @@ -92,8 +92,12 @@ ifeq ($(CONFIG_RAYER_BITBANG_SPI), yes) CONFIG_BITBANG_SPI = yes else +ifeq ($(CONFIG_INTERNAL), yes) +CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no endif +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -133,7 +137,7 @@ FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif only in patch2: unchanged: --- flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Revision 1013) +++ flashrom-bitbang_spi_nvidia_mcp/chipset_enable.c (Arbeitskopie) @@ -1063,10 +1063,8 @@ { int ret = 0; uint8_t val; - uint16_t status; char *busname; - uint32_t mcp_spibaraddr; - void *mcp_spibar; + uint32_t mcp6x_spibaraddr; struct pci_dev *smbusdev; msg_pinfo("This chipset is not really supported yet. Guesswork...\n"); @@ -1115,40 +1113,33 @@ smbusdev->bus, smbusdev->dev, smbusdev->func); /* Locate the BAR where the SPI interface lives. */ - mcp_spibaraddr = pci_read_long(smbusdev, 0x74); - msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr); + mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74); + msg_pdbg("SPI BAR is at 0x%08x, ", mcp6x_spibaraddr); /* We hope this has native alignment. We know the SPI interface (well, * a set of GPIOs that is connected to SPI flash) is at offset 0x530, * so we expect a size of at least 0x800. Clear the lower bits. * It is entirely possible that the BAR is 64k big and the low bits are * reserved for an entirely different purpose. */ - mcp_spibaraddr &= ~0x7ff; - msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr); + mcp6x_spibaraddr &= ~0x7ff; + msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp6x_spibaraddr); /* Accessing a NULL pointer BAR is evil. Don't do it. */ - if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { + if (mcp6x_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) { /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ - mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544); + mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544); -/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */ -#define MCP67_SPI_CS (1 << 1) -#define MCP67_SPI_SCK (1 << 2) -#define MCP67_SPI_MOSI (1 << 3) -#define MCP67_SPI_MISO (1 << 4) -#define MCP67_SPI_ENABLE (1 << 0) -#define MCP67_SPI_IDLE (1 << 8) - - status = mmio_readw(mcp_spibar + 0x530); - msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", - status, status & 0x1, (status >> 8) & 0x1); + if (mcp6x_spi_init()) + ret = 1; +#if 0 /* FIXME: Remove the physunmap once the SPI driver exists. */ - physunmap(mcp_spibar, 0x544); - } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { + physunmap(mcp6x_spibar, 0x544); +#endif + } else if (!mcp6x_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is invalid.\n"); buses_supported &= ~CHIP_BUSTYPE_SPI; ret = 1; - } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { + } else if (mcp6x_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) { msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently" " doesn't have SPI enabled.\n"); } else { @@ -1186,8 +1177,7 @@ result = enable_flash_mcp55(dev, name); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); @@ -1212,8 +1202,7 @@ msg_pinfo("LPC on this chipset is not supported yet.\n"); break; case CHIP_BUSTYPE_SPI: - msg_pinfo("SPI on this chipset is not supported yet.\n"); - buses_supported = CHIP_BUSTYPE_NONE; + msg_perr("SPI on this chipset is WIP. DO NOT USE!\n"); break; default: msg_pinfo("Something went wrong with bus type detection.\n"); only in patch2: unchanged: --- flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) +++ flashrom-bitbang_spi_nvidia_mcp/mcp6x_spi.c (Revision 0) @@ -0,0 +1,132 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller. + * Based on clean room reverse engineered docs from + * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html + * created by Michael Karcher. + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <stdint.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ + +/* Guessed. */ +#define MCP6X_SPI_CS 1 +#define MCP6X_SPI_SCK 2 +#define MCP6X_SPI_MOSI 3 +#define MCP6X_SPI_MISO 4 +#define MCP6X_SPI_ENABLE 0 +#define MCP6X_SPI_IDLE 8 + +void *mcp6x_spibar = NULL; + +void mcp6x_request_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte |= 1 << MCP6X_SPI_ENABLE; + mmio_writeb(byte, mcp6x_spibar + 0x530); + + /* Wait until we are allowed to use the SPI bus. */ + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_IDLE))) ; +} + +void mcp6x_release_spibus(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_ENABLE); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_cs(int val) +{ + uint8_t byte; + + /* Requesting and releasing the SPI bus is handled in here to allow the + * chipset to use its own SPI engine for native reads. + */ + if (val == 1) + mcp6x_request_spibus(); + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_CS); + byte |= (val << MCP6X_SPI_CS); + mmio_writeb(byte, mcp6x_spibar + 0x530); + + if (val == 0) + mcp6x_release_spibus(); +} + +void mcp6x_bitbang_set_sck(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_SCK); + byte |= (val << MCP6X_SPI_SCK); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +void mcp6x_bitbang_set_mosi(int val) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte &= ~(1 << MCP6X_SPI_MOSI); + byte |= (val << MCP6X_SPI_MOSI); + mmio_writeb(byte, mcp6x_spibar + 0x530); +} + +int mcp6x_bitbang_get_miso(void) +{ + uint8_t byte; + + byte = mmio_readb(mcp6x_spibar + 0x530); + byte = (byte >> MCP6X_SPI_MISO) & 0x1; + return byte; +} + +int mcp6x_spi_init(void) +{ + uint16_t status; + + status = mmio_readw(mcp6x_spibar + 0x530); + msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n", + status, (status >> MCP6X_SPI_ENABLE) & 0x1, + (status >> MCP6X_SPI_IDLE) & 0x1); + + if (bitbang_spi_init()) + return 1; + spi_controller = SPI_CONTROLLER_MCP6X_BITBANG; + + return 0; +} + +#endif -- http://www.hailfinger.org/

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[PATCH]libpayload support
by Patrick Georgi 26 Sep '10

26 Sep '10

Hi, attached patches implement libpayload support and improve life for DOS based flashrom, too: 1.physmap-allow-NULL changes the physmap* behaviour to use -1 as error code instead of 0. That way, 1:1 mapped memory can be supported properly because 0 is not a magic number anymore. -1 on the other hand is a rather unlikely memory offset, so that should be safe. 2.support-libpayload adds libpayload implementations of various functions and data structures and improves compatibility to libpayload by #ifdefing out various include statements, as well as file access related code. Some parts look weird, but I had to work around name clashes (eg. msr_t) flashrom.c is mostly unchanged, but my local changes beyond those in the patch aren't suitable for upstream. Any flashrom-as-payload project requires some entirely new frontend, but I hope that some libflashrom-type effort benefits from these patches and simplifies any frontend work later on. Both patches are Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Regards, Patrick

2 2

[PATCH] Make Bus Pirate init more robust
by Carl-Daniel Hailfinger 17 Sep '10

17 Sep '10

Thanks to Johannes Sjölund for reporting that the Bus Pirate init could not deal with a Bus Pirate which is already in binary Bitbang mode. This is caused by a combination of the slowness of the Bus Pirate, the slowness of USB and a fast serial port flush routine which just flushes the buffer contents and does not wait until data arrival stops. Make the Bus Pirate init more robust by running the flush command 10 times with 1.5 ms delay in between. This code development was sponsored by Mattias Mattsson. Thanks! Tested a few dozen times, should work reliably. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-buspirate_resilient_init/buspirate_spi.c =================================================================== --- flashrom-buspirate_resilient_init/buspirate_spi.c (Revision 1099) +++ flashrom-buspirate_resilient_init/buspirate_spi.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <string.h> #include <stdlib.h> #include <ctype.h> +#include <unistd.h> #include "flash.h" #include "chipdrivers.h" #include "spi.h" @@ -140,6 +141,20 @@ /* Read any response and discard it. */ sp_flush_incoming(); } + /* USB is slow. The Bus Pirate is even slower. Apparently the flush + * action above is too fast or too early. Some stuff still remains in + * the pipe after the flush above, and one additional flush is not + * sufficient either. Use a 1.5 ms delay inside the loop to make + * mostly sure that at least one USB frame had time to arrive. + * Looping only 5 times is not sufficient and causes the + * ocassional failure. + * Folding the delay into the loop above is not reliable either. + */ + for (i = 0; i < 10; i++) { + usleep(1500); + /* Read any response and discard it. */ + sp_flush_incoming(); + } /* Enter raw bitbang mode */ buf[0] = 0x00; ret = buspirate_sendrecv(buf, 1, 5); @@ -147,6 +162,8 @@ return ret; if (memcmp(buf, "BBIO", 4)) { msg_perr("Entering raw bitbang mode failed!\n"); + msg_pdbg("Got %02x%02x%02x%02x%02x\n", + buf[0], buf[1], buf[2], buf[3], buf[4]); return 1; } msg_pdbg("Raw bitbang mode version %c\n", buf[4]); @@ -158,8 +175,12 @@ /* Enter raw SPI mode */ buf[0] = 0x01; ret = buspirate_sendrecv(buf, 1, 4); + if (ret) + return ret; if (memcmp(buf, "SPI", 3)) { msg_perr("Entering raw SPI mode failed!\n"); + msg_pdbg("Got %02x%02x%02x%02x\n", + buf[0], buf[1], buf[2], buf[3]); return 1; } msg_pdbg("Raw SPI mode version %c\n", buf[3]); Index: flashrom-buspirate_resilient_init/serial.c =================================================================== --- flashrom-buspirate_resilient_init/serial.c (Revision 1099) +++ flashrom-buspirate_resilient_init/serial.c (Arbeitskopie) @@ -199,8 +199,10 @@ #else tmp = write(sp_fd, buf, writecnt); #endif - if (tmp == -1) + if (tmp == -1) { + msg_perr("Serial port write error!\n"); return 1; + } if (!tmp) msg_pdbg("Empty write\n"); writecnt -= tmp; @@ -220,8 +222,10 @@ #else tmp = read(sp_fd, buf, readcnt); #endif - if (tmp == -1) + if (tmp == -1) { + msg_perr("Serial port read error!\n"); return 1; + } if (!tmp) msg_pdbg("Empty read\n"); readcnt -= tmp; -- http://www.hailfinger.org/

2 3

[PATCH 1/1] Mark Gigabyte GA-6ETXDR as UNSUPPORTED so far
by Peter Lemenkov 16 Sep '10

16 Sep '10

Here is a short flashrom log: dev ~ # ~petro/flashrom/flashrom flashrom v0.9.2-r1025 on Linux 2.6.18-164.15.1.el5 (i686), built with libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. dev ~ # Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- print.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/print.c b/print.c index bf75990..bfe2dcb 100644 --- a/print.c +++ b/print.c @@ -334,6 +334,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-2761GXDK", 1, "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…", NULL), B("GIGABYTE", "GA-6BXC", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1445", NULL), B("GIGABYTE", "GA-6BXDU", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1429", NULL), + B("GIGABYTE", "GA-6ETXDR", 0, "http://www.gigabyte.com/products/product-page.aspx?pid=992", NULL), B("GIGABYTE", "GA-6ZMA", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1541", NULL), B("GIGABYTE", "GA-7VT600", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), -- 1.7.0.1

5 15

Re: [flashrom] [PATCH] MSI MS-6787 board enable
by Michael Karcher 15 Sep '10

15 Sep '10

Am Montag, den 16.08.2010, 16:29 +0400 schrieb Jon Shadow: > Fixed again Thanks for your patch. After a test by "Swift Geek", this is Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Please send your latest iteration of the patch, quoting my Ack and repeating your Sign-off to the flashrom mailing list, so we have everything (patch, Ack, Signoff) in one place. I added flashrom(a)flashrom.org back into Cc:, so if you use reply-to-all, this will hit the list. Regards, Michael Karcher

4 6

Tyan 2915 and 2915-E --- test report
by Axel Bergerhoff 15 Sep '10

15 Sep '10

Hi, tried several Tyan 2915 (S2915A2NRF) and S2915-E (S2915A2NRF-E) all with the same result. #1 Using flashrom -r to get the PROM's content and comparing that with the appropriate version from Tyan's website gives differences in all cases. #2 Took a 2915 (S2915A2NRF) and flashed with the DOS tool offered by Tyan (phlash16.exe) to BIOS revision 3.00 (2915v300.rom). Then reread with flashrom -r and compared both files - a bunch of differencies again. I attached the outputs of flashrom, lspci, and superiotool for this board. Regards, Axel // ----- * flashrom -V flashrom v0.9.2-r1096 on Linux 2.6.23.13-SMP64 (x86_64), built with libpci 2.2.9, GCC 4.2.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 931M loops per second, 10 myus = 11 us, 100 myus = 110 us, 1000 myus = 1058 us, 10000 myus = 9993 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Tyan Computer Corporation " DMI string system-product-name: "MCP55 " DMI string system-version: "REFERENCE" DMI string baseboard-manufacturer: "Tyan Computer Corporation " DMI string baseboard-product-name: "S2915 " DMI string baseboard-version: "REFERENCE" DMI string chassis-type: "Main Server Chassis" Found chipset "NVIDIA MCP55", enabling flash write... chipset PCI ID is 10de:0364, OK. This chipset supports the following protocols: Non-SPI. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004BV/BE-T, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-B, 512 KB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/CV/CE-T, 512 KB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Found chip "SST SST49LF080A" (1024 KB, LPC) at physical address 0xfff00000. Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x70, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0x0a, id2 0xc0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No operations were specified. * lspci -nnvvxxx 00:00.0 RAM memory [0500]: nVidia Corporation MCP55 Memory Controller [10de:0369] (rev a2) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [dc] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 69 03 06 00 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00 40: f1 10 15 29 08 dc e0 01 22 00 11 11 d0 00 00 00 50: 23 06 7f 00 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 0a 00 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 fa 00 64 0e 02 00 00 00 7f 00 00 00 90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 80 00 0f 0f d0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8 e0: 00 00 e0 fe 00 00 00 00 00 00 80 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation MCP55 LPC Bridge [10de:0364] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: I/O ports at 1c00 [size=128] 00: de 10 64 03 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 01 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: f1 10 15 29 00 00 d0 fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f9 ff 70: 10 00 ff ff c5 80 00 00 00 00 44 19 03 80 20 10 80: 09 b0 00 c6 da 12 00 40 ff 00 00 00 ff 00 00 00 90: ff 7f 00 00 00 00 00 00 21 47 95 86 ef cd ab 00 a0: 03 00 10 11 00 38 00 00 00 06 8f 06 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 1d 00 fc fd 03 00 30 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:01.1 SMBus [0c05]: nVidia Corporation MCP55 SMBus [10de:0368] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 255 Region 0: I/O ports at 2000 [size=64] Region 4: I/O ports at 2440 [size=64] Region 5: I/O ports at 2400 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus 00: de 10 68 03 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 01 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 41 24 00 00 01 24 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 01 00 00 40: f1 10 15 29 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 10 00 00 01 14 00 00 01 18 00 00 00 00 00 00 70: 01 00 00 00 00 00 04 a0 00 00 00 00 01 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 00 01 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 64 15 05 00 a5 21 50 03 80 30 80 00 77 44 44 11 f0: 5a ff 5f 3f 00 00 00 c0 10 00 00 00 00 00 00 00 00:02.0 USB Controller [0c03]: nVidia Corporation MCP55 USB Controller [10de:036c] (rev a1) (prog-if 10 [OHCI]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 10 Region 0: Memory at a0004000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 6c 03 07 00 b0 00 a1 10 03 0c 00 00 80 00 10: 00 40 00 a0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: f1 10 15 29 01 00 02 fe 00 00 00 00 00 00 00 00 50: c0 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:02.1 USB Controller [0c03]: nVidia Corporation MCP55 USB Controller [10de:036d] (rev a2) (prog-if 20 [EHCI]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 11 Region 0: Memory at a0005000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: de 10 6d 03 06 00 b0 00 a2 20 03 0c 00 00 80 00 10: 00 50 00 a0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 03 01 40: f1 10 15 29 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 3f 01 00 00 00 00 70: 00 00 08 00 00 10 20 80 89 3d b6 22 77 25 04 00 80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00 90: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 80 00 00 00 00 00 00 00 00 b0: 22 11 00 33 44 00 00 00 ff 03 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:04.0 IDE interface [0101]: nVidia Corporation MCP55 IDE [10de:036e] (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at 2480 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: AMD_IDE 00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 24 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: f1 10 15 29 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 00 00 00 00 00 00 a8 a8 a8 20 2f 00 ff 20 60: 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 12 00 00 00 00 00 00 00 00:05.0 IDE interface [0101]: nVidia Corporation MCP55 SATA Controller [10de:037f] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 24d0 [size=8] Region 1: I/O ports at 24c4 [size=4] Region 2: I/O ports at 24c8 [size=8] Region 3: I/O ports at 24c0 [size=4] Region 4: I/O ports at 2490 [size=16] Region 5: Memory at a0006000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: sata_nv 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: d1 24 00 00 c5 24 00 00 c9 24 00 00 c1 24 00 00 20: 91 24 00 00 00 60 00 a0 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 01 03 01 40: f1 10 15 29 01 b0 02 00 00 00 00 00 00 00 00 00 50: 0b 68 08 80 00 00 00 00 00 1d 00 00 00 60 09 00 60: 00 00 00 00 41 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 80 80: 00 00 00 00 5f de ff fb 00 00 c8 10 ff 7b ff ff 90: 00 00 bf 3d 00 00 00 00 06 00 06 10 7f 03 01 01 a0: 12 0a 00 00 40 00 00 00 00 00 00 00 23 31 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 0a 00 02 03 42 00 00 00 00 00 00 00 00 10 80 00 e0: 0a 00 02 03 42 00 00 00 00 00 00 00 0f 00 70 00 f0: 00 00 00 00 00 00 00 00 12 00 0c 00 00 00 00 00 00:05.1 IDE interface [0101]: nVidia Corporation MCP55 SATA Controller [10de:037f] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 18 Region 0: I/O ports at 24e8 [size=8] Region 1: I/O ports at 24dc [size=4] Region 2: I/O ports at 24e0 [size=8] Region 3: I/O ports at 24d8 [size=4] Region 4: I/O ports at 24a0 [size=16] Region 5: Memory at a0007000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: sata_nv 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: e9 24 00 00 dd 24 00 00 e1 24 00 00 d9 24 00 00 20: a1 24 00 00 00 70 00 a0 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 02 03 01 40: f1 10 15 29 01 b0 02 00 00 00 00 00 00 00 00 00 50: 0b 68 08 80 00 00 00 00 00 1d 00 00 00 60 09 00 60: 00 00 00 00 41 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 80 80: 00 00 00 00 ff 3f ff f7 00 00 eb 1c cf ff ff ff 90: 00 00 55 3f 00 00 00 00 06 00 06 10 7f 03 01 01 a0: 12 0a 00 00 40 00 00 00 00 00 00 00 33 31 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 0a 00 02 03 42 00 00 00 00 00 00 00 00 48 20 01 e0: 0a 00 02 03 42 00 00 00 00 00 00 00 0f 00 20 00 f0: 00 00 00 00 00 00 00 00 10 00 0c 00 00 00 00 00 00:05.2 IDE interface [0101]: nVidia Corporation MCP55 SATA Controller [10de:037f] (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin C routed to IRQ 17 Region 0: I/O ports at 2800 [size=8] Region 1: I/O ports at 24f4 [size=4] Region 2: I/O ports at 24f8 [size=8] Region 3: I/O ports at 24f0 [size=4] Region 4: I/O ports at 24b0 [size=16] Region 5: Memory at a0008000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/2 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: sata_nv 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 01 28 00 00 f5 24 00 00 f9 24 00 00 f1 24 00 00 20: b1 24 00 00 00 80 00 a0 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 03 03 01 40: f1 10 15 29 01 b0 02 00 00 00 00 00 00 00 00 00 50: 0b 68 08 80 00 00 00 00 00 1d 00 00 00 60 09 00 60: 00 00 00 00 41 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 80 80: 00 00 00 00 ed fe eb ff 00 00 9f 1a 6e ff 9f ff 90: 00 00 c6 2f 00 00 00 00 06 00 06 10 7f 03 01 01 a0: 12 0a 00 00 40 00 00 00 00 00 00 00 33 31 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8 d0: 0a 00 02 03 42 00 00 00 00 00 00 00 00 00 00 00 e0: 0a 00 02 03 42 00 00 00 00 00 00 00 00 00 a0 00 f0: 00 00 00 00 00 00 00 00 10 00 0c 00 00 00 00 00 00:06.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI bridge [10de:0370] (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 Memory behind bridge: a0100000-a01fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn+ Capabilities: [b8] Subsystem: nVidia Corporation Unknown device [10de:cb84] Capabilities: [8c] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 00: de 10 70 03 07 01 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 f0 00 80 02 20: 10 a0 10 a0 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 ff 00 04 0a 40: 00 00 33 07 01 00 02 00 05 00 00 00 00 00 48 00 50: 00 00 fe 9b 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 fe 63 02 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 de 10 84 cb c0: de 10 84 cb 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.1 Audio device [0403]: nVidia Corporation MCP55 High Definition Audio [10de:0371] (rev a2) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin B routed to IRQ 23 Region 0: Memory at a0000000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: de 10 71 03 06 00 b0 00 a2 00 03 04 00 00 80 00 10: 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 02 05 40: f1 10 15 29 01 50 02 c0 00 00 00 00 01 01 0f 00 50: 05 6c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 47 10 29 00 00 00 00 00 00 00:08.0 Bridge [0680]: nVidia Corporation MCP55 Ethernet [10de:0373] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 1273 Region 0: Memory at a0009000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 2808 [size=8] Region 2: Memory at a0005800 (32-bit, non-prefetchable) [size=256] Region 3: Memory at a0005400 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/3 Enable+ Address: 00000000fee0f00c Data: 41b9 Masking: 000000fe Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: forcedeth 00: de 10 73 03 07 04 b0 00 a3 00 80 06 00 00 00 00 10: 00 90 00 a0 09 28 00 00 00 58 00 a0 00 54 00 a0 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14 40: f1 10 15 29 01 70 02 fe 00 01 00 00 0c 00 00 00 50: 05 6c 87 01 0c f0 e0 fe 00 00 00 00 b9 41 00 00 60: fe 00 00 00 00 00 00 00 ff 00 00 00 08 00 03 a8 70: 11 50 07 00 02 00 00 00 03 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 11 00 00 00 52 01 00 00 00 00 00 00 00:09.0 Bridge [0680]: nVidia Corporation MCP55 Ethernet [10de:0373] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 21 Region 0: Memory at a000b000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 2810 [size=8] Region 2: Memory at a000a000 (32-bit, non-prefetchable) [size=256] Region 3: Memory at a0005c00 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI-X: Enable- Mask- TabSize=8 Vector table: BAR=2 offset=00000000 PBA: BAR=3 offset=00000000 Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/3 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: forcedeth 00: de 10 73 03 07 00 b0 00 a3 00 80 06 00 00 00 00 10: 00 b0 00 a0 11 28 00 00 00 a0 00 a0 00 5c 00 a0 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 01 14 40: f1 10 15 29 01 70 02 fe 00 00 00 00 0c 00 00 00 50: 05 6c 86 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 ff 00 00 00 08 00 03 a8 70: 11 50 07 00 02 00 00 00 03 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 11 00 00 00 52 01 00 00 00 00 00 00 00:0a.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0376] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4151 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 76 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 51 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 81 3c 11 05 90: 00 00 81 10 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0378] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=05, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: a0200000-a03fffff Prefetchable memory behind bridge: 00000000a4000000-00000000a40fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4159 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 78 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 05 00 31 31 00 00 20: 20 a0 30 a0 01 a4 01 a4 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 59 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 41 3c 11 02 90: 00 00 41 30 00 00 00 00 c0 01 48 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0377] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: a1000000-a2ffffff Prefetchable memory behind bridge: 00000000b0000000-00000000bfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4161 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 77 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 41 41 00 00 20: 00 a1 f0 a2 01 b0 f1 bf 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 0c 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 61 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 01 3d 11 00 90: 00 00 01 31 00 00 00 00 c0 01 48 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 03 00 02 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 03 00 e4 02 00 00 20 c8 2e 0f 30 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 36 61 34 01 00 00 00 00 03 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 b0: 01 0f 11 06 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00 d0: 69 01 61 01 00 00 7f 00 07 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 63 01 03 00 64 01 01 00 63 02 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 a0 00 20 ff bf 00 00 00 00 00 00 00 00 00 90: 03 00 c0 00 01 ff cf 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 03 0a 00 00 20 0b 00 00 b0: 03 00 e0 00 a0 ff e7 00 03 00 e8 00 81 ff ef 00 c0: 33 10 00 00 20 40 00 00 03 50 00 00 01 50 00 00 d0: 00 00 00 00 00 00 00 00 03 f0 00 00 01 f0 00 00 e0: 03 02 00 7f 13 00 80 ff 44 00 ff e3 74 03 8f e0 f0: 01 64 00 9c 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 01 00 00 00 01 02 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 e0 3d f8 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 80: 60 00 00 00 00 00 00 00 24 aa 67 ef 20 13 82 00 90: 10 28 00 00 6a 80 00 64 39 00 00 80 00 00 00 00 a0: eb 02 00 ef 00 00 00 00 00 00 00 00 00 00 00 00 b0: 27 6e 06 d6 a3 00 00 00 13 31 0e 3f e8 04 e0 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: f2 60 79 bf 32 b5 7f 1b 25 20 63 73 fa 26 6c d4 e0: fb 60 39 df 12 b9 fb 19 33 11 73 5b 7e 36 6c d4 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k8temp 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 04 00 40 00 10 0a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 f3 20 fe 60: 63 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1a 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 4e 00 00 00 00 02 60 02 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 70 6c 1e c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 06 a7 e2 04 10 27 60 20 26 26 25 00 e0: 00 00 00 00 24 1b 66 00 1b 17 00 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 13 0f 04 00 00:19.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 08 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 03 00 e4 00 00 00 20 c8 2e 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 6a 01 61 01 00 80 ff 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 b0: 36 61 34 01 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00 d0: 01 0f 11 06 00 00 00 00 03 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 63 01 03 00 64 01 01 00 63 02 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 a0 00 20 ff bf 00 00 00 00 00 00 00 00 00 90: 03 00 c0 00 01 ff cf 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 03 0a 00 00 20 0b 00 00 b0: 03 00 e0 00 a0 ff e7 00 03 00 e8 00 81 ff ef 00 c0: 33 10 00 00 20 40 00 00 03 50 00 00 01 50 00 00 d0: 00 00 00 00 00 00 00 00 03 f0 00 00 01 f0 00 00 e0: 03 02 00 7f 13 00 80 ff 44 00 ff e3 74 03 8f e0 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 01 00 00 00 01 02 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 e0 3d f8 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 80: 60 00 00 00 00 00 00 00 24 aa 67 ef 20 13 82 00 90: 10 28 00 00 6a 80 00 64 39 00 00 80 00 00 00 00 a0: eb 02 00 ef 00 00 00 00 00 00 00 00 00 00 00 00 b0: 98 36 0d d6 a3 00 00 00 18 06 93 a9 ad 4f c0 70 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 8f fe ed 6e 00 99 91 09 a4 a5 87 9b 19 2c 48 11 e0: 56 df 6c e6 00 dd 88 09 b6 a5 c7 cf 15 0d 0c 11 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k8temp 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 04 00 40 00 10 0a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 60: ff 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1a 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 4e 00 00 00 00 02 60 02 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 06 a7 e2 04 10 27 60 20 25 26 26 00 e0: 00 00 00 00 24 1b 66 00 1b 17 00 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 13 0f 04 00 01:05.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) [104c:8023] (prog-if 10 [OHCI]) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (500ns min, 1000ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at a0104000 (32-bit, non-prefetchable) [size=2K] Region 1: Memory at a0100000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ohci1394 00: 4c 10 23 80 56 01 10 02 00 10 00 0c 10 40 00 00 10: 00 40 10 a0 00 00 10 a0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 04 40: 00 00 00 00 01 00 02 7e 00 80 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 88 00 00 00 f0: 10 00 00 00 82 10 00 00 f1 10 15 29 00 00 00 00 03:00.0 PCI bridge [0604]: NEC Corporation uPD720400 PCI Express - PCI/PCI-X Bridge [1033:0125] (rev 06) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=03, secondary=04, subordinate=04, sec-latency=68 I/O behind bridge: 00003000-00003fff Memory behind bridge: a0300000-a03fffff Prefetchable memory behind bridge: 00000000a4000000-00000000a40fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <4us, L1 <16us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [54] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=03:00.0 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=32 CommitmentLimit=32 Downstream: Capacity=16 CommitmentLimit=16 Capabilities: [64] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=55mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [100] Advanced Error Reporting <?> 00: 33 10 25 01 47 01 10 00 06 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 03 04 04 44 31 31 20 04 20: 30 a0 30 a0 01 a4 01 a4 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 10 54 71 00 01 00 00 00 00 20 0a 00 81 6c 02 00 50: 00 00 41 00 07 64 c3 00 00 03 00 00 20 00 20 00 60: 10 00 10 00 01 00 42 da 00 00 c0 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 1f 3f 00 00 00 00 90: 13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.1 PCI bridge [0604]: NEC Corporation uPD720400 PCI Express - PCI/PCI-X Bridge [1033:0125] (rev 06) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Region 0: Memory at a0200000 (64-bit, non-prefetchable) [size=128] Bus: primary=03, secondary=05, subordinate=05, sec-latency=4 Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <4us, L1 <16us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [54] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=conv Status: Dev=03:00.1 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=32 CommitmentLimit=32 Downstream: Capacity=16 CommitmentLimit=16 Capabilities: [64] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=55mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [6c] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [7c] Hot-plug capable Capabilities: [100] Advanced Error Reporting <?> 00: 33 10 25 01 47 01 10 00 06 00 04 06 10 00 81 00 10: 04 00 20 a0 00 00 00 00 03 05 05 04 f1 01 20 24 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 40: 10 54 71 00 01 00 00 00 00 20 00 00 81 6c 02 00 50: 00 00 41 00 07 64 03 00 01 03 00 00 20 00 20 00 60: 10 00 10 00 01 6c 42 da 00 00 c0 00 05 7c 80 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:09.0 SCSI storage controller [0100]: Adaptec ASC-29320A U320 [9005:8000] (rev 10) Subsystem: Adaptec Unknown device [9005:0060] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (10000ns min, 6250ns max), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 20 Region 0: I/O ports at 3400 [disabled] [size=256] Region 1: Memory at a0300000 (64-bit, non-prefetchable) [size=8K] Region 3: I/O ports at 3000 [disabled] [size=256] [virtual] Expansion ROM at a4000000 [disabled] [size=512K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [94] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=8 Status: Dev=04:09.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=512 DMOST=8 DMCRS=16 RSCEM- 266MHz- 533MHz- Kernel driver in use: aic79xx 00: 05 90 00 80 56 01 30 04 10 00 00 01 10 40 00 00 10: 01 34 00 00 04 00 30 a0 00 00 00 00 01 30 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 05 90 60 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 28 19 40: c6 83 00 80 01 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 07 00 42 00 48 04 03 06 00 00 00 00 a0: 05 94 82 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 a0 02 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 06:00.0 VGA compatible controller [0300]: nVidia Corporation G71 [Quadro FX 1500] [10de:029e] (rev a1) (prog-if 00 [VGA controller]) Subsystem: nVidia Corporation Unknown device [10de:032c] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 22 Region 0: Memory at a2000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at b0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at a1000000 (64-bit, non-prefetchable) [size=16M] Region 5: I/O ports at 4000 [size=128] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <1us, L1 <4us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Virtual Channel <?> Capabilities: [128] Power Budgeting <?> Kernel driver in use: nvidia Kernel modules: nvidia 00: de 10 9e 02 47 00 10 00 a1 00 00 03 00 00 00 00 10: 00 00 00 a2 0c 00 00 b0 00 00 00 00 04 00 00 a1 20: 00 00 00 00 01 40 00 00 00 00 00 00 de 10 2c 03 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 02 00 00 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 00 01 00 00 05 00 00 80: 10 28 00 00 01 4d 01 00 08 00 01 11 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80:00.0 RAM memory [0500]: nVidia Corporation MCP55 Memory Controller [10de:0369] (rev a2) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [dc] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 69 03 06 00 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00 40: f1 10 15 29 08 dc e0 01 22 00 11 11 d0 00 00 00 50: 23 06 7f 00 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 0a 00 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 fa 00 64 0e 02 00 00 00 7f 00 00 00 90: 70 00 80 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 0f 0f d0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8 e0: 00 00 e0 fe 00 00 00 00 00 00 80 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80:01.0 RAM memory [0500]: nVidia Corporation MCP55 LPC Bridge [10de:0361] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: I/O ports at fc00 [size=128] Region 1: Memory at c0000000 (32-bit, non-prefetchable) [size=4K] 00: de 10 61 03 0f 00 a0 00 a3 00 00 05 00 00 80 00 10: 01 fc 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: f1 10 15 29 00 00 00 00 fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f9 ff 70: 10 00 ff ff 43 00 00 00 00 00 42 20 00 00 00 00 80: 00 00 00 00 00 00 00 00 f0 00 00 01 80 00 00 00 90: 00 00 00 00 00 00 00 00 21 47 95 86 ef cd ab 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 44 00 00 fe fd 73 00 a0 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 80:01.1 SMBus [0c05]: nVidia Corporation MCP55 SMBus [10de:0368] (rev a3) Subsystem: Tyan Computer Unknown device [10f1:2915] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 255 Region 0: I/O ports at 5000 [size=64] Region 4: I/O ports at 5440 [size=64] Region 5: I/O ports at 5400 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus 00: de 10 68 03 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 01 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 41 54 00 00 01 54 00 00 00 00 00 00 f1 10 15 29 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 01 00 00 40: f1 10 15 29 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 f0 00 00 01 f4 00 00 01 f8 00 00 00 00 00 00 70: 01 00 00 00 00 00 04 c0 00 00 00 00 01 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 00 01 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: e6 16 05 00 a5 21 50 03 80 ff f7 00 61 44 44 11 f0: 5a ff 5f 3f 00 00 00 c0 10 00 00 00 00 00 00 00 80:0a.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0376] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=80, secondary=81, subordinate=81, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4169 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x8, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 76 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 80 81 81 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 69 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 81 3c 11 05 90: 00 00 81 10 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80:0d.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0378] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=80, secondary=82, subordinate=82, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4171 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 78 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 80 82 82 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 71 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 41 3c 11 02 90: 00 00 41 10 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80:0f.0 PCI bridge [0604]: nVidia Corporation MCP55 PCI Express bridge [10de:0377] (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=80, secondary=83, subordinate=83, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Unknown device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4179 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 0, PowerLimit 0.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Capabilities: [160] Advanced Error Reporting <?> Kernel driver in use: pcieport-driver 00: de 10 77 03 47 05 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 80 83 83 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 79 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 1f 28 00 00 01 3d 11 00 90: 00 00 01 11 00 00 00 00 c0 01 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 * superiotool -deV superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x0000, rev=0x00 Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0400, id=0x0081 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8100, rev=0x1 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x8100, rev=0x1 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x8100, rev=0x1 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x8100, rev=0x1 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x8100, rev=0x1 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC SCH5307 (id=0x81, rev=0x00) at 0x2e No dump available for this Super I/O No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0x00/0x00, rev=0x00 Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found.

4 7

Abit VA6 / Atmel AT49F002NT
by Mattias Mattsson 14 Sep '10

14 Sep '10

Hi, I have tested flashrom r1138 on an Abit VA6 with Atmel AT49F002NT flash. Probe, read, erase, write all work together with this patch: http://www.coreboot.org/pipermail/flashrom/2010-August/004439.html lspci crashes with the -xxx option on this board (the lspci manpage mentions this could happen) so output is with -x only. Logs attached. Thanks -mattias

4 4

[PATCH] Nvidia MCP SPI speedup
by Carl-Daniel Hailfinger 14 Sep '10

14 Sep '10

Use caching for Nvidia MCP SPI GPIO accesses. Reduce clock delay to zero. Should result in a 2x speedup, maybe more. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Revision 1130) +++ flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Arbeitskopie) @@ -42,41 +42,39 @@ void *mcp6x_spibar = NULL; +/* Cached value of last GPIO state. */ +static uint8_t mcp_gpiostate; + static void mcp6x_request_spibus(void) { - uint8_t tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(tmp, mcp6x_spibar + 0x530); - /* Wait until we are allowed to use the SPI bus. */ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val) { - uint8_t tmp; - /* Requesting and releasing the SPI bus is handled in here to allow the * chipset to use its own SPI engine for native reads. */ if (val == 0) mcp6x_request_spibus(); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_CS); - tmp |= (val << MCP6X_SPI_CS); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); if (val == 1) mcp6x_release_spibus(); @@ -84,31 +82,22 @@ static void mcp6x_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_SCK); - tmp |= (val << MCP6X_SPI_SCK); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_MOSI); - tmp |= (val << MCP6X_SPI_MOSI); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp = (tmp >> MCP6X_SPI_MISO) & 0x1; - return tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -176,9 +165,10 @@ msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", status, (status >> MCP6X_SPI_REQUEST) & 0x1, (status >> MCP6X_SPI_GRANT) & 0x1); + mcp_gpiostate = status & 0xff; - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 1)) { + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; -- http://www.hailfinger.org/

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flashrom August 2010