Split AMD CS5536 chipset enable in a processor function (Geode RCONF)
and a southbridge function (CS5536 NOR flash control).
This patch has no functional changes.
Is it possible to combine a Geode LX with a CS5535 or even a CS5530?
Is it possible to combine a Geode GX (or earlier) with a CS5536?
If the answer to any of the questions above is "yes", the split probably
makes sense and we should execute the processor specific enable function
inside the new processor enable routine in flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c
===================================================================
--- flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c (Revision 1035)
+++ flashrom-geodelx_cs5536_chipsetenable_split/chipset_enable.c (Arbeitskopie)
@@ -728,16 +728,12 @@
/**
* Geode systems write protect the BIOS via RCONFs (cache settings similar
- * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
- *
- * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
- * To enable write to NOR Boot flash for the benefit of systems that have such
- * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
+ * FIXME: Is this only for Geode LX or also for other Geode models?
*/
-static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+static int enable_flash_geode(void)
{
#define MSR_RCONF_DEFAULT 0x1808
-#define MSR_NORF_CTL 0x51400018
msr_t msr;
@@ -751,6 +747,30 @@
wrmsr(MSR_RCONF_DEFAULT, msr);
}
+ cleanup_cpu_msr();
+
+#undef MSR_RCONF_DEFAULT
+ return 0;
+}
+
+/**
+ * CS5536 systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
+ * To enable write to NOR Boot flash for the benefit of systems that have such
+ * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
+ */
+static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
+{
+#define MSR_NORF_CTL 0x51400018
+
+ msr_t msr;
+
+ if (enable_flash_geode())
+ return -1;
+
+ /* Geode only has a single core */
+ if (setup_cpu_msr(0))
+ return -1;
+
msr = rdmsr(MSR_NORF_CTL);
/* Raise WE_CS3 bit. */
msr.lo |= 0x08;
@@ -758,7 +778,6 @@
cleanup_cpu_msr();
-#undef MSR_RCONF_DEFAULT
#undef MSR_NORF_CTL
return 0;
}
--
http://www.hailfinger.org/
With the attached patch it is no longer necessary to have an extra
dependency step.
--
coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 . Fax: +49 761 7664613
Email: info(a)coresystems.de . http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg . HRB 7656
Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866
On 30.05.2010 19:43, Michael Karcher wrote:
> Not ready for commit because of the pending list refactoring.
>
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
>
This was committed with some changes as part of r1025.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
On 30.05.2010 19:42, Michael Karcher wrote:
> Also modifies nvidia_mcp_gpio_set to cope with multiple MCP55 chips on
> the same board, like on the Tyan S2915-E.
>
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
>
This was committed in r1025.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/