February 2010 - flashrom - mail.coreboot.org

[PATCH] Add Abit VT6X4 board enable
by Michael Karcher Feb. 22, 2010

Feb. 22, 2010

This board has *no* usable IDs at all, neither DMI nor PCI subsystem IDs. You have to force it using "-m abit:vt6x4" Try 2: correct polarity of the GPIO Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index ae46fb0..8018c3a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -973,6 +973,15 @@ static int via_apollo_gpo0_lower(const char *name) } /** + * Suited for Abit VT6X5: Pro133x + VT82C686A + */ +static int via_apollo_gpo4_raise(const char *name) +{ + return via_apollo_gpo_set(4, 1); +} + + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1216,6 +1225,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, intel_ich_gpio16_raise}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, via_apollo_gpo4_raise}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, w83627hf_gpio24_raise_2e}, -- 1.6.5

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[PATCH 2/2] Add Abit VT6X4 board enable
by Michael Karcher Feb. 21, 2010

Feb. 21, 2010

This board has *no* usable IDs at all, neither DMI nor PCI subsystem IDs. You have to force it using "-m abit:vt6x4" Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index ae46fb0..8018c3a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -973,6 +973,15 @@ static int via_apollo_gpo0_lower(const char *name) } /** + * Suited for Abit VT6X5: Pro133x + VT82C686A + */ +static int via_apollo_gpo4_raise(const char *name) +{ + return via_apollo_gpo_set(4, 1); +} + + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1216,6 +1225,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, intel_ich_gpio16_raise}, + {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, via_apollo_gpo4_raise}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, w83627hf_gpio24_raise_2e}, -- 1.6.5

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[PATCH 1/2] Factor out Via Apollo GPO setting
by Michael Karcher Feb. 21, 2010

Feb. 21, 2010

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 49 +++++++++++++++++++++++++++++++++++++------------ 1 files changed, 37 insertions(+), 12 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2de5fd7..ae46fb0 100644 --- a/board_enable.c +++ b/board_enable.c @@ -915,14 +915,11 @@ static int board_kontron_986lcd_m(const char *name) return ret; } -/** - * Suited for Soyo SY-7VCA: Pro133A + VT82C686. - */ -static int board_soyo_sy_7vca(const char *name) +static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; + struct pci_dev *dev; uint32_t base; - uint8_t tmp; + uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); @@ -931,23 +928,51 @@ static int board_soyo_sy_7vca(const char *name) return -1; } - /* GPO0 output from PM IO base + 0x4C */ + printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); - tmp &= ~0x03; + switch(gpio) + { + case 0: + tmp &= ~0x03; + break; + case 1: + tmp |= 0x04; + break; + case 2: + tmp |= 0x08; + break; + case 3: + tmp |= 0x10; + break; + } pci_write_byte(dev, 0x54, tmp); /* PM IO base */ base = pci_read_long(dev, 0x48) & 0x0000FF00; /* Drop GPO0 */ - tmp = INB(base + 0x4C); - tmp &= ~0x01; - OUTB(tmp, base + 0x4C); + tmp = INL(base + 0x4C); + if (raise) + tmp |= 1U << gpio; + else + tmp &= ~(1U << gpio); + OUTL(tmp, base + 0x4C); return 0; } /** + * Suited for Soyo SY-7VCA: Pro133A + VT82C686. + */ +static int via_apollo_gpo0_lower(const char *name) +{ + return via_apollo_gpo_set(0, 0); +} + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1239,7 +1264,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, board_soyo_sy_7vca}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, via_apollo_gpo0_lower}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, via_vt823x_gpio15_raise}, -- 1.6.5

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HPT360/HPT370 ATA controller flash interface
by Michael Karcher Feb. 21, 2010

Feb. 21, 2010

Hello flashrom developers, (obtained from reversing the vendor update tool) Supported IDs (names stolen from pci.ids, the double 372N is not my fault): 1103:0004 HPT366/368/370/370A/372/372N 1103:0005 HPT372A/372N 1103:0006 HPT302/302N Flash enable at 58L.24 (setpci syntax), set to enable flash writing Flash interface select at 70B, 1 = mmapped in ROM addr space, 0 = io mapped IO-mapped access: (BAR4)+0x90 -> DWORD Address (BAR4)+0x94 -> BYTE/WORD/DWORD data access. memmapped chip access was not shown in the tool, but the flash disable code disables the extension ROM BAR. So probably its just mmapped read/write in that area. Maximum Chip size supported by the vendor tool: 128K Regards, Michael Karcher

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[commit] r908 - trunk
by repository service Feb. 21, 2010

Feb. 21, 2010

Author: uwe Date: Sun Feb 21 22:17:00 2010 New Revision: 908 URL: http://flashrom.org/trac/coreboot/changeset/908 Log: Add initial (non-working) code for Highpoint ATA/RAID controllers. It's disabled by default. The current status is detailed at: http://www.flashrom.org/pipermail/flashrom/2010-January/001828.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/atahpt.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/print_wiki.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Feb 19 01:52:10 2010 (r907) +++ trunk/Makefile Sun Feb 21 22:17:00 2010 (r908) @@ -83,6 +83,10 @@ # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes +# Highpoint (HPT) ATA/RAID controller support. +# IMPORTANT: This code is not yet working! +CONFIG_ATAHPT ?= no + # Always enable FT2232 SPI dongles for now. CONFIG_FT2232SPI ?= yes @@ -138,6 +142,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_ATAHPT), yes) +FEATURE_CFLAGS += -D'ATAHPT_SUPPORT=1' +PROGRAMMER_OBJS += atahpt.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_FT2232SPI), yes) FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") # This is a totally ugly hack. Added: trunk/atahpt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/atahpt.c Sun Feb 21 22:17:00 2010 (r908) @@ -0,0 +1,85 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define BIOS_ROM_ADDR 0x90 +#define BIOS_ROM_DATA 0x94 + +#define REG_FLASH_ACCESS 0x58 + +#define PCI_VENDOR_ID_HPT 0x1103 + +struct pcidev_status ata_hpt[] = { + {0x1103, 0x0004, PCI_NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, + {0x1103, 0x0005, PCI_NT, "Highpoint", "HPT372A/372N"}, + {0x1103, 0x0006, PCI_NT, "Highpoint", "HPT302/302N"}, + + {}, +}; + +int atahpt_init(void) +{ + uint32_t reg32; + + get_io_perms(); + + io_base_addr = pcidev_init(PCI_VENDOR_ID_HPT, PCI_BASE_ADDRESS_4, + ata_hpt, programmer_param); + + /* Enable flash access. */ + reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); + reg32 |= (1 << 24); + pci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int atahpt_shutdown(void) +{ + uint32_t reg32; + + /* Disable flash access again. */ + reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); + reg32 &= ~(1 << 24); + pci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); + + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void atahpt_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + +uint8_t atahpt_chip_readb(const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flash.h Sun Feb 21 22:17:00 2010 (r908) @@ -55,6 +55,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, #endif +#if ATAHPT_SUPPORT == 1 + PROGRAMMER_ATAHPT, +#endif #if INTERNAL_SUPPORT == 1 PROGRAMMER_IT87SPI, #endif @@ -328,7 +331,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -466,6 +469,15 @@ extern struct pcidev_status satas_sii[]; #endif +/* atahpt.c */ +#if ATAHPT_SUPPORT == 1 +int atahpt_init(void); +int atahpt_shutdown(void); +void atahpt_chip_writeb(uint8_t val, chipaddr addr); +uint8_t atahpt_chip_readb(const chipaddr addr); +extern struct pcidev_status ata_hpt[]; +#endif + /* ft2232_spi.c */ #define FTDI_FT2232H 0x6010 #define FTDI_FT4232H 0x6011 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flashrom.8 Sun Feb 21 22:17:00 2010 (r908) @@ -146,6 +146,8 @@ .sp .BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controllers)" .sp +.BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" +.sp .BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI translation unit)" .sp .BR "* ft2232spi" " (for flash ROMs attached to a FT2232H/FT4232H based USB SPI programmer)" @@ -185,7 +187,8 @@ Currently the following programmers support this mechanism: .BR nic3com , .BR gfxnvidia , -.BR satasii . +.BR satasii , +.BR atahpt . .sp The it87spi programmer has an optional parameter which will set the I/O base port of the IT87* SPI controller interface to the port specified in the Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Feb 19 01:52:10 2010 (r907) +++ trunk/flashrom.c Sun Feb 21 22:17:00 2010 (r908) @@ -44,7 +44,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 +#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all external programmers except one. #endif enum programmer programmer = @@ -60,6 +60,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII #endif +#if ATAHPT_SUPPORT == 1 + PROGRAMMER_ATAHPT +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI #endif @@ -206,6 +209,25 @@ .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + +#if ATAHPT_SUPPORT == 1 + { + .name = "atahpt", + .init = atahpt_init, + .shutdown = atahpt_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Feb 19 01:52:10 2010 (r907) +++ trunk/print_wiki.c Sun Feb 21 22:17:00 2010 (r908) @@ -566,6 +566,9 @@ #if SATASII_SUPPORT == 1 print_supported_pcidevs_wiki(satas_sii); #endif +#if ATAHPT_SUPPORT == 1 + print_supported_pcidevs_wiki(ata_hpt); +#endif printf("\n|}\n"); }

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Recommendation for board to be used only with flashrom?
by Daniel Clark Feb. 20, 2010

Feb. 20, 2010

I'm looking for a well-supported by flashrom, preferably very inexpensive board to use only as a PLCC programmer for other devices [1]. Anyone have a specific recommendation? [1] Talk:Openbiosprog - Currently Available Alternatives? http://www.randomprojects.org/wiki/Talk:Openbiosprog Thanks, -- Daniel JB Clark | Free Software Activist | http://pobox.com/~dclark

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Re: [flashrom] [PATCH] Probe/Read tested for SST29EE020A
by Peter Lemenkov Feb. 19, 2010

Feb. 19, 2010

Hello All! 2010/2/19 Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>: > http://www.flashrom.org/pipermail/flashrom/2010-February/002318.html > > Should we commit single patches for each positive test report we get, > or collect them? I believe, that committing each (un)successful report in a separated patch is a better idea, than combining them into one or more larger patches (that means some unavoidable delay). -- With best regards, Peter Lemenkov. Sent from Moscow, Mow, Russia

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[PATCH] Probe/Read tested for SST29EE020A
by Michael Karcher Feb. 19, 2010

Feb. 19, 2010

http://www.flashrom.org/pipermail/flashrom/2010-February/002318.html Should we commit single patches for each positive test report we get, or collect them? --- flashchips.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/flashchips.c b/flashchips.c index cfe9dba..6b29f5b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3763,7 +3763,7 @@ struct flashchip flashchips[] = { .total_size = 256, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10, .block_erasers = -- 1.6.5

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[PATCH] fix kontron 986lcd-m and winbond w39v080fa
by Stefan Reinauer Feb. 19, 2010

Feb. 19, 2010

See patch. This is what I had to do to get the combo working again.

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Successful BIOS read on eMachines 333cs
by Andre Robatino Feb. 19, 2010

Feb. 19, 2010

The following command ran successfully on an eMachines 333cs. (I checked that my.rom was the same as the original ROM file flashed to the BIOS.) flashrom -rV my.rom > flashrom.txt The smolt URL for this machine is http://www.smolts.org/client/show/pub_7982b3d7-a650-4770-8128-d385918bf9bd The file flashrom.txt is attached.

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