flashrom November 2010

flashrom@flashrom.org

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146 discussions

[PATCH] Convert WPCE775X interface to flashrom style
by Carl-Daniel Hailfinger 22 Nov '10

22 Nov '10

This patch applies against the top of the flashrom-chromium tree. Compile tested only, I'd be surprised if stuff like write works. Probe and read may work, though. Convert WPCE775X interface to flashrom style. The current code had a fake flashchips.c entry for all chips behind a WPCE775X which is changed on the fly to the real chip data. This means that all relevant logic was duplicated, and the interface was not portable to the current upstream partial write infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> diff --git a/flashchips.c b/flashchips.c index 8e95dd1..f7930a9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7745,22 +7745,5 @@ struct flashchip flashchips[] = { .write = NULL, }, - { - .vendor = "Nuvoton", - .name = "WPCE775x", - .bustype = CHIP_BUSTYPE_FWH, - .manufacture_id = GENERIC_MANUF_ID, - .model_id = GENERIC_DEVICE_ID, - .total_size = 2048, - .page_size = 256, - .tested = TEST_OK_PREW, - .probe = probe_wpce775x, - .probe_timing = TIMING_ZERO, - /* .block_erasers is generated according to detected flashchip. */ - .write = write_wpce775x, - .read = read_memmapped, - .wp = &wp_wpce775x, - }, - { NULL } }; diff --git a/programmer.h b/programmer.h index bbe24f9..40fe656 100644 --- a/programmer.h +++ b/programmer.h @@ -478,6 +478,7 @@ enum spi_controller { SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, SPI_CONTROLLER_MCP6X_BITBANG, + SPI_CONTROLLER_WPCE775XX, #endif #endif #if CONFIG_FT2232_SPI == 1 @@ -563,6 +564,14 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif +/* wpce775x.c */ +#if CONFIG_INTERNAL == 1 +int wpce775x_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int wpce775x_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +int wpce775x_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +#endif + /* serprog.c */ int serprog_init(void); int serprog_shutdown(void); diff --git a/spi.c b/spi.c index 9768bce..91cf615 100644 --- a/spi.c +++ b/spi.c @@ -95,6 +95,13 @@ const struct spi_programmer spi_programmer[] = { .read = bitbang_spi_read, .write_256 = bitbang_spi_write_256, }, + + { /* SPI_CONTROLLER_WPCE775XX */ + .command = wpce775x_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wpce775x_spi_read, + .write_256 = wpce775x_spi_write_256, + }, #endif #endif diff --git a/wpce775x.c b/wpce775x.c index a659893..fe9c35a 100644 --- a/wpce775x.c +++ b/wpce775x.c @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010 Carl-Daniel Hailfinger * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -164,12 +165,13 @@ static int nuvoton_get_sio_index(uint16_t *port) /** Call superio to get pre-configured WCB address. * Read LDN 0x0f (SHM) idx:f8-fb (little-endian). */ -static int get_shaw2ba(chipaddr *shaw2ba) +static int get_shaw2ba(chipaddr *shaw2ba, uint8_t *comm_fwh) { uint16_t idx; uint8_t org_ldn; uint8_t win_cfg; uint8_t shm_cfg; + int ret = 0; if (nuvoton_get_sio_index(&idx) < 0) return -1; @@ -196,27 +198,40 @@ static int get_shaw2ba(chipaddr *shaw2ba) */ win_cfg = sio_read(idx, WPCE775X_WIN_CFG); if (win_cfg & WPCE775X_WIN_CFG_SHWIN_ACC) { - uint8_t idsel; - /* Make sure shared BIOS memory is enabled */ shm_cfg = sio_read(idx, WPCE775X_SHM_CFG); - if ((shm_cfg & WPCE775X_SHM_CFG_BIOS_FWH_EN)) - idsel = 0xf; - else { + if (!(shm_cfg & WPCE775X_SHM_CFG_BIOS_FWH_EN)) { msg_cdbg("Shared BIOS memory is diabled.\n"); msg_cdbg("Please check SHM_CFG:BIOS_FWH_EN.\n"); - goto error; + ret = -1; + goto out; } - - *shaw2ba &= 0x0fffffff; - *shaw2ba |= idsel << 28; + /* FIXME: Check that this is a FWH capable chipset. */ + *comm_fwh = 1; + /* Check if bit 24-27 are set. Intel ICH will never issue any + * LPC firmware memory (FWH) cycles with them cleared. + * FWH cycles only have 28 address bits. + */ + if ((*shaw2ba & (0xf << 24)) != 0xf << 24) { + msg_cerr("WPCE775X shadow window 2 is outside the " + "region addressable with FWH!\n"); + ret = -1; + goto out; + } + /* FWH cycles are only issued for memory mapped to the top + * 16 MB of the 4 GB address space. We could set only the top + * 4 bits since those are ignored by the WPCE775X and we checked + * bits 24-27 to be 0xf above, but setting the top 8 bits makes + * the 16 MB constraint more clear. + */ + *shaw2ba |= 0xff << 24; + } else { + *comm_fwh = 0; } - - sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); - return 0; -error: + +out: sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); - return -1; + return ret; } /* Call superio to get pre-configured fwh_id. @@ -232,7 +247,8 @@ static int get_fwh_id(uint8_t *fwh_id) org_ldn = sio_read(idx, NUVOTON_SIOCFG_LDN); sio_write(idx, NUVOTON_SIOCFG_LDN, NUVOTON_LDN_SHM); - *fwh_id = sio_read(idx, WPCE775X_SHM_CFG); + /* Upper 4 bits of WPCE775X_SHM_CFG store the FWH ID. */ + *fwh_id = sio_read(idx, WPCE775X_SHM_CFG) >> 4; sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); return 0; @@ -322,8 +338,8 @@ static int InitFlash(unsigned char srp) /* Byte 5: opcode for Write Status Enable JEDEC_EWSR defines 0x50, but W25Q16 - accepts 0x06 to enable write status */ - wcb->field[1] = 0x06; + accepts JEDEC_WREN to enable write status */ + wcb->field[1] = JEDEC_WREN; /* Byte 6: opcode for Write Enable */ wcb->field[2] = JEDEC_WREN; @@ -362,11 +378,10 @@ static int InitFlash(unsigned char srp) } /** Read flash vendor/device IDs through EC. - * @param id0, id1, id2, id3 Pointers to store detected IDs. NULL will be ignored. + * @param readarr 4-byte buffer for JEDEC_RDID response. * @return 1 for error; 0 for success. */ -static int ReadId(unsigned char* id0, unsigned char* id1, - unsigned char* id2, unsigned char* id3) +static int ReadId(unsigned char *readarr) { assert_ec_is_free(); @@ -374,42 +389,28 @@ static int ReadId(unsigned char* id0, unsigned char* id1, if (blocked_exec()) return 1; - msg_cdbg("id0: 0x%2x, id1: 0x%2x, id2: 0x%2x, id3: 0x%2x\n", - wcb->field[0], wcb->field[1], wcb->field[2], wcb->field[3]); - if (id0) { - *id0 = wcb->field[0]; - } - if (id1) { - *id1 = wcb->field[1]; - } - if (id2) { - *id2 = wcb->field[2]; - } - if (id3) { - *id3 = wcb->field[3]; - } + readarr[0] = wcb->field[0]; + readarr[1] = wcb->field[1]; + readarr[2] = wcb->field[2]; + readarr[3] = wcb->field[3]; return 0; } /** probe if WPCE775x is present. - * @return 0 for error; 1 for success + * @return 1 for error; 0 for success */ -int probe_wpce775x(struct flashchip *flash) +int wpce775x_init(void) { - unsigned char ids[4]; - unsigned long base; uint16_t sio_port; uint8_t srid; uint8_t fwh_id; - uint32_t size; - chipaddr original_memory; - uint32_t original_size; - int i; + uint8_t comm_fwh = 0; /* detect if wpce775x exists */ if (nuvoton_get_sio_index(&sio_port) < 0) { msg_cdbg("No Nuvoton chip is found.\n"); + /* No chip found is not an error. */ return 0; } srid = sio_read(sio_port, NUVOTON_SIOCFG_SRID); @@ -425,101 +426,51 @@ int probe_wpce775x(struct flashchip *flash) } /* get the address of Shadow Window 2. */ - if (get_shaw2ba(&wcb_physical_address) < 0) { + if (get_shaw2ba(&wcb_physical_address, &comm_fwh) < 0) { msg_cdbg("Cannot get the address of Shadow Window 2"); - return 0; + return 1; } msg_cdbg("Get the address of WCB(SHA WIN2) at 0x%08x\n", (uint32_t)wcb_physical_address); - wcb = (struct wpce775x_wcb *) - programmer_map_flash_region("WPCE775X WCB", + + /* If we use FWH for Shadow Window 2, we have to set FWH IDSEL in the + * chipset before we try to access Shadow Window 2. + */ + if (comm_fwh) { + if (get_fwh_id(&fwh_id) < 0) { + msg_cdbg("Cannot get fwh_id value.\n"); + return 1; + } + msg_cdbg("get fwh_id: 0x%02x\n", fwh_id); + + /* TODO: set fwh_idsel of chipset. + * Currently, we employ "-p internal:fwh_idsel=0x0000223e". + */ + } + + wcb = (struct wpce775x_wcb *)physmap("WPCE775X WCB", wcb_physical_address, getpagesize() /* min page size */); msg_cdbg("mapped wcb address: %p for physical addr: 0x%08lx\n", wcb, wcb_physical_address); if (!wcb) { msg_perr("FATAL! Cannot map memory area for wcb physical address.\n"); - return 0; + return 1; } memset((void*)wcb, 0, sizeof(*wcb)); - if (get_fwh_id(&fwh_id) < 0) { - msg_cdbg("Cannot get fwh_id value.\n"); - return 0; - } - msg_cdbg("get fwh_id: 0x%02x\n", fwh_id); - - /* TODO: set fwh_idsel of chipset. - Currently, we employ "-p internal:fwh_idsel=0x0000223e". */ - /* Initialize the parameters of EC SHM component */ if (InitFlash(0x00)) - return 0; - - /* Query the flash vendor/device ID */ - if (ReadId(&ids[0], &ids[1], &ids[2], &ids[3])) - return 0; - - /* In current design, flash->virtual_memory is mapped before calling flash->probe(). - * So that we have to update flash->virtual_memory after we know real flash size. - * Unmap allocated memory before allocate new memory. */ - original_size = flash->total_size * 1024; /* original flash size */ - original_memory = flash->virtual_memory; - - for (scan = &flashchips[0]; scan && scan->name; scan++) { - if (!(scan->bustype & CHIP_BUSTYPE_SPI)) { - msg_cdbg("WPCE775x: %s bustype supports no SPI: %s\n", - scan->name, flashbuses_to_text(scan->bustype)); - continue; - } - if ((scan->manufacture_id != GENERIC_MANUF_ID) && - (scan->manufacture_id != ids[0])) { - msg_cdbg("WPCE775x: %s manufacture_id does not match: 0x%02x\n", - scan->name, scan->manufacture_id); - continue; - } - if ((scan->model_id != GENERIC_DEVICE_ID) && - (scan->model_id != ((ids[1]<<8)|ids[2]))) { - msg_cdbg("WPCE775x: %s model_id does not match: 0x%02x\n", - scan->name, scan->model_id); - continue; - } - - msg_cdbg("WPCE775x: found the flashchip %s.\n", scan->name); - - /* Copy neccesary information */ - flash->total_size = scan->total_size; - flash->page_size = scan->page_size; - memcpy(flash->block_erasers, scan->block_erasers, - sizeof(scan->block_erasers)); - /* .block_erase is pointed to EC-specific way. */ - for (i = 0; i < NUM_ERASEFUNCTIONS; ++i) - flash->block_erasers[i].block_erase = erase_wpce775x; - break; - } - if (!scan || !scan->name) { - msg_cdbg("WPCE775x: cannot recognize the flashchip.\n"); - scan = 0; /* since scan is a global variable, reset pointer - * to indicate nothing was detected */ - return 0; - } - - /* Unmap allocated memory before allocate new memory. */ - programmer_unmap_flash_region((void*)original_memory, original_size); - - /* In current design, flash->virtual_memory is mapped before calling flash->probe(). - * So that we have to update flash->virtual_memory after we know real flash size. - * Map new virtual address here. */ - size = flash->total_size * 1024; /* new flash size */ - base = 0xffffffff - size + 1; - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); - msg_cdbg("Remap memory to 0x%08lx from base: 0x%08lx size=0x%08lx\n", - flash->virtual_memory, base, (long unsigned int)size); + return 1; - return 1; + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with WPCE775x SPI.\n"); + spi_controller = SPI_CONTROLLER_WPCE775XX; + buses_supported |= CHIP_BUSTYPE_SPI; + return 0; } /** Tell EC to "enter flash update" mode. */ -int EnterFlashUpdate(void) +static int EnterFlashUpdate(void) { if (in_flash_update_mode) { /* already in update mode */ @@ -544,7 +495,7 @@ int EnterFlashUpdate(void) * Without calling this function, the EC stays in busy-loop and will not * response further request from host, which means system will halt. */ -int ExitFlashUpdate(unsigned char exit_code) +static int ExitFlashUpdate(unsigned char exit_code) { if (in_flash_update_mode <= 0) { msg_cdbg("Not in flash update mode yet.\n"); @@ -571,62 +522,56 @@ int ExitFlashUpdate(unsigned char exit_code) * 0x20 is used for EC F/W no change, but BIOS changed (in Share mode) * 0x21 is used for EC F/W changed. Goto EC F/W, wait system reboot. * 0x22 is used for EC F/W changed, Goto EC Watchdog reset. */ -int ExitFlashUpdateFirmwareNoChange(void) { +static int ExitFlashUpdateFirmwareNoChange(void) { return ExitFlashUpdate(0x20); } -int ExitFlashUpdateFirmwareChanged(void) { +static int ExitFlashUpdateFirmwareChanged(void) { return ExitFlashUpdate(0x21); } -int erase_wpce775x(struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen) +static int wpce775x_set_write_window(unsigned int base, unsigned int size) { assert_ec_is_free(); /* Set Write Window on flash chip (optional). * You may limit the window to partial flash for experimental. */ wcb->code = 0xC5; /* Set Write Window */ - wcb->field[0] = 0x00; /* window base: little-endian */ - wcb->field[1] = 0x00; - wcb->field[2] = 0x00; - wcb->field[3] = 0x00; - wcb->field[4] = 0x00; /* window length: little-endian */ - wcb->field[5] = 0x00; - wcb->field[6] = 0x20; - wcb->field[7] = 0x00; + wcb->field[0] = base & 0xff; /* window base: little-endian */ + wcb->field[1] = (base >> 8) & 0xff; + wcb->field[2] = (base >> 16) & 0xff; + wcb->field[3] = (base >> 24) & 0xff; + wcb->field[4] = size & 0xff; /* window length: little-endian */ + wcb->field[5] = (size >> 8) & 0xff; + wcb->field[6] = (size >> 16) & 0xff; + wcb->field[7] = (size >> 24) & 0xff; if (blocked_exec()) return 1; + return 0; +} - /* TODO: here assume block sizes are identical. The right way is to traverse - * block_erasers[] and find out the corresponding block size. */ - unsigned int block_size = flash->block_erasers[0].eraseblocks[0].size; - unsigned int current; - - msg_cdbg("Erasing ... 0x%08x 0x%08x\n", blockaddr, blocklen); +static int handle_erase_wpce775x(unsigned int blockaddr) +{ + /* FIXME: A 2 MByte window is too small. */ + if (wpce775x_set_write_window(0x0, 0x200000)) + return 1; - if (EnterFlashUpdate()) return 1; + assert_ec_is_free(); - for (current = 0; - current < blocklen; - current += block_size) { - wcb->code = 0x80; /* Sector/block erase */ - - /* WARNING: assume the block address for EC is lalways little-endian. */ - unsigned int addr = blockaddr + current; - wcb->field[0] = addr & 0xff; - wcb->field[1] = (addr >> 8) & 0xff; - wcb->field[2] = (addr >> 16) & 0xff; - wcb->field[3] = (addr >> 24) & 0xff; - if (blocked_exec()) - goto error_exit; - } + if (EnterFlashUpdate()) + return 1; - if (ExitFlashUpdateFirmwareChanged()) return 1; + wcb->code = 0x80; /* Sector/block erase */ + /* WARNING: assume the block address for EC is always little-endian. */ + wcb->field[0] = blockaddr & 0xff; + wcb->field[1] = (blockaddr >> 8) & 0xff; + wcb->field[2] = (blockaddr >> 16) & 0xff; + wcb->field[3] = (blockaddr >> 24) & 0xff; + if (blocked_exec()) + goto error_exit; - if (check_erased_range(flash, blockaddr, blocklen)) { - msg_perr("ERASE FAILED!\n"); + if (ExitFlashUpdateFirmwareChanged()) return 1; - } return 0; @@ -635,55 +580,37 @@ error_exit: return 1; } -/** Callback function for do_romentries(). - * @flash - point to flash info - * @buf - the address of buffer - * @addr - the start offset in buffer - * @len - length to write (start from @addr) +/** + * Page write helper */ -int write_wpce775x_entry(struct flashchip *flash, uint8_t *buf, - const chipaddr addr, size_t len) +static int write_wpce775x_entry(unsigned long writeaddr, unsigned long writelen, const unsigned char *buf) { - chipaddr current; - unsigned int block_size = flash->block_erasers[0].eraseblocks[0].size; - unsigned int bytes_until_next_block; - unsigned int written = 0; + if (writelen > 8) { + msg_perr("WTF did you call %s with writelen=%li\n", __func__, writelen); + return 1; + } - msg_cdbg("Writing ... 0x%08lx 0x%08lx\n", (long unsigned int)addr, - (long unsigned int)len); + /* FIXME: assert_ec_is_free() missing? */ + if (EnterFlashUpdate()) + return 1; - if (EnterFlashUpdate()) return 1; - for (current = addr; - current < addr + len; - current += written/* maximum program buffer */) { - /* erase sector before write it. */ - if ((current & (block_size-1))==0) { - if (erase_wpce775x(flash, current, block_size)) - goto error_exit; - } + /* wpce775x provides a 8-byte program buffer. */ + wcb->code = 0xA0; /* Set Address */ + wcb->field[0] = writeaddr & 0xff; + wcb->field[1] = (writeaddr >> 8) & 0xff; + wcb->field[2] = (writeaddr >> 16) & 0xff; + wcb->field[3] = (writeaddr >> 24) & 0xff; + if (blocked_exec()) + goto error_exit; - /* wpce775x provides a 8-byte program buffer. */ - wcb->code = 0xA0; /* Set Address */ - wcb->field[0] = current & 0xff; - wcb->field[1] = (current >> 8) & 0xff; - wcb->field[2] = (current >> 16) & 0xff; - wcb->field[3] = (current >> 24) & 0xff; - if (blocked_exec()) - goto error_exit; - - bytes_until_next_block = block_size - (current % block_size); - if (bytes_until_next_block > 0 && bytes_until_next_block < 8) - written = bytes_until_next_block; - else - written = 8; /* maximum buffer size */ - wcb->code = 0xB0 | written; - int i; - for (i = 0; i < written; i++) { - wcb->field[i] = buf[current + i]; - } - if (blocked_exec()) - goto error_exit; + /* 8 is maximum buffer size */ + wcb->code = 0xB0 | writelen; + int i; + for (i = 0; i < writelen; i++) { + wcb->field[i] = buf[i]; } + if (blocked_exec()) + goto error_exit; if (ExitFlashUpdateFirmwareChanged()) return 1; return 0; @@ -693,40 +620,11 @@ error_exit: return 1; } -/** Write data to flash (layout supported). - * In some cases, EC and BIOS share a physical flash chip. So it is dangerous - * to erase whole flash chip when you only wanna update BIOS image. - * By calling do_romentries(), we won't erase/program those blocks/sectors - * not specified by -i parameter. - */ -int write_wpce775x(struct flashchip *flash, uint8_t * buf) -{ - return do_romentries(buf, flash, write_wpce775x_entry); -} - -int set_range_wpce775x(struct flashchip *flash, unsigned int start, unsigned int len) { - struct w25q_status status; - - if (w25_range_to_status(scan, start, len, &status)) return -1; - - /* Since WPCE775x doesn't support reading status register, we have to - * set SRP0 to 1 when writing status register. */ - status.srp0 = 1; - - msg_cdbg("Going to set: 0x%02x\n", *((unsigned char*)&status)); - msg_cdbg("status.busy: %x\n", status.busy); - msg_cdbg("status.wel: %x\n", status.wel); - msg_cdbg("status.bp0: %x\n", status.bp0); - msg_cdbg("status.bp1: %x\n", status.bp1); - msg_cdbg("status.bp2: %x\n", status.bp2); - msg_cdbg("status.tb: %x\n", status.tb); - msg_cdbg("status.sec: %x\n", status.sec); - msg_cdbg("status.srp0: %x\n", status.srp0); - +static int wpce775x_wrsr(const unsigned char status) { /* InitFlash (with particular status value), and EnterFlashUpdate() then * ExitFlashUpdate() immediately. Thus, the flash status register will * be updated. */ - if (InitFlash(*(unsigned char*)&status)) + if (InitFlash(status)) return -1; if (EnterFlashUpdate()) return 1; ExitFlashUpdateFirmwareNoChange(); @@ -734,14 +632,59 @@ int set_range_wpce775x(struct flashchip *flash, unsigned int start, unsigned int return 0; } -static int enable_wpce775x(struct flashchip *flash) +int wpce775x_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) { - msg_cdbg("WPCE775x always sets SRP0 in set_range_wpce775x()\n"); - return 0; + unsigned char ids[4]; + unsigned int addr = 0; + + /* Ugly hack. Not my fault. -- Carl-Daniel */ + switch(writearr[0]) { + case JEDEC_RDID: + /* We always read 4 ID bytes. Return only the wanted parts. */ + if (ReadId(ids)) + return 1; + memcpy(readarr, ids, min(readcnt, 4)); + break; + case JEDEC_BYTE_PROGRAM: + /* FIXME: Precedence! */ + addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + if (write_wpce775x_entry(addr, writecnt - 4, writearr + 4)) + return 1; + break; + case JEDEC_SE: + /* FIXME: Precedence! */ + addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + if (handle_erase_wpce775x(addr)) + return 1; + break; + case JEDEC_WRSR: + if (wpce775x_wrsr(writearr[1])) + return 1; + break; + case JEDEC_WREN: + case JEDEC_RDSR: + default: + msg_perr("You are truly screwed. This command is not " + "implemented (yet)\n"); + return 1; + } + return 0; } +/* FIXME: This command is not implemented. We have to use read_memmapped, but + * the mapping window is too small for reasonably sized chips. + */ +int wpce775x_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + if (flash->total_size * 1024 > 2 * 1024 * 1024) { + msg_perr("Chip is too big for reading on wpce775x.\n"); + return 1; + } + return read_memmapped(flash, buf, start, len); +} -struct wp wp_wpce775x = { - .set_range = set_range_wpce775x, - .enable = enable_wpce775x, -}; +int wpce775x_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + return spi_write_chunked(flash, buf, start, len, 8); +} -- http://www.hailfinger.org/

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Success report: Tyan S2466 (Tiger MPX)
by Uwe Hermann 22 Nov '10

22 Nov '10

I successfully tested write/erase on Tyan S2466 (Tiger MPX). http://www.tyan.com/archive/products/html/tigermpx.html Logs attached. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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the missing attachment
by Xhuman 21 Nov '10

21 Nov '10

goddamnit- forgot to 'save' the pasted output. *i think* in caso, tenga esta.

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another hot-swapped winbond dip8
by Xhuman 21 Nov '10

21 Nov '10

latest (as of 11.20.10) svn/git checkout of flashrom. success with 3 different dip8 bios(es?) w/ same MoBo (i guess as long as bios dip p/o were the same, it would work??.) here's the terminal output, in case it is of help- side note, i applied the latest(?) nvidia chipset patch to the svn source and got an error during the make/install command- applied patch via quilt gui, and the error was for the module for which the patch was made - ie. it just didn't build the 'nvidiaXXy.o' -just popped the patch (and a glass pirate eye fell out) and did a make distclean (what ever happened to Mr. Proper?) and everything built fine. again, amidst my 'i've been up for two days trying to recover my Fuckdo$e 7 box psychotic ramblings', thanks for your work. if my email seems hard to follow, that's because it is. it must suck to be on the receiving end of my corrospodence (sp) . i read too much burroughs and artaud during my younger days- my writing abilities are pretty much fucked-for-a-while at this point. as far as testing, if you want/need/etc, i will include output from flashrom commands as i try them on other (people's) boards. (i help out the relatives across the street with computer *repair*. many people (unknowingly) have sacrificed $100's worth of machines in the name of my education, and i am a bold, and hell of a curious motherfucker. especially when it comes to flashing chipsets (i have a decent pile of linksys hope!ess!y bricked routers from my jtag study course, and i'm ready to add some motherboards to the trophy pile. i love flashing chips, bios, and children- especially when it's really 'iffy' and the likelyhood is high that i'll have to make up a diagnostic lie as to why customer's comps are now parts and paperweights)

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(yes, it is in all caps) THANK YOU!! (repeat adementia)
by Xhuman 20 Nov '10

20 Nov '10

yes, thank you jesus for you, your whole family, and every seed of your loins! i am writing this before setting my *initial* bios settings because i am sofa king happy that your program worked!! i swear, i'd donate a kidney or two to you about right now!! i actually hot-swapped two AMI bios (8pin dip) and flashed them. my first board i screwed the bios by playing around with a bios edit prog, the second, i bought last week since it had 8pin dip bios, figured i could use it to reflash the bad one, and have an extra board. but, my phenom ii x4 (965 black ed-) runs at 140w, and the new mobo kept shutting down stating (the obvious) that my cpu was running over ~125 watts, so i couldn't use it to flash the old bios, but i hadn't noticed that my linux box had an 8pin dip bios also, until i was playing around with a lpt 25 pin header (for jtag), so i updated the 'you're over 125w' bios as well as flashed the original bios mistake/lesson i had. so all from linux desktop! quite nice! i'll send attachments of my mobo/chipset info for you with this, but i didn't run the commands with -V nor did i save the output. i tend to read the instructions after the fact..(why i ended up with the bios problem in the first place) so again, thanks, and EXCELLENT work!!!!!!!!!!

1 0

Support for Nvidia chips
by Joe Pea 20 Nov '10

20 Nov '10

I tried flashrom and it said there's no support for my chip :( This is the output of flashrom -V: flashrom v0.9.2-r1001 on Linux 2.6.35-ARCH (x86_64), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease) flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "BIOSTAR Group" DMI string system-product-name: "N61PB-M2S" DMI string system-version: " " DMI string baseboard-manufacturer: "BIOSTAR Group" DMI string baseboard-product-name: "N61PB-M2S" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8716 Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:03eb at 00:01:1 SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000 SPI control is 0x000a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. No IT87* serial flash segment enabled. Calibrating delay loop... 1454M loops per second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1010 us, 10000 myus = 10017 us, OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Can we get it working? -= Joe Pea =-

2 1

Breaking the assumption that filesize == romsize
by Richard Smith 18 Nov '10

18 Nov '10

Current flashrom forces that the loaded filesize must equal the romsize. If you are using an external programmer then this may not be true. How deeply wired is this assumption? I'd like to bypass those checks it if the -p option is used. -- Richard A. Smith

4 5

[PATCH 0/5] ft2232_spi: OpenMoko DebugBoard support
by Alex Badea 18 Nov '10

18 Nov '10

Hi, This patch series adds support for the OpenMoko DebugBoard V2+, which is based on the FT2232D. A few fixes were required to make it work. Any feedback is greatly appreciated, this is my first contribution to flashrom. Thanks. Alex Badea (5): ft2232_spi: don't hardcode USB VID ft2232_spi: add support for the OpenMoko DebugBoard V2+ ft2232_spi: allow CLOCK_X5 to be set at runtime ft2232_spi: retry short reads ft2232_spi: flag OpenMoko DebugBoard as tested ft2232_spi.c | 67 ++++++++++++++++++++++++++++++++++++++-------------------- 1 files changed, 44 insertions(+), 23 deletions(-)

3 16

[PATCH] Fix IDSEL handling in WPCE775X
by Carl-Daniel Hailfinger 17 Nov '10

17 Nov '10

Fix IDSEL handling in WPCE775X. - Clean up the code - Check that SHM window 2 is reachable if FWH communication is used - IDSEL is 4 bits, use a mask to extract it correctly - IDSEL setup needs to happen before SHM window 2 is accessed if FWH communication is used Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> diff --git a/wpce775x.c b/wpce775x.c index a659893..1407977 100644 --- a/wpce775x.c +++ b/wpce775x.c @@ -164,12 +164,13 @@ static int nuvoton_get_sio_index(uint16_t *port) /** Call superio to get pre-configured WCB address. * Read LDN 0x0f (SHM) idx:f8-fb (little-endian). */ -static int get_shaw2ba(chipaddr *shaw2ba) +static int get_shaw2ba(chipaddr *shaw2ba, uint8_t *comm_fwh) { uint16_t idx; uint8_t org_ldn; uint8_t win_cfg; uint8_t shm_cfg; + int ret = 0; if (nuvoton_get_sio_index(&idx) < 0) return -1; @@ -196,27 +197,40 @@ static int get_shaw2ba(chipaddr *shaw2ba) */ win_cfg = sio_read(idx, WPCE775X_WIN_CFG); if (win_cfg & WPCE775X_WIN_CFG_SHWIN_ACC) { - uint8_t idsel; - /* Make sure shared BIOS memory is enabled */ shm_cfg = sio_read(idx, WPCE775X_SHM_CFG); - if ((shm_cfg & WPCE775X_SHM_CFG_BIOS_FWH_EN)) - idsel = 0xf; - else { + if (!(shm_cfg & WPCE775X_SHM_CFG_BIOS_FWH_EN)) { msg_cdbg("Shared BIOS memory is diabled.\n"); msg_cdbg("Please check SHM_CFG:BIOS_FWH_EN.\n"); - goto error; + ret = -1; + goto out; } - - *shaw2ba &= 0x0fffffff; - *shaw2ba |= idsel << 28; + /* FIXME: Check that this is a FWH capable chipset. */ + comm_fwh = 1; + /* Check if bit 24-27 are set. Intel ICH will never issue any + * LPC firmware memory (FWH) cycles with them cleared. + * FWH cycles only have 28 address bits. + */ + if (*shaw2ba & (0xf << 24) != 0xf << 24) { + msg_cerr("WPCE775X shadow window 2 is outside the " + "region addressable with FWH!\n"); + ret = -1; + goto out; + } + /* FWH cycles are only issued for memory mapped to the top + * 16 MB of the 4 GB address space. We could set only the top + * 4 bits since those are ignored by the WPCE775X and we checked + * bits 24-27 to be 0xf above, but setting the top 8 bits makes + * the 16 MB constraint more clear. + */ + *shaw2ba |= 0xff << 24; + } else { + *comm_fwh = 0; } - - sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); - return 0; -error: + +out: sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); - return -1; + return ret; } /* Call superio to get pre-configured fwh_id. @@ -232,7 +246,8 @@ static int get_fwh_id(uint8_t *fwh_id) org_ldn = sio_read(idx, NUVOTON_SIOCFG_LDN); sio_write(idx, NUVOTON_SIOCFG_LDN, NUVOTON_LDN_SHM); - *fwh_id = sio_read(idx, WPCE775X_SHM_CFG); + /* Upper 4 bits of WPCE775X_SHM_CFG store the FWH ID. */ + *fwh_id = sio_read(idx, WPCE775X_SHM_CFG) >> 4; sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); return 0; @@ -402,6 +417,7 @@ int probe_wpce775x(struct flashchip *flash) uint16_t sio_port; uint8_t srid; uint8_t fwh_id; + uint8_t comm_fwh = 0; uint32_t size; chipaddr original_memory; uint32_t original_size; @@ -425,14 +441,29 @@ int probe_wpce775x(struct flashchip *flash) } /* get the address of Shadow Window 2. */ - if (get_shaw2ba(&wcb_physical_address) < 0) { + if (get_shaw2ba(&wcb_physical_address, &comm_fwh) < 0) { msg_cdbg("Cannot get the address of Shadow Window 2"); return 0; } msg_cdbg("Get the address of WCB(SHA WIN2) at 0x%08x\n", (uint32_t)wcb_physical_address); - wcb = (struct wpce775x_wcb *) - programmer_map_flash_region("WPCE775X WCB", + + /* If we use FWH for Shadow Window 2, we have to set FWH IDSEL in the + * chipset before we try to access Shadow Window 2. + */ + if (comm_fwh) { + if (get_fwh_id(&fwh_id) < 0) { + msg_cdbg("Cannot get fwh_id value.\n"); + return 0; + } + msg_cdbg("get fwh_id: 0x%02x\n", fwh_id); + + /* TODO: set fwh_idsel of chipset. + * Currently, we employ "-p internal:fwh_idsel=0x0000223e". + */ + } + + wcb = (struct wpce775x_wcb *)physmap("WPCE775X WCB", wcb_physical_address, getpagesize() /* min page size */); msg_cdbg("mapped wcb address: %p for physical addr: 0x%08lx\n", wcb, wcb_physical_address); @@ -442,15 +473,6 @@ int probe_wpce775x(struct flashchip *flash) } memset((void*)wcb, 0, sizeof(*wcb)); - if (get_fwh_id(&fwh_id) < 0) { - msg_cdbg("Cannot get fwh_id value.\n"); - return 0; - } - msg_cdbg("get fwh_id: 0x%02x\n", fwh_id); - - /* TODO: set fwh_idsel of chipset. - Currently, we employ "-p internal:fwh_idsel=0x0000223e". */ - /* Initialize the parameters of EC SHM component */ if (InitFlash(0x00)) return 0; -- http://www.hailfinger.org/

1 2

[commit] r1234 - trunk
by repository service 16 Nov '10

16 Nov '10

Author: hailfinger Date: Tue Nov 16 22:25:29 2010 New Revision: 1234 URL: http://flashrom.org/trac/flashrom/changeset/1234 Log: Support bulk read on Dediprog SF100. Should result in native speed for plain read and erase. Should result in a measurable speedup for writes due to a fast verify. Packet size is 512 bytes. Depending on your USB hardware and the Dediprog firmware version, this may not work at all. That said, it worked on the hardware we tested. Add lots of error checking where it was missing before. Thanks to Richard A. Smith, Mathias Krause and David Hendricks for testing multiple iterations of this patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-By: Richard A. Smith <richard(a)laptop.org> Acked-By: Mathias Krause <mathias.krause(a)secunet.com> Modified: trunk/dediprog.c Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Tue Nov 16 18:21:58 2010 (r1233) +++ trunk/dediprog.c Tue Nov 16 22:25:29 2010 (r1234) @@ -27,6 +27,7 @@ #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; +static int dediprog_endpoint; #if 0 /* Might be useful for other pieces of code as well. */ @@ -148,11 +149,93 @@ } #endif +/* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. + * @start start address + * @len length + * @return 0 on success, 1 on failure + */ +static int dediprog_spi_bulk_read(struct flashchip *flash, uint8_t *buf, + int start, int len) +{ + int ret; + int i; + /* chunksize must be 512, other sizes will NOT work at all. */ + const int chunksize = 0x200; + const int count = len / chunksize; + const char count_and_chunk[] = {count & 0xff, + (count >> 8) & 0xff, + chunksize & 0xff, + (chunksize >> 8) & 0xff}; + + if ((start % chunksize) || (len % chunksize)) { + msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " + "at flashrom(a)flashrom.org\n", __func__, start, len); + return 1; + } + + /* No idea if the hardware can handle empty reads, so chicken out. */ + if (!len) + return 0; + /* Command Read SPI Bulk. No idea which read command is used on the + * SPI side. + */ + ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % 0x10000, + start / 0x10000, (char *)count_and_chunk, + sizeof(count_and_chunk), DEFAULT_TIMEOUT); + if (ret != sizeof(count_and_chunk)) { + msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, + usb_strerror()); + return 1; + } + + for (i = 0; i < count; i++) { + ret = usb_bulk_read(dediprog_handle, 0x80 | dediprog_endpoint, + (char *)buf + i * chunksize, chunksize, + DEFAULT_TIMEOUT); + if (ret != chunksize) { + msg_perr("SPI bulk read %i failed, expected %i, got %i " + "%s!\n", i, chunksize, ret, usb_strerror()); + return 1; + } + } + + return 0; +} + int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); - /* Chosen read length is 16 bytes for now. */ - return spi_read_chunked(flash, buf, start, len, 16); + int ret; + /* chunksize must be 512, other sizes will NOT work at all. */ + const int chunksize = 0x200; + int residue = start % chunksize ? chunksize - start % chunksize : 0; + int bulklen; + + if (residue) { + msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", + start, residue); + ret = spi_read_chunked(flash, buf, start, residue, 16); + if (ret) + return ret; + } + + /* Round down. */ + bulklen = (len - residue) / chunksize * chunksize; + ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, + bulklen); + if (ret) + return ret; + + len -= residue + bulklen; + if (len) { + msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", + start, len); + ret = spi_read_chunked(flash, buf + residue + bulklen, + start + residue + bulklen, len, 16); + if (ret) + return ret; + } + + return 0; } int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -345,6 +428,7 @@ struct usb_device *dev; char *voltage; int millivolt = 3500; + int ret; msg_pspew("%s\n", __func__); @@ -371,8 +455,23 @@ dev->descriptor.idVendor, dev->descriptor.idProduct); dediprog_handle = usb_open(dev); - usb_set_configuration(dediprog_handle, 1); - usb_claim_interface(dediprog_handle, 0); + ret = usb_set_configuration(dediprog_handle, 1); + if (ret < 0) { + msg_perr("Could not set USB device configuration: %i %s\n", + ret, usb_strerror()); + if (usb_close(dediprog_handle)) + msg_perr("Could not close USB device!\n"); + return 1; + } + ret = usb_claim_interface(dediprog_handle, 0); + if (ret < 0) { + msg_perr("Could not claim USB device interface %i: %i %s\n", + 0, ret, usb_strerror()); + if (usb_close(dediprog_handle)) + msg_perr("Could not close USB device!\n"); + return 1; + } + dediprog_endpoint = 2; /* URB 6. Command A. */ if (dediprog_command_a()) return 1; @@ -461,8 +560,12 @@ if (dediprog_set_spi_voltage(0x0)) return 1; + if (usb_release_interface(dediprog_handle, 0)) { + msg_perr("Could not release USB interface!\n"); + return 1; + } if (usb_close(dediprog_handle)) { - msg_perr("Couldn't close USB device!\n"); + msg_perr("Could not close USB device!\n"); return 1; } return 0;

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flashrom November 2010