On Fri, 9 Sep 2011 13:10:47 -0700 Rohit Vijapure dbnk83@motorola.com wrote:
I am trying to mass update the BIOS on MB899 Intel ® CoreTM 2 Duo/CoreTM Duo/ Solo 945GM Mini-ITX Motherboard. I did compile the flashrom by following two modifications as I was getting errors for the global declaration .
*Compilation errors* programmer.h:567: warning: declaration of 'programmer' shadows a global declaration
board_enable.c: In function 'nvidia_mcp_gpio_set': board_enable.c:892: error: too few arguments to function 'pci_get_dev'
*Compilation success with following changes.* *1. Makefile* CFLAGS ?= -Os -Wall #CFLAGS ?= -Os -Wall -Wshadow
*2. board_enable.c* dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); /* dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);*/
hello!
hm. you are using the 0.9.4 snapshot without any modifications (apart from those above) and gcc 4.0.2, right?
Flash image he76.052008 was taken from another machine with proper BIOS using "flashrom -r he76.052008" command.
this board is supported, but needs the following command line arguments to work: flashrom -p internal:boardenable=force -m IBASE:MB899 -w <file>
i am not sure why the autodetection is kinda disabled for this board. if you could mail us the output of flashrom -V and lspci -xxnnvvv we might be able to fix this.
Hi Stefan
Many thanks for your prompt reply. The -m option worked just fine for me. I will test it locally on couple of machine today. flashrom utility is awesome. Kudos to you and the team. Here is the output of the commands.
[root@me11 ~]$ flashrom -V ; lspci -xxnnvvv flashrom v0.9.4-r1395 on Linux 2.6.18.6-2g2g (i686), built with libpci 2.1.99-test8, GCC 4.0.2 20051125 (Red Hat 4.0.2-8), little endian flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OS timer resolution is 1 usecs, 870M loops per second, delay more than 10% too short (got 83% of expected delay), recalculating... 860M loops per second, delay more than 10% too short (got 83% of expected delay), recalculating... 939M loops per second, 10 myus = 9 us, 100 myus = 77 us, 1000 myus = 774 us, 10000 myus = 7995 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "945GM" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "Intel ICH7M" with PCI ID 8086:27b9. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0
Root Complex Register Block address = 0xfed1c000 GCS = 0xb10c64: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled OK. This chipset supports the following protocols: FWH. Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. Lock status for 0x000000 (size 0x010000) is 01, write locked Lock status for 0x010000 (size 0x010000) is 01, write locked Lock status for 0x020000 (size 0x010000) is 01, write locked Lock status for 0x030000 (size 0x010000) is 01, write locked Lock status for 0x040000 (size 0x010000) is 01, write locked Lock status for 0x050000 (size 0x010000) is 01, write locked Lock status for 0x060000 (size 0x010000) is 01, write locked Lock status for 0x070000 (size 0x010000) is 01, write locked Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x9a, id2 0x6d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 No operations were specified.
Restoring PCI config space for 00:1f:0 reg 0xdc 00:00.0 Class 0600: 8086:27a0 (rev 03) Subsystem: 8086:27a0 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort+ <MAbort+ >SERR- <PERR- Latency: 0 Capabilities: [e0] Vendor Specific Information 00: 86 80 a0 27 06 00 90 30 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 a0 27 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
00:02.0 Class 0300: 8086:27a2 (rev 03) Subsystem: 8086:27a2 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fde80000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at ff00 [size=8] Region 2: Memory at d0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at fdf80000 (32-bit, non-prefetchable) [size=256K] Capabilities: [90] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00 10: 00 00 e8 fd 01 ff 00 00 08 00 00 d0 00 00 f8 fd 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 a2 27 30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00
00:02.1 Class 0380: 8086:27a6 (rev 03) Subsystem: 8086:27a2 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 0: Memory at fdf00000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 a6 27 06 00 90 00 03 00 80 03 00 00 80 00 10: 00 00 f0 fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 a2 27 30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00
00:1c.0 Class 0604: 8086:27d0 (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size 01 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fdc00000-fdcfffff Prefetchable memory behind bridge: 00000000fd800000-00000000fd800000 Secondary status: 66Mhz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s unlimited, L1 unlimited Device: Errors: Correctable- Non-Fatal- Fatal+ Unsupported- Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- Device: MaxPayload 128 bytes, MaxReadReq 128 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 1 Link: Latency L0s <256ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk+ ExtSynch- Link: Speed 2.5Gb/s, Width x1 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+ Slot: Number 16, PowerLimit 10.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Unknown, PwrInd Unknown, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [90] #0d [0000] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 d0 27 07 00 10 00 02 00 04 06 01 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 e0 e0 00 00 20: c0 fd c0 fd 81 fd 81 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 40: 10 80 41 01 c0 0f 00 00 04 00 10 00 11 2c 11 01 50: 40 00 11 30 60 05 80 00 00 00 48 01 04 00 00 00 60: 00 00 00 00 00:1c.1 Class 0604: 8086:27d2 (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size 01 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fd700000-fd7fffff Prefetchable memory behind bridge: 00000000fdd00000-00000000fdd00000 Secondary status: 66Mhz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Express Root Port (Slot+) IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s unlimited, L1 unlimited Device: Errors: Correctable- Non-Fatal- Fatal+ Unsupported- Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- Device: MaxPayload 128 bytes, MaxReadReq 128 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 2 Link: Latency L0s <256ns, L1 <4us Link: ASPM Disabled RCB 64 bytes CommClk+ ExtSynch- Link: Speed 2.5Gb/s, Width x1 Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+ Slot: Number 17, PowerLimit 10.000000 Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- Slot: AttnInd Unknown, PwrInd Unknown, Power- Root: Correctable- Non-Fatal- Fatal- PME- Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [90] #0d [0000] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 d2 27 07 00 10 00 02 00 04 06 01 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 d0 d0 00 00 20: 70 fd 70 fd d1 fd d1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 07 02 00 00 40: 10 80 41 01 c0 0f 00 00 04 00 12 00 11 2c 11 02 50: 40 00 11 30 60 05 88 00 00 00 48 01 04 00 00 00 60: 00 00 00 00 00:1d.0 Class 0c03: 8086:27c8 (rev 02) Subsystem: 8086:27c8 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 4: I/O ports at fe00 [size=32] 00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fe 00 00 00 00 00 00 00 00 00 00 86 80 c8 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 09 01 00 00
00:1d.1 Class 0c03: 8086:27c9 (rev 02) Subsystem: 8086:27c9 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at fd00 [size=32] 00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fd 00 00 00 00 00 00 00 00 00 00 86 80 c9 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00
00:1d.2 Class 0c03: 8086:27ca (rev 02) Subsystem: 8086:27ca Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at fc00 [size=32] 00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 86 80 ca 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 03 00 00
00:1d.3 Class 0c03: 8086:27cb (rev 02) Subsystem: 8086:27ca Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 16 Region 4: I/O ports at fb00 [size=32] 00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fb 00 00 00 00 00 00 00 00 00 00 86 80 ca 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 00
00:1d.7 Class 0c03: 8086:27cc (rev 02) (prog-if 20) Subsystem: 8086:27cc Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at fdfff000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 86 80 cc 27 06 00 90 02 02 20 03 0c 00 00 00 00 10: 00 f0 ff fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 cc 27 30: 00 00 00 00 50 00 00 00 00 00 00 00 09 01 00 00
00:1e.0 Class 0604: 8086:2448 (rev e2) (prog-if 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=32 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: fda00000-fdbfffff Prefetchable memory behind bridge: 00000000fd900000-00000000fd900000 Secondary status: 66Mhz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [50] #0d [0000] 00: 86 80 48 24 07 00 10 00 e2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 20 c0 c0 80 22 20: a0 fd b0 fd 91 fd 91 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00
00:1f.0 Class 0601: 8086:27b9 (rev 02) Subsystem: 8086:27b9 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [e0] Vendor Specific Information 00: 86 80 b9 27 07 01 10 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 b9 27 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
00:1f.1 Class 0101: 8086:27df (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: 8086:27df Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: I/O ports at <unassigned> Region 1: I/O ports at <unassigned> Region 2: I/O ports at <unassigned> Region 3: I/O ports at <unassigned> Region 4: I/O ports at f800 [size=16] 00: 86 80 df 27 05 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 f8 00 00 00 00 00 00 00 00 00 00 86 80 df 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00
00:1f.3 Class 0c05: 8086:27da (rev 02) Subsystem: 8086:27da Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at 0500 [size=32] 00: 86 80 da 27 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 05 00 00 00 00 00 00 00 00 00 00 86 80 da 27 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00
01:00.0 Class 0200: 11ab:4362 (rev 15) Subsystem: 1148:4340 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size 01 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fdcfc000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at ee00 [size=256] [virtual] Expansion ROM at fd800000 [disabled] [size=128K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [5c] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] Express Legacy Endpoint IRQ 0 Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag- Device: Latency L0s unlimited, L1 unlimited Device: AtnBtn- AtnInd- PwrInd- Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported- Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s, Port 0 Link: Latency L0s <256ns, L1 unlimited Link: ASPM Disabled RCB 128 bytes CommClk+ ExtSynch- Link: Speed 2.5Gb/s, Width x1 00: ab 11 62 43 07 00 10 00 15 00 00 02 01 00 00 00 10: 04 c0 cf fd 00 00 00 00 01 ee 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 48 11 40 43 30: 00 00 00 00 48 00 00 00 00 00 00 00 0b 01 00 00
02:00.0 Class 0b40: 10ee:1777 Subsystem: 10ee:1777 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, Cache Line Size 01 Interrupt: pin A routed to IRQ 17 [virtual] Expansion ROM at fdd00000 [disabled] [size=1M] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [60] Express Endpoint IRQ 0 Device: Supported: MaxPayload 512 bytes, PhantFunc 1, ExtTag+ Device: Latency L0s unlimited, L1 unlimited Device: AtnBtn- AtnInd- PwrInd- Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported- Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ Device: MaxPayload 128 bytes, MaxReadReq 512 bytes Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s, Port 0 Link: Latency L0s unlimited, L1 unlimited Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch- Link: Speed 2.5Gb/s, Width x1 00: ee 10 77 17 07 00 10 00 00 00 40 0b 01 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ee 10 77 17 30: 00 00 00 00 40 00 00 00 00 00 00 00 07 01 00 00 40: 01 48 03 08 00 00 00 00 05 60 80 00 00 00 00 00 50: 00 00 00 00 00 00 03:01.0 Class 0200: 8086:1076 (rev 05) Subsystem: 8086:1076 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (63750ns min), Cache Line Size 01 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fdba0000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fdb80000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at cf00 [size=64] [virtual] Expansion ROM at fd900000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=0 Dev=0 Func=0 64bit- 133MHz- SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=0, RSCEM- 00: 86 80 76 10 07 00 30 02 05 00 00 02 01 20 00 00 10: 00 00 ba fd 00 00 b8 fd 01 cf 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 76 10 30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 ff 00
03:05.0 Class 0200: 8086:1076 (rev 05) Subsystem: 8086:1076 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (63750ns min), Cache Line Size 01 Interrupt: pin A routed to IRQ 18 Region 0: Memory at fdb60000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fdbc0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at ce00 [size=64] [virtual] Expansion ROM at fd920000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=0 Dev=0 Func=0 64bit- 133MHz- SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=0, RSCEM- 00: 86 80 76 10 07 00 30 02 05 00 00 02 01 20 00 00 10: 00 00 b6 fd 00 00 bc fd 01 ce 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 76 10 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 ff 00
03:07.0 Class 0c00: 104c:8023 (prog-if 10) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (500ns min, 1000ns max), Cache Line Size 01 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fdbff000 (32-bit, non-prefetchable) [size=2K] Region 1: Memory at fdbf8000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 4c 10 23 80 06 00 10 02 00 10 00 0c 01 20 00 00 10: 00 f0 bf fd 00 80 bf fd 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 02 04
03:08.0 Class 0200: 8086:27dc (rev 02) Subsystem: 8086:0000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2000ns min, 14000ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at fdbfe000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at cd00 [size=64] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- 00: 86 80 dc 27 07 00 90 02 02 00 00 02 00 20 00 00 10: 00 e0 bf fd 01 cd 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0f 01 08 38
03:0d.0 Class 0b40: 10ee:0777 Subsystem: 10ee:0777 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Interrupt: pin A routed to IRQ 17 Region 0: Memory at fda00000 (32-bit, non-prefetchable) [size=1M] 00: ee 10 77 07 06 00 00 02 00 00 40 0b 00 20 00 00 10: 00 00 a0 fd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ee 10 77 07 30: 00 00 00 00 00 00 00 00 00 00 00 00 07 01 00 00
With regards
Rohit Vijapure Motorola Mobility. 2450 Walsh Ave Santa Clara, CA 95051 Ph: - 408 235 5720
On Sun, Sep 11, 2011 at 1:04 PM, Stefan Tauner < stefan.tauner@student.tuwien.ac.at> wrote:
On Fri, 9 Sep 2011 13:10:47 -0700 Rohit Vijapure dbnk83@motorola.com wrote:
I am trying to mass update the BIOS on MB899 Intel ® CoreTM 2 Duo/CoreTM Duo/ Solo 945GM Mini-ITX Motherboard. I did compile the flashrom by following two modifications as I was getting errors for the global declaration .
*Compilation errors* programmer.h:567: warning: declaration of 'programmer' shadows a global declaration
board_enable.c: In function 'nvidia_mcp_gpio_set': board_enable.c:892: error: too few arguments to function 'pci_get_dev'
*Compilation success with following changes.* *1. Makefile* CFLAGS ?= -Os -Wall #CFLAGS ?= -Os -Wall -Wshadow
*2. board_enable.c* dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); /* dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);*/
hello!
hm. you are using the 0.9.4 snapshot without any modifications (apart from those above) and gcc 4.0.2, right?
Flash image he76.052008 was taken from another machine with proper BIOS using "flashrom -r he76.052008" command.
this board is supported, but needs the following command line arguments to work: flashrom -p internal:boardenable=force -m IBASE:MB899 -w <file>
i am not sure why the autodetection is kinda disabled for this board. if you could mail us the output of flashrom -V and lspci -xxnnvvv we might be able to fix this.
-- Kind regards/Mit freundlichen Grüßen, Stefan Tauner
-
Rohit Vijapure -
Stefan Tauner