Michael,
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
Thanks a lot in advance! Regards, Carl-Daniel
On 31.10.2009 15:30, Spangler, Mike T wrote:
Carl-Daniel -
I can tell everyone's very busy. Just wanted to make sure that I haven't been forgotten. The system is still up and ready for testing.Mike
-----Original Message----- From: Spangler, Mike T Sent: Friday, September 18, 2009 4:48 PM To: 'Carl-Daniel Hailfinger' Cc: flashrom@flashrom.org Subject: RE: [flashrom] Trial of ARIMA:HDAMA Motherboard
Carl-Daniel -
Yes, we are stuck with factory bios for now and a lot of it's due to our reliance on HP hardware and their maintenance requirements. We do have legacy Linux Networx gear that I could run coreboot on with gPXE. I'll have to investigate that solution at a later date.
Also, the good thing about my method of reading the bios and flashing what I read is that it moves my bios settings with the flash. If you pull the flash off of the factory distribution, you have to redo the bios settings for every node one at a time.
Below is the lspci output per your request:
0000:00:18.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c8 00 0f 74 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 90: 56 04 51 02 00 01 04 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:18.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:18.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: fd 2f 13 bf d0 00 00 00 d7 ff 5e 81 d0 87 9f 90 c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 12 57 44 8d 44 e0 76 fe 8e 08 60 6d c8 54 69 e0: 14 44 63 6b e5 42 f3 db 33 8e 62 1c f4 4c b9 3a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:18.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 08 86 bb c0 60 00 00 00 16 16 16 00 40 d7 be 22 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3c 00 00 80 db e5 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 0c 57 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:19.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c8 00 0f 7c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 56 04 51 02 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 0c 34 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:19.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:19.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 6f 68 15 bf d0 00 00 00 50 3e 50 02 c0 a1 42 d4 c0: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 58 6f ff 13 b4 43 27 ba b5 7f 19 9f 74 7f eb bb e0: f9 f6 cf bb 95 cd f3 bc 7d dc 8d af fd 99 ce a3 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:00:19.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 88 71 e6 db 21 00 00 00 16 16 16 00 c0 d3 be 22 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 36 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 10 55 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:01.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb000000-fb0fffff Prefetchable memory behind bridge: 00000000fb100000-00000000fb000000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] Capabilities: [c0] #08 [0041] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 02 02 40 21 11 20 22 20: 00 fb 00 fb 11 fb 01 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 01 2c 00 00 50: 00 00 03 00 00 00 05 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 c0: 08 00 41 00 22 00 11 11 22 00 00 00 22 04 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 04 04 10 00 04 04 0d 00 04 04 16 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:01.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb100000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 00 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 00 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:02.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb100000-fb0fffff Prefetchable memory behind bridge: 00000000fa000000-00000000faf00000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 03 03 40 21 11 20 a3 20: 10 fb 00 fb 01 fa f1 fa 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 05 00 1f 00 00 00 00 00 00 00 00 00 01 2c 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 c3 00 10 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:02.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb101000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 10 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 10 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:03.0 Class 0604: 1022:7460 (rev 07) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 00001000-00001fff Memory behind bridge: f8000000-f90fffff Prefetchable memory behind bridge: fb100000-fb0fffff Expansion ROM at 00001000 [disabled] [size=4K] BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [c0] #08 [0083] Capabilities: [f0] #08 [8000] 00: 22 10 60 74 47 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 01 04 04 40 10 10 00 22 20: 00 f8 00 f9 10 fb 00 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0f 08 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 83 00 22 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 0f 00 08 00 11 00 0f 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:04.0 Class 0601: 1022:7468 (rev 05) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 30 07 c0 01 00 00 02 9f fd 00 01 00 00 00 c0 50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:04.1 Class 0101: 1022:7469 (rev 03) (prog-if 8a [Master SecP PriP]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Region 4: I/O ports at 0f00 [size=16] 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 f0 0f 00 00 00 00 00 5e 5e 5e 20 2a 00 ff 20 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:04.2 Class 0c05: 1022:746a (rev 02) Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: I/O ports at 2400 00: 22 10 6a 74 01 00 00 02 02 00 05 0c 00 40 00 00 10: 01 24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:01:04.3 Class 0000: 1022:746b (rev 05) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 d1 00 04 00 00 00 00 20 14 10 00 00 00 00 00 50: 00 80 00 00 0f 00 00 00 01 20 00 00 00 00 00 00 60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 54 ac 76 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:02:03.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb000000 (64-bit, non-prefetchable) [size=1026M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfb626b00cc0528 Data: 0109 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 00 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 20 40 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 00 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 00 00 0a 80 a0 22 05 00 86 00 28 05 cc 00 60: 6b 62 fb fc 09 01 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 9f 13 88 f6 34 00 13 04 82 10 08 00 90: 09 92 00 01 83 01 00 00 00 00 00 00 83 01 00 00 a0: 00 00 00 00 bb 00 00 00 00 00 00 00 cd 01 00 00 b0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 c0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 d0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 e0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 f0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6
0000:02:04.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb010000 (64-bit, non-prefetchable) [size=106M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfd56ebfbf37f4c Data: eff5 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 01 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 ad 06 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 b8 00 f7 e5 fe 79 05 00 86 00 4c 7f f3 fb 60: eb 56 fd fc f5 ef 00 00 9a 02 02 10 00 00 3f 76 70: be 12 00 00 df 00 00 00 50 00 00 00 00 00 00 00 80: 03 58 b8 00 5f bf f5 eb 34 00 00 00 fe 10 08 00 90: 01 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:03:01.0 Class 0280: 14c1:8043 (rev 04) Subsystem: 14c1:8043 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Interrupt: pin A routed to IRQ 17 Region 0: Memory at fa000000 (64-bit, prefetchable) Capabilities: [44] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [54] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=3 Dev=1 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=3, DMOST=0, DMCRS=2, RSCEM-00: c1 14 43 80 42 00 30 80 04 00 80 02 10 40 00 00 10: 0c 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 14 43 80 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 55 05 54 80 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 07 00 00 00 08 03 63 08 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ac 00 60 dd 48 b1 80
0000:04:00.0 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9000000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 80 00 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:04:00.1 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9001000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 00 00 10: 00 10 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:04:00.2 Class 0c03: 1022:7463 (rev 02) (prog-if 20) Subsystem: 1022:7463 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9003000 (32-bit, non-prefetchable) Region 1: Memory at f9004000 (32-bit, non-prefetchable) [size=32] Capabilities: [80] #0a [4000] Capabilities: [88] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 63 74 02 00 10 02 02 20 03 0c 00 40 00 00 10: 00 30 00 f9 00 40 00 f9 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 63 74 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00 40: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 22 10 63 74 01 00 00 00 40 30 00 01 00 00 00 00 80: 0a 88 00 40 00 00 00 00 01 00 82 fe 00 00 00 00 90: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000:04:06.0 Class 0300: 1002:4752 (rev 27) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 0 Region 0: Memory at f8000000 (32-bit, non-prefetchable) Region 1: I/O ports at 1000 [size=256] Region 2: Memory at f9002000 (32-bit, non-prefetchable) [size=4K] Capabilities: [5c] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 52 47 83 00 90 02 27 00 00 03 10 40 00 00 10: 00 00 00 f8 01 10 00 00 00 20 00 f9 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 5c 00 00 00 00 00 00 00 00 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 3:18 PM To: Spangler, Mike T Cc: flashrom@flashrom.org Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
Hi Mike,
On 18.09.2009 18:55, Spangler, Mike T wrote:
I've corrected my email and am now sending to the group.
Thanks.
Of course I'd prefer it if you tried to flash coreboot (new name of LinuxBIOS) to these boards, but that's your choice. Anyway, you said you have the factory BIOS around somewhere. Is it the one at http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ?
I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it.
That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice.
So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios.
That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512
This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable.
flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does.
Hmm ok. I think we have enough docs to iterate through all possible board enables. How many of these boards do you have (in case we trash the ROM of one of them)?
The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares.
Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board.
Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options.
Regards, Carl-Daniel
Am Donnerstag, den 18.02.2010, 20:59 +0100 schrieb Carl-Daniel Hailfinger:
Michael,
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
First result: The BIOS is a new-style Phoenix BIOS image with the board enable code appended to the ROM. The idea of cutting the first 512K to get the BIOS image is correct. This file format is usually distributed with the extension ".WPH".
Regards, Michael Karcher
Am Donnerstag, den 18.02.2010, 23:40 +0100 schrieb Michael Karcher:
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
First result: The BIOS is a new-style Phoenix BIOS image with the board enable code appended to the ROM. The idea of cutting the first 512K to get the BIOS image is correct. This file format is usually distributed with the extension ".WPH".
The BIOS upgrade does not contain an GPIO board enable in the upgrade code. I would guess that the GPIO based boot block write protection that was observed on this board is already disabled in startup code by the vendor.
Mike, do you have a board with the vendor BIOS and a coreboot board, both running linux, at hand? If yes, I can send you a tool that dumps GPIO configuration for both the chipset and the SuperIO, so we can compare the differences. Beforehands you should check whether flashrom works on a board with vendor the BIOS. If yes, the crucial point is really hidden in the POST code.
As I understand it, you have a lot of boards to flash, so hot-swap-flashing in another board is not an option for you.
Regards, Michael Karcher
On 19.02.2010 00:12, Michael Karcher wrote:
Am Donnerstag, den 18.02.2010, 23:40 +0100 schrieb Michael Karcher:
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
First result: The BIOS is a new-style Phoenix BIOS image with the board enable code appended to the ROM. The idea of cutting the first 512K to get the BIOS image is correct. This file format is usually distributed with the extension ".WPH".
The BIOS upgrade does not contain an GPIO board enable in the upgrade code. I would guess that the GPIO based boot block write protection that was observed on this board is already disabled in startup code by the vendor.
Mike, do you have a board with the vendor BIOS and a coreboot board, both running linux, at hand? If yes, I can send you a tool that dumps GPIO configuration for both the chipset and the SuperIO, so we can compare the differences. Beforehands you should check whether flashrom works on a board with vendor the BIOS. If yes, the crucial point is really hidden in the POST code.
As I understand it, you have a lot of boards to flash, so hot-swap-flashing in another board is not an option for you.
An alternative way to the goal: Finding out the source of the WP# (write protect) and/or BPL# (boot block protect) pins with a continuity tester (or visual inspection) might help a lot. For example, if you can trace them to your NSC PC87360 SuperI/O, we can probably go toggle all GPIO lines there and be successful. If you can trace them to the southbridge, that helps as well. Now if you manage to track down the exact pin on the southbridge or superio, we can just look up the associated GPIO in the datasheet, and code it up pretty easily.
Note: I'm sure you know it, but I want to state it for legal reasons: Never use the continuity tester on a board that is attached to any power source.
Regards, Carl-Daniel
Michael, Carl-Daniel -
Sorry was away on a trip. See my answers below:
-----Original Message----- From: Michael Karcher [mailto:flashrom@mkarcher.dialup.fu-berlin.de] Sent: Thursday, February 18, 2010 3:12 PM To: Carl-Daniel Hailfinger Cc: 'flashrom@flashrom.org'; Spangler, Mike T Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
Am Donnerstag, den 18.02.2010, 23:40 +0100 schrieb Michael Karcher:
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
First result: The BIOS is a new-style Phoenix BIOS image with the board enable code appended to the ROM. The idea of cutting the first 512K to get the BIOS image is correct. This file format is usually distributed with the extension ".WPH".
The BIOS upgrade does not contain an GPIO board enable in the upgrade code. I would guess that the GPIO based boot block write protection that was observed on this board is already disabled in startup code by the vendor.
Mike, do you have a board with the vendor BIOS and a coreboot board, both running linux, at hand? If yes, I can send you a tool that dumps GPIO configuration for both the chipset and the SuperIO, so we can compare the differences. Beforehands you should check whether flashrom works on a board with vendor the BIOS. If yes, the crucial point is really hidden in the POST code.
Yes. I have both vendor BIOS and LinuxBios systems all running Linux. If you send me your GPIO code I'll run it for you on both systems. Don't think flashrom will work with vendor BIOS, but will try.
As I understand it, you have a lot of boards to flash, so hot-swap-flashing in another board is not an option for you.
Yes. You are correct.
Regards, Michael Karcher
Carl-Daniel -
Many thanks for opening up this case again. I can probe with a continuity tester, but would need to know specific pin locations to try. Do you have any generic info on doing this?
Mike
-----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Thursday, February 18, 2010 3:47 PM To: Michael Karcher Cc: flashrom; Spangler, Mike T Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
On 19.02.2010 00:12, Michael Karcher wrote:
Am Donnerstag, den 18.02.2010, 23:40 +0100 schrieb Michael Karcher:
could you please take care of this one? Mike has been waiting for 5 months to get a solution, and a stream of unlucky events caused his request to end up on the TODO list each time.
First result: The BIOS is a new-style Phoenix BIOS image with the board enable code appended to the ROM. The idea of cutting the first 512K to get the BIOS image is correct. This file format is usually distributed with the extension ".WPH".
The BIOS upgrade does not contain an GPIO board enable in the upgrade code. I would guess that the GPIO based boot block write protection that was observed on this board is already disabled in startup code by the vendor.
Mike, do you have a board with the vendor BIOS and a coreboot board, both running linux, at hand? If yes, I can send you a tool that dumps GPIO configuration for both the chipset and the SuperIO, so we can compare the differences. Beforehands you should check whether flashrom works on a board with vendor the BIOS. If yes, the crucial point is really hidden in the POST code.
As I understand it, you have a lot of boards to flash, so hot-swap-flashing in another board is not an option for you.
An alternative way to the goal: Finding out the source of the WP# (write protect) and/or BPL# (boot block protect) pins with a continuity tester (or visual inspection) might help a lot. For example, if you can trace them to your NSC PC87360 SuperI/O, we can probably go toggle all GPIO lines there and be successful. If you can trace them to the southbridge, that helps as well. Now if you manage to track down the exact pin on the southbridge or superio, we can just look up the associated GPIO in the datasheet, and code it up pretty easily.
Note: I'm sure you know it, but I want to state it for legal reasons: Never use the continuity tester on a board that is attached to any power source.
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Michael Karcher -
Spangler, Mike T