Author: stefanct Date: Sat Oct 27 02:06:02 2012 New Revision: 1616 URL: http://flashrom.org/trac/flashrom/changeset/1616
Log: Add support for Atmel AT26DF041.
Wicked chip: No WRSR, no write enable command (but swallows our default one without a problem), supports an auto-erasing page write (but even without that page writes are recommended to write the whole page i.e. operate on a completely erased page), mad requirements on block refreshments if only partly written.
Found on my Intel D946GZIS and tested with my serprog in situ. Using the page write by setting JEDEC_BYTE_PROGRAM to 0x11 and using the spi_chip_write_256 command greatly improves performance and works flawlessly.
Signed-off-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at Acked-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at
Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/spi.h trunk/spi25.c
Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/chipdrivers.h Sat Oct 27 02:06:02 2012 (r1616) @@ -41,7 +41,9 @@ int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/flashchips.c Sat Oct 27 02:06:02 2012 (r1616) @@ -1795,18 +1795,24 @@ .total_size = 512, .page_size = 256, /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { + .eraseblocks = { {256, 2048} }, + .block_erase = spi_block_erase_81, + }, { + .eraseblocks = { {2 * 1024, 256} }, + .block_erase = spi_block_erase_50, + }, { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, } - }, - .write = NULL /* Incompatible Page write */, - .read = spi_chip_read, + }, /* Supports also an incompatible page write (of exactly 256 B) and an auto-erasing write. */ + .write = spi_chip_write_1, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, /* 3.0-3.6V for higher speed, 2.7-3.6V normal */ },
Modified: trunk/spi.h ============================================================================== --- trunk/spi.h Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/spi.h Sat Oct 27 02:06:02 2012 (r1616) @@ -76,11 +76,21 @@ #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00
+/* Block Erase 0x50 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_50 0x50 +#define JEDEC_BE_50_OUTSIZE 0x04 +#define JEDEC_BE_50_INSIZE 0x00 + /* Block Erase 0x52 is supported by SST and old Atmel chips. */ #define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00
+/* Block Erase 0x81 is supported by Atmel AT26DF chips. */ +#define JEDEC_BE_81 0x81 +#define JEDEC_BE_81_OUTSIZE 0x04 +#define JEDEC_BE_81_INSIZE 0x00 + /* Block Erase 0xd8 is supported by EON/Macronix chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04
Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Fri Oct 26 18:49:15 2012 (r1615) +++ trunk/spi25.c Sat Oct 27 02:06:02 2012 (r1616) @@ -741,6 +741,86 @@ return 0; }
+int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_50_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_50, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 10 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { +/* .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { */ + .writecnt = JEDEC_BE_81_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_81, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 8 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen) {
On Sat, Oct 27, 2012 at 1:06 AM, repository service svn@flashrom.org wrote:
Wicked chip: No WRSR, no write enable command (but swallows our default one without a problem), supports an auto-erasing page write (but even without that page writes are recommended to write the whole page i.e. operate on a completely erased page), mad requirements on block refreshments if only partly written.
Sounds familiar. The AT45DB chips I've looked at have a fairly similar erase hierarchy and exactly the same page refresh requirements if you're only updating some of the pages within a sector. The command set's slightly different, of course. Weird chips.
-
Aidan Thornton -
repository service