NVIDIA CK804: TYAN VX50 B4985: unexpected second chipset match: "NVIDIA CK804"
Dear flashrom folks, We still have some very old systems, where we need to update the firmware so that it can start GRUB from the MBR. The systems seem to consists out of two boards with a separate chipset and flash ROM chip. Reading the 1 MB SST49LF080A seems to work. I haven’t tried writing yet. ``` $ sudo ./flashrom -p internal -r tyan-vx50-b4985.rom flashrom p1.0-148-ge2cbb12 on Linux 4.14.87.mx64.236 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "NVIDIA CK804". Enabling flash write... OK. Warning: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom@flashrom.org with 'CHIPSET: your board name' in the subject line. Found SST flash chip "SST49LF080A" (1024 kB, LPC) mapped at physical address 0x00000000fff00000. Reading flash... done. $ lspci -nn 00:00.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:005e] (rev a4) 00:01.0 ISA bridge [0601]: NVIDIA Corporation CK804 ISA Bridge [10de:0051] (rev f1) 00:01.1 SMBus [0c05]: NVIDIA Corporation CK804 SMBus [10de:0052] (rev a2) 00:02.0 USB controller [0c03]: NVIDIA Corporation CK804 USB Controller [10de:005a] (rev a2) 00:02.1 USB controller [0c03]: NVIDIA Corporation CK804 USB Controller [10de:005b] (rev a4) 00:06.0 IDE interface [0101]: NVIDIA Corporation CK804 IDE [10de:0053] (rev f3) 00:07.0 IDE interface [0101]: NVIDIA Corporation CK804 Serial ATA Controller [10de:0054] (rev f3) 00:08.0 IDE interface [0101]: NVIDIA Corporation CK804 Serial ATA Controller [10de:0055] (rev f3) 00:09.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCI Bridge [10de:005c] (rev f2) 00:0a.0 Bridge [0680]: NVIDIA Corporation CK804 Ethernet Controller [10de:0057] (rev f3) 00:0b.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0c.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0d.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0e.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev a3) 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:19.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:19.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:19.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:19.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:19.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1a.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1a.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1a.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1a.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1a.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1b.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1b.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1b.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1b.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1b.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1c.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1c.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1c.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1c.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1c.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1d.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1d.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1d.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1d.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1d.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1e.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1e.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1e.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1e.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1e.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 00:1f.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] 00:1f.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map [1022:1201] 00:1f.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller [1022:1202] 00:1f.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control [1022:1203] 00:1f.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control [1022:1204] 01:06.0 Ethernet controller [0200]: Intel Corporation 82541GI Gigabit Ethernet Controller [8086:1076] (rev 05) 01:09.0 VGA compatible controller [0300]: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core) [18ca:0020] 05:00.0 RAID bus controller [0104]: 3ware Inc 9650SE SATA-II RAID PCIe [13c1:1004] (rev 01) 0a:00.0 RAID bus controller [0104]: 3ware Inc 9690SA SAS/SATA-II RAID PCIe [13c1:1005] (rev 01) 80:00.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:005e] (rev a4) 80:01.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:00d3] (rev f1) 80:0a.0 Bridge [0680]: NVIDIA Corporation CK804 Ethernet Controller [10de:0057] (rev f3) 80:0b.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0c.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0d.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0e.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev a3) ``` I uploaded the verbose logs [1]. Does flashrom have the infrastructure to read (and write) the second chip? Kind regards, Paul [1]: https://paste.flashrom.org/view.php?id=3226
Reply below. On Fri, Oct 04, 2019 at 12:17:17PM +0200, Paul Menzel wrote:
Dear flashrom folks,
We still have some very old systems, where we need to update the firmware so that it can start GRUB from the MBR.
The systems seem to consists out of two boards with a separate chipset and flash ROM chip.
Reading the 1 MB SST49LF080A seems to work. I haven’t tried writing yet.
``` $ sudo ./flashrom -p internal -r tyan-vx50-b4985.rom flashrom p1.0-148-ge2cbb12 on Linux 4.14.87.mx64.236 (x86_64) flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "NVIDIA CK804". Enabling flash write... OK. Warning: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom@flashrom.org with 'CHIPSET: your board name' in the subject line. Found SST flash chip "SST49LF080A" (1024 kB, LPC) mapped at physical address 0x00000000fff00000. Reading flash... done. $ lspci -nn 00:00.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:005e] (rev a4) 00:01.0 ISA bridge [0601]: NVIDIA Corporation CK804 ISA Bridge [10de:0051] (rev f1) 00:01.1 SMBus [0c05]: NVIDIA Corporation CK804 SMBus [10de:0052] (rev a2) 00:02.0 USB controller [0c03]: NVIDIA Corporation CK804 USB Controller [10de:005a] (rev a2) 00:02.1 USB controller [0c03]: NVIDIA Corporation CK804 USB Controller [10de:005b] (rev a4) 00:06.0 IDE interface [0101]: NVIDIA Corporation CK804 IDE [10de:0053] (rev f3) 00:07.0 IDE interface [0101]: NVIDIA Corporation CK804 Serial ATA Controller [10de:0054] (rev f3) 00:08.0 IDE interface [0101]: NVIDIA Corporation CK804 Serial ATA Controller [10de:0055] (rev f3) 00:09.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCI Bridge [10de:005c] (rev f2) 00:0a.0 Bridge [0680]: NVIDIA Corporation CK804 Ethernet Controller [10de:0057] (rev f3) 00:0b.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0c.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0d.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 00:0e.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev a3) ~ snip ~ 80:00.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:005e] (rev a4) 80:01.0 Memory controller [0580]: NVIDIA Corporation CK804 Memory Controller [10de:00d3] (rev f1) 80:0a.0 Bridge [0680]: NVIDIA Corporation CK804 Ethernet Controller [10de:0057] (rev f3) 80:0b.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0c.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0d.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev f3) 80:0e.0 PCI bridge [0604]: NVIDIA Corporation CK804 PCIE Bridge [10de:005d] (rev a3) ```
I uploaded the verbose logs [1].
Does flashrom have the infrastructure to read (and write) the second chip?
Probably doesn't need it... https://github.com/flashrom/flashrom/commit/89bed6d83606c26445b088f483387377... was added it made assumptions about how existing chipset enables worked... Apparently when CK804 support was first added (before the above commit) all matched chips had an enable procedure run against them. Apparently the "A01" revision (I'm presuming) of the CK804 needed a workaround for some or all of the secondary CK804 chips in the system, and the intent was that the chipset enable procedure would handle both that workaround and the enable on the LPC bridge on the primary CK804. Your board probably only has a single LPC flash chip on the LPC bus hosted by [10de:0051] located at 00:01.0. I've never heard of flash chip(s) existing on multiple independent LPC busses in the same system. [10de:00d3] is the alter-ego of the CK804 LPC bridge when it's not hosting the system's LPC bus. I would expect you can ignore this warning, as your CK804 seems to be a "rev f1", which may be newer than A0 or A01 or A1. Assuming your board doesn't need a special WP# deassert via GPIO, I would expect flashrom should work for you. Beware of course of obliterating any board-specific data in your existing ROM image. Your Ethernet MAC addresses are most likely in the ROM image, so care should be taken to preserve them. Jonathan Kollasch
participants (2)
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Jonathan A. Kollasch -
Paul Menzel