Tyan S2915 OEM / HP xw9400 now supported

[Carl-Daniel Hailfinger]

Hi,

flashrom should work fine since version 0.9.2 revision 1008 on all Tyan
S2915 OEM boards.
The reason for the failing access was that those boards have two MCP55
LPC bridges. flashrom enabled the first LPC bridge (oddball PCI class)
instead of the second one (ISA bridge PCI class). Since we don't have
any reports of PCI ID 10de:0361 being used as "real" primary LPC bridge,
we blacklisted that ID for now until class checking is in place (which
may break on other boards with buggy BIOS, not sure). The "real" LPC
bridge on this board has the PCI ID

I'd appreciate full output of
flashrom -V
with latest flashrom (at least 0.9.2-r1008).

Thanks to everyone who tested and provided lspci output.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

[Nils-Helge Garli Hegvik]

flashrom -v output attached.

Nils-H


On Sat, May 22, 2010 at 10:05 AM, Carl-Daniel Hailfinger
<[e-mail]> wrote:
> Hi,
>
> flashrom should work fine since version 0.9.2 revision 1008 on all Tyan
> S2915 OEM boards.
> The reason for the failing access was that those boards have two MCP55
> LPC bridges. flashrom enabled the first LPC bridge (oddball PCI class)
> instead of the second one (ISA bridge PCI class). Since we don't have
> any reports of PCI ID 10de:0361 being used as "real" primary LPC bridge,
> we blacklisted that ID for now until class checking is in place (which
> may break on other boards with buggy BIOS, not sure). The "real" LPC
> bridge on this board has the PCI ID
>
> I'd appreciate full output of
> flashrom -V
> with latest flashrom (at least 0.9.2-r1008).
>
> Thanks to everyone who tested and provided lspci output.
>
> Regards,
> Carl-Daniel

[Nicolas AVELINE]

Hi

this works fine !


flashrom v0.9.2-r1023 on Linux 2.6.32-22-generic (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
Found chip "SST SST49LF080A" (1024 KB, LPC) at physical address 0xfff00000.
No operations were specified.
> Date: Sat, 22 May 2010 10:05:30 +0200
> From: [e-mail]
> To: [e-mail]
> CC: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
> Subject: Tyan S2915 OEM / HP xw9400 now supported
>
> Hi,
>
> flashrom should work fine since version 0.9.2 revision 1008 on all Tyan
> S2915 OEM boards.
> The reason for the failing access was that those boards have two MCP55
> LPC bridges. flashrom enabled the first LPC bridge (oddball PCI class)
> instead of the second one (ISA bridge PCI class). Since we don't have
> any reports of PCI ID 10de:0361 being used as "real" primary LPC bridge,
> we blacklisted that ID for now until class checking is in place (which
> may break on other boards with buggy BIOS, not sure). The "real" LPC
> bridge on this board has the PCI ID
>
> I'd appreciate full output of
> flashrom -V
> with latest flashrom (at least 0.9.2-r1008).
>
> Thanks to everyone who tested and provided lspci output.
>
> Regards,
> Carl-Daniel

_________________________________________________________________
La boîte mail NOW Génération vous permet de réunir toutes vos boîtes mail dans Hotmail !
http://www.windowslive.fr/hotmail/nowgeneration/

[Nicolas AVELINE]

hi !

i tryed to flash a tyan bios but he was 2kB longer from the bios that i read with  flashrom.

I use dd to make it fit in 1MB.

But now i can't flash because there is a write protection.

On a forum i have seen that you should link pin 7 and 32 of the rom chip.

this disable write protection.

So flashrom was able to write, but did stop at 0xF000.

Now my motherboard dont boot anymore.

I'am buying a chip + a plcc32 socket on ebay.

I will try again when i receive the chip, because it is very interessant !

Read of bios work very well, write not because of the write protection.

more read here => http://forums.bit-tech.net/showthread.php?p=2319331

Nicolas Aveline
From: [e-mail]
To: [e-mail]; [e-mail]
CC: [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: RE: Tyan S2915 OEM / HP xw9400 now supported
Date: Tue, 1 Jun 2010 03:50:27 +0200








Hi

this works fine !


flashrom v0.9.2-r1023 on Linux 2.6.32-22-generic (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
Found chip "SST SST49LF080A" (1024 KB, LPC) at physical address 0xfff00000.
No operations were specified.
> Date: Sat, 22 May 2010 10:05:30 +0200
> From: [e-mail]
> To: [e-mail]
> CC: [e-mail]; [e-mail]; [e-mail]; [e-mail]; [e-mail]
> Subject: Tyan S2915 OEM / HP xw9400 now supported
>
> Hi,
>
> flashrom should work fine since version 0.9.2 revision 1008 on all Tyan
> S2915 OEM boards.
> The reason for the failing access was that those boards have two MCP55
> LPC bridges. flashrom enabled the first LPC bridge (oddball PCI class)
> instead of the second one (ISA bridge PCI class). Since we don't have
> any reports of PCI ID 10de:0361 being used as "real" primary LPC bridge,
> we blacklisted that ID for now until class checking is in place (which
> may break on other boards with buggy BIOS, not sure). The "real" LPC
> bridge on this board has the PCI ID
>
> I'd appreciate full output of
> flashrom -V
> with latest flashrom (at least 0.9.2-r1008).
>
> Thanks to everyone who tested and provided lspci output.
>
> Regards,
> Carl-Daniel

Votre vie privée l'est-elle vraiment ? Internet Explorer 8 vous protège gratuitement ! 		 	   		  
_________________________________________________________________
Découvrez Windows Phone 7 : Une nouvelle ère de téléphones !
http://www.microsoft.com/windowsmobile/fr-fr/cmpn1/windowsphone7series/defau...

[Michael Karcher]

Am Dienstag, den 01.06.2010, 17:22 +0200 schrieb Nicolas AVELINE:
> On a forum i have seen that you should link pin 7 and 32 of the rom
> chip. this disable write protection.
> You wouldn't have needed to do that, if you applied the patch from
> http://patchwork.coreboot.org/patch/1426/ (very recent).
> So flashrom was able to write, but did stop at 0xF000.
> Because your chips has *two* regions. The main region is 0..0xEFFFF, and
> protected by pin 7 (#WP), while the boot block region is
> 0xF0000..0xFFFFF and protected by pin 8 (#TBL - Top Block Lock).

On the HP xw9400, #WP can be controlled by software, and the patch
mentioned above disables write protection using pin 7. I just committed
the patch as r1025. On the other hand, #TBL (pin 8) can not be
controlled in software. There is an unpopulated Jumper position on your
mainboard, next to the fuse F2. If you short these two pins (or connect
pins 8 and 32 of the flash chip), protection of the boot block is
disabled.
> Now my motherboard dont boot anymore.
> That's because flashrom left the main block in an erased state when it
> found out that the boot block can not be erased. When you had to cut
> your BIOS, it's most likely Phoenix. You have chances that you can
> recover if you connect a USB *floppy* drive (or an internal one, if your
> board supports it) and put in a very special Phoenix Crisis Recovery
> Disk. An USB flash drive does not work.

Regards,
  Michael Karcher

[Nils-Helge Garli Hegvik]

Hi!

I tried the same thing. I was able to write the Tyan BIOS (with the
'dd' trick). However, sincen aparently the boot block is write
protected, I get some system write errors on boot, and it takes an
awful long time to boot. But at least it boots... I tried flashing the
old xw9400 BIOS back with no luck. This is the error I get:
http://flashrom.pastebin.com/KNNiTJ0x

It also sees that I get some problems with the SATA-controllers, but
that might be related to the BIOS not functioning properly I guess.

Nils-Helge Garli Hegvik

On Tue, Jun 1, 2010 at 5:22 PM, Nicolas AVELINE <[e-mail]> wrote:
> hi !
>
> i tryed to flash a tyan bios but he was 2kB longer from the bios that i read
> with  flashrom.
>
> I use dd to make it fit in 1MB.
>
> But now i can't flash because there is a write protection.
>
> On a forum i have seen that you should link pin 7 and 32 of the rom chip.
>
> this disable write protection.
>
> So flashrom was able to write, but did stop at 0xF000.
>
> Now my motherboard dont boot anymore.
>
> I'am buying a chip + a plcc32 socket on ebay.
>
> I will try again when i receive the chip, because it is very interessant !
>
> Read of bios work very well, write not because of the write protection.
>
> more read here => http://forums.bit-tech.net/showthread.php?p=2319331
>
> Nicolas Aveline
> ________________________________
> From: [e-mail]
> To: [e-mail]; [e-mail]
> CC: [e-mail]; [e-mail]; [e-mail]; [e-mail]
> Subject: RE: Tyan S2915 OEM / HP xw9400 now supported
> Date: Tue, 1 Jun 2010 03:50:27 +0200
>
> Hi
>
> this works fine !
>
> flashrom v0.9.2-r1023 on Linux 2.6.32-22-generic (x86_64), built with libpci
> 3.0.0, GCC 4.4.3, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
>
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "NVIDIA MCP55", enabling flash write... OK.
> This chipset supports the following protocols: Non-SPI.
> Found chip "SST SST49LF080A" (1024 KB, LPC) at physical address 0xfff00000.
> No operations were specified.
> > Date: Sat, 22 May 2010 10:05:30 +0200
> > From: [e-mail]
> > To: [e-mail]
> > CC: [e-mail]; [e-mail]; [e-mail]; [e-mail];
> > [e-mail]
> > Subject: Tyan S2915 OEM / HP xw9400 now supported
> >
> > Hi,
> >
> > flashrom should work fine since version 0.9.2 revision 1008 on all Tyan
> > S2915 OEM boards.
> > The reason for the failing access was that those boards have two MCP55
> > LPC bridges. flashrom enabled the first LPC bridge (oddball PCI class)
> > instead of the second one (ISA bridge PCI class). Since we don't have
> > any reports of PCI ID 10de:0361 being used as "real" primary LPC bridge,
> > we blacklisted that ID for now until class checking is in place (which
> > may break on other boards with buggy BIOS, not sure). The "real" LPC
> > bridge on this board has the PCI ID
> >
> > I'd appreciate full output of
> > flashrom -V
> > with latest flashrom (at least 0.9.2-r1008).
> >
> > Thanks to everyone who tested and provided lspci output.
> >
> > Regards,
> > Carl-Daniel
>
> ________________________________
> Votre vie privée l'est-elle vraiment ? Internet Explorer 8 vous protège
> gratuitement !
> ________________________________
> De nouvelles Emoticones sur Messenger ? Téléchargez les Emoticones pâte à
> modeler !

[PATCH] Add coreboot IDs to make manual selection of HP xw9400 possible

[Michael Karcher]

Hi Nilse-Helge,

you experience problems trying to flash back to the HP BIOS, because with
the original Tyan BIOS, flashrom is unable to detect you have the HP OEM 
version of the board. This is why flashrom does not remove write protection
anymore. The attached patch adds a coreboot ID for the HP xw9400 board, which
makes it possible to tell flashrom you are on an xw9400 from the command line.

After applying this patch, run
   
flashrom -m hp:xw9400 -w hpbios.bin

This should return you to the original HP BIOS if the boot block write
enable jumper is shorted (the two pins next to F2), or bring you into    
big trouble if the boot block is still write protected.

Regards,
  Michael Karcher

---
 board_enable.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board_enable.c b/board_enable.c
index 69de0f9..a1867be 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1469,7 +1469,7 @@ struct board_pciid_enable board_pciid_enables[] = {
 	{0x1166, 0x0223, 0x103c, 0x320d,  0x102b, 0x0522, 0x103c, 0x31fa, NULL,          "hp",         "dl145_g3",    "HP",          "DL145 G3",              0,   OK, board_hp_dl145_g3_enable},
 	{0x8086, 0x2415, 0x103c, 0x1249,  0x10b7, 0x9200, 0x103c, 0x1246, NULL,          NULL,         NULL,          "HP",          "Vectra VL400",          0,   OK, board_hp_vl400}, 
 	{0x8086, 0x1a30, 0x103c, 0x1a30,  0x8086, 0x2443, 0x103c, 0x2440, "^VL420$",     NULL,         NULL,          "HP",          "VL420 SFF",             0,   OK, intel_ich_gpio22_raise},
-	{0x10de, 0x0369, 0x103c, 0x12fe,  0x10de, 0x0364, 0x103c, 0x12fe, NULL,          NULL,         NULL,          "HP",          "xw9400",                0,   OK, nvidia_mcp_gpio5_raise},
+	{0x10de, 0x0369, 0x103c, 0x12fe,  0x10de, 0x0364, 0x103c, 0x12fe, NULL,          "hp",         "xw9400",      "HP",          "xw9400",                0,   OK, nvidia_mcp_gpio5_raise},
 	{0x8086, 0x27A0,      0,      0,  0x8086, 0x27B9,      0,      0, NULL,          "ibase",      "mb899",       "iBASE",       "MB899",                 0,   NT, intel_ich_gpio26_raise},
 	{0x1166, 0x0205, 0x1014, 0x0347,  0x1002, 0x515E, 0x1014, 0x0325, NULL,          NULL,         NULL,          "IBM",         "x3455",                 0,   OK, board_ibm_x3455},
 	{0x1039, 0x5513, 0x8086, 0xd61f,  0x1039, 0x6330, 0x8086, 0xd61f, NULL,          NULL,         NULL,          "Intel",       "D201GLY",               0,   OK, wbsio_check_for_spi},
-- 
1.7.1