Asus m2n-mx revision 1.06G

Dear reader,

my Asus m2n-mx motherboard seems not supported by Flashrom. The
w39v040c was not found automatically, so I tried a forced read. 
The flashrom dump and the original bios are very similar but not the
same. In case you want to have a look at the dump, I included a link
to the file. If you need extra information, please let me know.

Ted Crilly

Motherboard:
Asus m2n-mx rev. 1.06G

Flashrom (visual inspection):
Winbond PLCC32
w39v040cpz  
4548323002
632fafa

SuperIO (visual inspection):
ITE
it8712f-s
0714-kxs
zm2s50 L

BIOS:
(Bios version 1004 adds protection from downgrading BIOS version)
ftp://ftp.asus.com/pub/ASUS/mb/socketAM2/M2N-MX/M2NX1004.zip

DUMPED BIOS forced read:
(flashrom -f -r -c W39V040C m2n-mx.bios1004_dump)
http://datastructuur.nl/flashrom/m2n-mx.bios1004_dump

[Michael Karcher]

Am Mittwoch, den 17.02.2010, 01:06 +0100 schrieb
[e-mail]:
> my Asus m2n-mx motherboard seems not supported by Flashrom. The
> w39v040c was not found automatically, so I tried a forced read. 
> The flashrom dump and the original bios are very similar but not the
> same.

That's OK. Most modern BIOSses save some system information in the
Flash.
> Motherboard:
> Asus m2n-mx rev. 1.06G

MCP61 + non-SPI flash. Interesting to hear about!

This chipset is not really supported yet. The flash write enable bit for
LPC/FWH flash is the same as in MCP55, which is not yet enabled for
MCP61.
A board enable bit is GPIO31 on the IT8712F chip. To access this chip,
the BIOS sets PCIConf[0x7B] in the ISA bridge to 0x19, accesses the port
(0xA02 in your case) and restores PCIConf[0x7B] of the ISA bridge to
0x20.
Just for reference: The board enable procedure is at 3E5D in the F
segment.

Regards,
  Michael Karcher

[Carl-Daniel Hailfinger]

Hi Ted,

On 17.02.2010 01:06, [e-mail] wrote:
> my Asus m2n-mx motherboard seems not supported by Flashrom. The
> w39v040c was not found automatically, so I tried a forced read.
>
> Asus m2n-mx rev. 1.06G
> w39v040cpz

Can you please retry with flashrom revision 906 (or later)? Output from
flashrom -V
is sufficient for now. Please don't try to write yet, the code is still
untested (but it should work).
Thanks.

Regards,
Carl-Daniel

On Thu, 18 Feb 2010 13:38:49 +0100
Carl-Daniel Hailfinger  wrote:
> Can you please retry with flashrom revision 906 (or later)? Output
> from flashrom -V
> is sufficient for now. Please don't try to write yet, the code is
> still untested (but it should work).
> Thanks.
>
> Regards,
> Carl-Daniel

Hi Carl-Daniel,

Probe and read of the w39v040c work indeed. Thanks Carl-Daniel!

For further testing I will use a pm49fl004 I had lying around. 
A probe and read were successful also. Erasing the chip failed however.

Best regards,
Ted Crilly

[Carl-Daniel Hailfinger]

Hi Ted,

On 18.02.2010 23:44, [e-mail] wrote:
> Probe and read of the w39v040c work indeed. Thanks Carl-Daniel!

Thank you for testing so quickly.
> For further testing I will use a pm49fl004 I had lying around. 
> A probe and read were successful also.

Nice, as I had hoped.
> Erasing the chip failed however.

That's expected with the current source tree. We're in the process of
converting the chip unlock code to a new interface, and right now only a
very small number of chips has the necessary unlock functionality.
> flashrom v0.9.1-r906
> No coreboot table found.
> DMI string 0: "System manufacturer"
> DMI string 1: "System Product Name"
> DMI string 2: "System Version"
> DMI string 3: "ASUSTeK Computer INC."
> DMI string 4: "M2N-MX"
> DMI string 5: "Rev 1.xx"
> Found ITE SuperI/O, id 8712
> Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork...
> ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0
> Guessed flash bus type is LPC

Yay. Our guess worked out just fine.
> Found SMBus device 10de:03eb at 00:01:1
> SPI BAR is at 0x00000000, after clearing low bits BAR is at 0x00000000
> MCP SPI is not used.
> OK.
> This chipset supports the following protocols: LPC.
> Calibrating delay loop... 588M loops per second, 100 myus = 191 us. OK.
> [...]
> Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xda, id2 0x50
> Found chip "Winbond W39V040C" (512 KB, LPC) at physical address 0xfff80000.

I guess we can mark the MCP61 as partially supported now. The failing
erase is a chip issue, not a chipset issue, and will be addressed in due
course.

Regards,
Carl-Daniel

[Michael Karcher]

Am Donnerstag, den 18.02.2010, 23:44 +0100 schrieb
[e-mail]:
> For further testing I will use a pm49fl004 I had lying around. 
> A probe and read were successful also. Erasing the chip failed however.

PM49FL004 is one of the chips where the recent unlock regression
applies: flashrom forgets to unlock the chip, I hope that's the only
reason you see the erase failure. Otherwise, the board might have the
Write Protect pin of the flash chip tied to some GPIO pin of the chipset
or the Super I/O which inhibits writing.

Regards,
  Michael Karcher