Hi,
here is the patch for RTL1839 based NICs. Still got some problems: * Those Nics can have a wide varity of PCI (Vendor) IDs. * Code is instable, "erase" fails but "read" reads only FFs.
It is disabled by default in the Makefile.
Regards, Jörg Fischer
Signed-off-by: Joerg Fischer turboj@gmx.de
Index: flash.h =================================================================== --- flash.h (Revision 999) +++ flash.h (Arbeitskopie) @@ -46,6 +46,10 @@ #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM, #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK, + PROGRAMMER_NICREALTEK2, +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA, #endif @@ -330,7 +334,7 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) +#if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) || (ATAHPT_SUPPORT == 1) || (NICREALTEK_SUPPORT == 1) void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -462,6 +466,18 @@ extern struct pcidev_status drkaiser_pcidev[]; #endif
+/* nicrealtek.c */ +#if NICREALTEK_SUPPORT == 1 +int nicrealtek_init(void); +int nicsmc1211_init(void); +int nicrealtek_shutdown(void); +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); +uint8_t nicrealtek_chip_readb(const chipaddr addr); +extern struct pcidev_status nics_realtek[]; +extern struct pcidev_status nics_realteksmc1211[]; +#endif + + /* satasii.c */ #if SATASII_SUPPORT == 1 int satasii_init(void); Index: flashrom.c =================================================================== --- flashrom.c (Revision 999) +++ flashrom.c (Arbeitskopie) @@ -47,13 +47,17 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT > 1 +#if NIC3COM_SUPPORT+GFXNVIDIA_SUPPORT+DRKAISER_SUPPORT+SATASII_SUPPORT+ATAHPT_SUPPORT+FT2232_SPI_SUPPORT+SERPROG_SUPPORT+BUSPIRATE_SPI_SUPPORT+DEDIPROG_SUPPORT+NICREALTEK_SUPPORT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all external programmers except one. #endif enum programmer programmer = #if NIC3COM_SUPPORT == 1 PROGRAMMER_NIC3COM #endif +#if NICREALTEK_SUPPORT == 1 + PROGRAMMER_NICREALTEK + PROGRAMMER_NICREALTEK2 +#endif #if GFXNVIDIA_SUPPORT == 1 PROGRAMMER_GFXNVIDIA #endif @@ -159,6 +163,42 @@ }, #endif
+#if NICREALTEK_SUPPORT == 1 + { + .name = "nicrealtek", + .init = nicrealtek_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, + { + .name = "nicsmc1211", + .init = nicsmc1211_init, + .shutdown = nicrealtek_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + + #if GFXNVIDIA_SUPPORT == 1 { .name = "gfxnvidia", Index: Makefile =================================================================== --- Makefile (Revision 999) +++ Makefile (Arbeitskopie) @@ -110,6 +110,9 @@ # Always enable Dr. Kaiser for now. CONFIG_DRKAISER ?= yes
+# Disable Realtek NICs for now, not working correctly. +CONFIG_NICREALTEK ?= no + # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATESPI ?= yes
@@ -181,6 +184,14 @@ NEED_PCI := yes endif
+ +ifeq ($(CONFIG_NICREALTEK), yes) +FEATURE_CFLAGS += -D'NICREALTEK_SUPPORT=1' +PROGRAMMER_OBJS += nicrealtek.o +NEED_PCI := yes +endif + + ifeq ($(CONFIG_BUSPIRATESPI), yes) FEATURE_CFLAGS += -D'BUSPIRATE_SPI_SUPPORT=1' PROGRAMMER_OBJS += buspirate_spi.o Index: nicrealtek.c =================================================================== --- nicrealtek.c (Revision 0) +++ nicrealtek.c (Revision 0) @@ -0,0 +1,84 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 TURBO J turboj@gmx.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include "flash.h" + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_VENDOR_ID_SMC1211 0x1113 + +#define BIOS_ROM_ADDR 0xD4 +#define BIOS_ROM_DATA 0xD7 + +struct pcidev_status nics_realtek[] = { + {0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"}, + {}, +}; + +struct pcidev_status nics_realteksmc1211[] = { + {0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"}, + {} +}; + + +int nicrealtek_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0, + nics_realtek, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + + +int nicsmc1211_init(void) +{ + get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0, + nics_realteksmc1211, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int nicrealtek_shutdown(void) +{ + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void nicrealtek_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); + OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); +} + +uint8_t nicrealtek_chip_readb(const chipaddr addr) +{ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +}