On 17.12.2009 10:52, Uwe Hermann wrote:
On Fri, Oct 30, 2009 at 05:24:40AM +0100, Carl-Daniel Hailfinger wrote:
Use the maximum decode size infrastructure.
- Detect max FWH size for Intel
631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10.
- Move IDSEL override before decode size checking for the chipsets
listed above or flashrom will complain based on old values.
- Adjust supported flash buses for the chipsets listed above (none of
them supports LPC or Parallel).
- Detect max parallel size for AMD/National Semiconductor CS5530.
Btw, this also applies CS5530A (which is mostly compatible to the CS5530). I checked the CS5530A datasheet, your code works for both.
Thanks, I updated the changlog.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Committed in r806.
- if (idsel) {
idsel += strlen("fwh_idsel=");fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);We should probably check the return value of strtoul() and handle errors
Yes.
(this can be an extra follow-up patch).
I think we should add a print after each of the cases, so that the user can see how much this board can decode. IMHO we should just _always_ print that info for all chipsets/boards (if known), at least in -V. In the CS5530 case it might also be interesting _why_ 16MB can be decoded (as there are two cases which result in 16MB), so a print would be nice.
Agreed. I'd like to have the decode printing (at least for the end result) in generic code, though. We already perform decodesize vs. chipsize checking
This is material for an extra patch, though.
On my test-board (GX1) the value was 16MB due to CS5530_ENABLE_SA2320, IIRC.
Thanks for testing.
Regards, Carl-Daniel