Author: stefanct Date: Mon Nov 14 00:03:30 2011 New Revision: 1465 URL: http://flashrom.org/trac/flashrom/changeset/1465
Log: Create a directory for documentation files
Move the serprog specification there and document a few things we could not figure out on intel platforms yet.
Signed-off-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Added: trunk/Documentation/ trunk/Documentation/mysteries_intel.txt (contents, props changed) trunk/Documentation/serprog-protocol.txt (contents, props changed) - copied, changed from r1464, trunk/serprog-protocol.txt Deleted: trunk/serprog-protocol.txt
Added: trunk/Documentation/mysteries_intel.txt ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/Documentation/mysteries_intel.txt Mon Nov 14 00:03:30 2011 (r1465) @@ -0,0 +1,18 @@ += BBAR on ICH8 = + There is no sign of BBAR (BIOS Base Address Configuration Register) in the + public datasheet (or specification update) of the ICH8. Also, the offset of + that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + + A0h), so we have no clue if or where it is on ICH8. Out current policy is to + not touch it at all and assume/hope it is 0. + += Accesses beyond region bounds in descriptor mode = + Intel's flash image tool will always expand the last region so that it covers + the whole flash chip, but some boards ship with a different configuration. + It seems that in descriptor mode all addresses outside the used regions can not + be accessed whatsoever. This is not specified anywhere publicly as far as we + could tell. flashrom does not handle this explicitly yet. It will just fail + when trying to touch an address outside of any region. + See also http://www.flashrom.org/pipermail/flashrom/2011-August/007606.html + += Unlocking the ME region = +TODO
Copied and modified: trunk/Documentation/serprog-protocol.txt (from r1464, trunk/serprog-protocol.txt) ==============================================================================