Output from flashrom (from the .rar Glenn provided in a previous mail):
Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. Found chip "SST SST49LF040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! Verifying flash... FAILED at 0x00000000! Expected=0x95, Read=0x49
Output from lspci -vnnxxx attached.
Suggested ids:
Host Bridge KT400: 0x1106, 0x3189, 0x1043, 0x807F ISA Bridge VT8235: 0x1106, 0x3177, 0x1043, 0x808C
Board enable requires two things:
io(0x370) &= ~0x02; io(PM_IO_Base + 0x2C) |= 0x01;
The second scarily translates to: "Enable SMI generation".
The first is (according to carldani) most likely an io range for the super io. The superio is probably an it8712, but we do not know for sure, but there is a good chance that this is about dropping a gpio line. We might then get lucky and might not need SMI at all.
Glenn, please attach the output of superio -Vd, we cannot proceed without that.
Luc Verhaegen.