Hello David,
We have same issue, here. We used some tool, from Intel, to change the layout of Region 0, and now, it comes to 0x001FFFFF. With this, all works.
Another solution, highlighted by Stefan, is to use --layout option. We did not try it yet, though, but it would work with only read or write (I do not remember).
Stephan.
Le 16/01/2015 07:41, David Mirabito a écrit :
Hello,
We have a Rangely-based board and would strongly prefer to be able to update the bios via flashrom, and I'm coming across two issues here:
Attached is the output from './flashrom --programmer internal:laptop=this_is_not_a_laptop -o vanilla.log -VV'
- Note the descriptor table:
--- Details --- Region 0 (Descr.) 0x00000000 - 0x0000ffff Region 1 (BIOS ) 0x00200000 - 0x007fffff Region 2 (ME ) is unused. Region 3 (GbE ) is unused. Region 4 (Platf.) is unused.
The gap between Regions 0 and 1 appears unreadable, and I get transaction failures at 0x00010000. Modifying flashrom to only dump the final 6MB works as expected.
- Given the above modifications (which ideally I'll roll properly
into the layout file infrastructure) I am still having trouble writing to Region 1.
After making sure that nothing is attempting to read or write outside the required range, the write transaction still fails at the first access (see fail.log):
ETransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=0 Running OPCODE 0x20 failed at address 0x400000 (payload length was 0). spi_block_erase_20 failed during command execution at address 0x400000
(interestingly, last time I tried this I had the same error at 0x200000)
It appears to me that it should be writiable, is this not the case?
Thanks for any input! Additionally we may have some input with the BIOS vendor (and ability to write via JTAG or EFIshell), so if there's anything specific we might ask for as far as leaving chipset registers in a certain state, then this may be a posisbility if it comes to that.
Cheers, DavidM
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