Signed-off-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at --- ichspi.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/ichspi.c b/ichspi.c index 0b9db20..4e303d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -62,6 +62,9 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +/* We combine SSFS and SSFC to one lword, + * therefore SSFC bits are off by 8. + * This bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ #define SSFC_RESERVED_MASK 0xf8008100
#define ICH9_REG_FADDR 0x08 /* 32 Bits */ @@ -116,7 +119,7 @@ static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type - uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 + uint8_t atomic; //Use preop: (0: none, 1: preop0 only, 2: both) } OPCODE;
/* Suggested opcode definition: @@ -679,7 +682,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
/* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); - /* keep reserved bits */ + /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); @@ -688,6 +691,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ;
+ /* Set data byte count (DBC) and data cycle bit (DS) */ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS;