On Sat, 23 Feb 2013 23:06:31 +0200 Kyösti Mälkki kyosti.malkki@gmail.com wrote:
I came across two problems using 2 MiB FWH flash on two different boards with old ICH4 and ICH6 chipsets:
First, ICH3/4/5 do not implement fwh_idsel= parameter. If vendor bios had the default map of 1 MiB, it did not even detect 2 MiB flash chips. For this I have patches prepared already.
Thanks for your patches. Since Carl-Daniel has been pulling a Carl-Daniel on these again, I merged them today.
I took a look at the respective datasheets and noticed that ICH2 (and its derivative C-ICH) do also feature those registers. I have changed your patches accordingly before merging them. Even ICH and ICH0 do have similar registers but only for the "first" 4MB, which I have noted in a fixme (only).
Second, a board with ICH6 had all except one 512 kiB range of flash disabled by vendor bios and it would not detect 1MiB and 2MiB flash chips. NOTE: the board actually had 512kiB flash for these logs, but you can see where ther problem is.
Before: (decode-disabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode disabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled ... Maximum FWH chip size: 0x80000 bytes ... Probing for SST SST49LF008C, 1024 kB: Chip size 1024 kB is bigger than supported size 512 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
I used the following as a work-around for ICH6, but this should be derived from fwh_idsel= parameter: $ setpci -s 0:1f.0 0xd8.W=0xf0c0
After: (decode-enabled.txt) 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled Maximum FWH chip size: 0x200000 bytes
Patches welcome, and they would not bitrot over half a year this time, I promise. ;)