On 17.03.2010 01:45, Uwe Hermann wrote:
On Thu, Mar 04, 2010 at 09:00:49PM +0100, Carl-Daniel Hailfinger wrote:
PCI device BARs of all types had only bits 1:0 cleared while reading the address. That was correct for IO BARs, but failed to mask bit 3:2 for MEM BARs, resulting in odd offsets for prefetchable MEM BARs and for 64-bit capable MEM BARs. Mask the correct number of bits for all types of BARs and add some debug printing about BAR type.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Thanks, committed in r946.
Regards, Carl-Daniel