Now checks for the right SMBus device and is compilable.
Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de --- board_enable.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/board_enable.c b/board_enable.c index b5eb63f..2f3a6f4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -552,6 +552,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; + uint16_t devclass; uint8_t tmp;
if ((gpio < 0) || (gpio >= 0x40)) { @@ -566,17 +567,33 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; - default: - /* Newer MCPs use the SMBus Controller */ - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); - switch (dev->device_id) { - case 0x0264: /* MCP51 */ + case 0x0260: /* MCP51 */ + case 0x0364: /* MCP55 */ + /* find SMBus controller on *this* southbridge */ + /* The infamous Tyan S2915-E has two south bridges; they are + easily told apart from each other by the class of the + LPC bridge, but have the same SMBus bridge IDs */ + if (dev->func != 0) { + msg_perr("MCP LCP bridge at unexpected function" + " number %d\n", dev->func); + return -1; + } + + dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); + if (!dev) { + msg_perr("MCP SMBus controller could not be found\n"); + return -1; + } + devclass = pci_read_word(dev, 0x0a); + if (devclass != 0x0C05) { + msg_perr("Unexpected device class %04x for SMBus" + " controller\n", devclass); + return -1; + } break; - default: + default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; - } - break; }
base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ @@ -651,6 +668,31 @@ static int nvidia_mcp_gpio31_raise(const char *name) }
/** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int board_hp_xw9400(const char *name) +{ + struct pci_dev * dev; + uint16_t base; + uint16_t tmp; + dev = pci_get_dev(pacc, 0, 0, 1, 1); /* UGLY HACK! */ + if(!dev) { + fprintf(stderr, "SMBus bridge not found?!\n"); + return -1; + } + base = pci_read_long(dev,0x60) & 0xFF00; + if(base < 0x400) { + fprintf(stderr, "bogus I/O base %04x\n", base); + return -1; + } + tmp = INW(base+2); + tmp &= 0xFEFF; + OUTW(tmp, base+2); + + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1437,6 +1479,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, board_hp_xw9400}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},