[flashrom] [PATCH 3/6] changes macros for SSFS and SSFC bits: - introduce mask macros - add comments - change SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing

[Stefan Tauner]

Signed-off-by: Stefan Tauner 
---
 ichspi.c |   56 ++++++++++++++++++++++++++++++++++----------------------
 1 files changed, 34 insertions(+), 22 deletions(-)

diff --git a/ichspi.c b/ichspi.c
index 4e303d7..9491604 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -43,32 +43,44 @@
 #include "spi.h"

/* ICH9 controller register definition */
+#define ICH9_REG_FADDR		0x08	/* 32 Bits */
+#define ICH9_REG_FDATA0		0x10	/* 64 Bytes */

-#define ICH9_REG_SSFS          0x90	/* 08 Bits */
-#define SSFS_SCIP		0x00000001
-#define SSFS_CDS		0x00000004
-#define SSFS_FCERR		0x00000008
-#define SSFS_AEL		0x00000010
+#define ICH9_REG_SSFS		0x90	/* 08 Bits */
+#define SSFS_SCIP		0x00000001	/* SPI Cycle In Progress */
+#define SSFS_SCIP_OFF		0
+#define SSFS_FDONE		0x00000004	/* Cycle Done Status */
+#define SSFS_FDONE_OFF		2
+#define SSFS_FCERR		0x00000008	/* Flash Cycle Error */
+#define SSFS_FCERR_OFF		3
+#define SSFS_AEL		0x00000010	/* Access Error Log */
+#define SSFS_AEL_OFF		4
 #define SSFS_RESERVED_MASK	0x000000e2

-#define ICH9_REG_SSFC          0x91	/* 24 Bits */
-#define SSFC_SCGO		0x00000200
-#define SSFC_ACS		0x00000400
-#define SSFC_SPOP		0x00000800
-#define SSFC_COP		0x00001000
-#define SSFC_DBC		0x00010000
-#define SSFC_DS			0x00400000
-#define SSFC_SME		0x00800000
-#define SSFC_SCF		0x01000000
-#define SSFC_SCF_20MHZ 0x00000000
-#define SSFC_SCF_33MHZ 0x01000000
+#define ICH9_REG_SSFC		0x91	/* 24 Bits */
+#define SSFC_SCGO		0x00000200	/* SPI Cycle Go */
+#define SSFC_SCGO_OFF		(1 + 8)
+#define SSFC_ACS		0x00000400	/* Atomic Cycle Sequence */
+#define SSFC_ACS_OFF		(2 + 8)
+#define SSFC_SPOP		0x00000800	/* Sequence Prefix Opcode Pointer */
+#define SSFC_SPOP_OFF		(3 + 8)
+#define SSFC_COP		0x00007000	/* Cycle Opcode Pointer */
+#define SSFC_COP_OFF		(4 + 8)
+#define SSFC_DBC		0x003F0000	/* Data Byte Count */
+#define SSFC_DBC_OFF		(8 + 8)
+#define SSFC_DS			0x00400000	/* Data Cycle */
+#define SSFC_DS_OFF		(14 + 8)
+#define SSFC_SME		0x00800000	/* SPI SMI# Enable */
+#define SSFC_SME_OFF		(15 + 8)
+#define SSFC_SCF		0x07000000	/* SPI Cycle Frequency */
+#define SSFC_SCF_OFF		(16 + 8)
+#define SSFC_SCF_20MHZ		0x00000000
+#define SSFC_SCF_33MHZ		0x01000000
 /* We combine SSFS and SSFC to one lword,
  * therefore SSFC bits are off by 8.
  * This bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */
 #define SSFC_RESERVED_MASK	0xf8008100

-#define ICH9_REG_FADDR		0x08	/* 32 Bits */
-#define ICH9_REG_FDATA0		0x10	/* 64 Bytes */
 #define ICH9_REG_PREOP		0x94	/* 16 Bits */
 #define ICH9_REG_OPTYPE		0x96	/* 16 Bits */
 #define ICH9_REG_OPMENU		0x98	/* 64 Bits */
@@ -684,8 +696,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
    temp32 = REGREAD32(ICH9_REG_SSFS);
    /* Keep reserved bits only */
    temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
-	/* clear error status registers */
-	temp32 |= (SSFS_CDS + SSFS_FCERR);
+	/* Clear cycle done and cycle error status registers */
+	temp32 |= (SSFS_FDONE + SSFS_FCERR);
    REGWRITE32(ICH9_REG_SSFS, temp32);

/* Use 20 MHz */
@@ -695,7 +707,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
    if (datalength != 0) {
    	uint32_t datatemp;
    	temp32 |= SSFC_DS;
-		datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
+		datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC);
    	temp32 |= datatemp;
    }

@@ -735,7 +747,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,

/* Wait for Cycle Done Status or Flash Cycle Error. */
    timeout = 100 * 60;	/* 60 ms are 9.6 million cycles at 16 MHz. */
-	while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) &&
+	while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
           --timeout) {
    	programmer_delay(10);
    }