On Sat, Dec 26, 2009 at 02:40:34PM -0600, Chris wrote:
With instruction from twice11 in the IRC channel, I've created a patch enabling erase/write support for the Abit KN8 Ultra motherboard.
Patch is attached.
This motherboard uses the LPC protocol.
Index: board_enable.c
--- board_enable.c (revision 824) +++ board_enable.c (working copy) @@ -474,6 +474,14 @@ }
/**
- Suited for Abit KN8 Ultra: nVidia CK804.
- */
+static int nvidia_mcp_gpio2_lower(const char *name) +{
- return nvidia_mcp_gpio_set(0x02, 0);
+}
+/**
- Suited for MSI K8N Neo4: nVidia CK804.
*/ static int nvidia_mcp_gpio2_raise(const char *name) @@ -1175,6 +1183,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise},
- {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, "Abit", "KN8 Ultra", nvidia_mcp_gpio2_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
Nice work, but stuck on administrativia.
Please provide the output of:
lspci -vvnnxxx superiotool -deV dmidecode
Then this board will be added.
Luc Verhaegen.