Today's systems are quite capable of running 2^32 reads in short time. Some chips may be slow enough to fall off the loop here. This patch is an attempt at debugging a problem we're seeing on the Winbond W39V040C where the standard toggle bit algorithm seems to fail for block erases.
Note: This probably needs a few tweaks before it can be committed.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-detect_excessive_toggle/jedec.c =================================================================== --- flashrom-detect_excessive_toggle/jedec.c (Revision 803) +++ flashrom-detect_excessive_toggle/jedec.c (Arbeitskopie) @@ -33,7 +33,7 @@ return (val ^ (val >> 1)) & 0x1; }
-void toggle_ready_jedec(chipaddr dst) +void toggle_ready_jedec_common(chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; @@ -41,14 +41,31 @@ tmp1 = chip_readb(dst) & 0x40;
while (i++ < 0xFFFFFFF) { + if (delay) + programmer_delay(delay); tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } tmp1 = tmp2; } + if (i > 0x10000) + printf_debug("%s: excessive toggle, i=0x%x\n", __func__, i); }
+void toggle_ready_jedec(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 0); +} + +/* Some chips require a minimum delay between toggle bit reads. + * The Winbond W39V040C wants 50 ms between reads on sector erase toggle. + */ +void toggle_ready_jedec_slow(chipaddr dst) +{ + toggle_ready_jedec_common(dst, 50 * 1000); +} + void data_polling_jedec(chipaddr dst, uint8_t data) { unsigned int i = 0; @@ -62,6 +79,8 @@ break; } } + if (i > 0x10000) + printf_debug("%s: excessive data poll, i=0x%x\n", __func__, i); }
void start_program_jedec(chipaddr bios)