Thanks for your help! Answers inline below.
Ricardo Menzer ricardomenzer@gmail.com (32)8865-8805
On Wed, Aug 13, 2014 at 8:16 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Hi Ricardo,
your log is weird in a way I've never seen before. Details below.
Am 13.08.2014 21:24 schrieb Ricardo Menzer:
I have also found that if I probe the chip three times, it will work
As you can see, the chip continuously outputs 0xbf 0x25 0x41 in an endless loop. Normally, the SST SST25VF016B chip should always return the same ID response to probe_spi_rdid_generic: id1 0xbf, id2 0x2541. However, your chip seems to be cycling through shifted variants of that response. This indicates the chip never leaves ID (read JEDEC ID with command 0x9f) mode, probably because the CE# (chip enable) line is stuck on low. I've never seen that happen before, and it's certainly really weird. Do you have a multimeter to confirm that the CE# pin of the flash chip is indeed continuously at 0V?
The line is not stuck at a specific level. I got a logic analyzer and I can see the level changing from 0 to 1 and vice-versa.
The Intel Tunnel Creek chipset may be at fault, or some other weird component is screwing things up.
Two things I'd like you to try:
- Compile latest flashrom from source, reboot and then write a log file
with the new flashrom using -o logfile.txt . It needs to be the first run after the reboot or we'll get mostly random results.
I'll do that. It's not a scientific experiment, but I have the feeling that, indeed, reading/writing chips work better right after a reboot, instead of after using the system for a while.
- Put an oscilloscope on the CE# line and check if it ever goes to high
(3.3V) again after a flashrom run.
Used a Saleae Logic Analyzer. All four lines are changing levels. I have two problems now: First, when I attach the logic analyzer to the chip, and run flashrom in verify mode, it show differences between the flash and its image on disk. Obviously, the analyzer is interfering in the SPI lines sufficiently to cause read errors. When I remove the analyzer, the verification process finishes fine, even with the probes/wires connected. (implicit question: is there a parameter to set SPI frequency for the internal programmer?)
Second, all read/write operations I made today worked! I was hoping to see what's going wrong on the bus with the logic analyzer. As soon it starts to fail again I'll try to do that.
Regards, Carl-Daniel