Misha, could you please test this patch with the satasii programmer on your CurtisWright Raptor and ack it if it works? A verbose log from a successful write would be appreciated. The patch applies on top of an otherwise unpatched tree with latest flashrom from svn.
Convert all PCI-based external programmers to use special little-endian accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well).
Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code.
To test on x86, compile flashrom normally. To test on non-x86, please run
make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-pci_endian/flash.h =================================================================== --- flashrom-pci_endian/flash.h (Revision 1013) +++ flashrom-pci_endian/flash.h (Arbeitskopie) @@ -403,6 +403,8 @@ uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif + +/* hwaccess.c */ void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -415,6 +417,12 @@ uint8_t mmio_le_readb(void *addr); uint16_t mmio_le_readw(void *addr); uint32_t mmio_le_readl(void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl
/* programmer.c */ int noop_shutdown(void); Index: flashrom-pci_endian/drkaiser.c =================================================================== --- flashrom-pci_endian/drkaiser.c (Revision 1013) +++ flashrom-pci_endian/drkaiser.c (Arbeitskopie) @@ -70,10 +70,10 @@
void drkaiser_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, drkaiser_bar + addr); + pci_mmio_writeb(val, drkaiser_bar + addr); }
uint8_t drkaiser_chip_readb(const chipaddr addr) { - return mmio_readb(drkaiser_bar + addr); + return pci_mmio_readb(drkaiser_bar + addr); } Index: flashrom-pci_endian/gfxnvidia.c =================================================================== --- flashrom-pci_endian/gfxnvidia.c (Revision 1013) +++ flashrom-pci_endian/gfxnvidia.c (Arbeitskopie) @@ -95,10 +95,10 @@
void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, nvidia_bar + addr); + pci_mmio_writeb(val, nvidia_bar + addr); }
uint8_t gfxnvidia_chip_readb(const chipaddr addr) { - return mmio_readb(nvidia_bar + addr); + return pci_mmio_readb(nvidia_bar + addr); } Index: flashrom-pci_endian/satasii.c =================================================================== --- flashrom-pci_endian/satasii.c (Revision 1013) +++ flashrom-pci_endian/satasii.c (Arbeitskopie) @@ -62,7 +62,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
/* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n");
buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -82,32 +82,32 @@ { uint32_t ctrl_reg, data_reg;
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
- data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar);
- while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; }
uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg;
- while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;
/* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
- mmio_writel(ctrl_reg, sii_bar); + pci_mmio_writel(ctrl_reg, sii_bar);
- while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ;
- return (mmio_readl(sii_bar + 4)) & 0xff; + return (pci_mmio_readl(sii_bar + 4)) & 0xff; }