On 06.10.2009 13:52, Uwe Hermann wrote:
I'm thankful for better suggestions to track which chipsets and especially boards can decode how much.
Could you please change chipset_max_rom_decode_kb to a struct with one value per bustype? All Intel chipsets with SPI support have two independent limits: One for FWH and one for SPI. SB600 has three limits: FWH, LPC and SPI (yes, it can speak FWH).
For boards we need to autodetect them (not possible for all boards unfortunately). For those with board-enables we could reuse that table and enhance/add board-enables, whether that's a good idea is another issue.
Board matching is already done via board enables. While the size limit is not directly a board enable, we also use board enables to add buses (e.g. behind a IT8716F SPI), so it would only be logical to use board enables for board sizing constraints.
How should we handle double limits (board+chipset)? Pick the minimum? Logical AND?
IMHO the chipset enable should set the limits for every supported bus, and the board enable should override settings where/how appropriate. That also means there's only one variable per bus. If you change your patch that way, I think I'll ack it right away.
For boards that cannot be autodetected we should at least have a table of the max. supported ROM chip size, which can be printed in "flashrom -L" and in the wiki.
Such boards will appear as "needs special board enable", though. Oh well. Maybe it is time to introduce a "reason" bitfield in the board enable table which says why the board is listed there.
Regards, Carl-Daniel