[flashrom] SPI status register writes

[Carl-Daniel Hailfinger]

Quite a few SPI flash chips need a few milliseconds to write the status
register (AT25 series etc.), but we do not take care of this at all. The
same flash chips ignore any commands sent while the status register
write cycle is in progress. Given that we execute WRSR once per write, I
think it is pretty OK to have a 100 ms programmer delay after WRSR. An
alternative would be to watch the status register contents, but that may
or may not work, the datasheets are completely unclear about that case.
If we're lucky, this will even solve a few write/erase issues we were
seeing.

What do you think?

Regards,
Carl-Daniel