Re: [flashrom] [PATCH] SB600 SPI off-by-one read count workaround

[Carl-Daniel Hailfinger]

On 23.07.2009 03:30, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
> > This is a workaround for a bug in SB600 and SB700. If we only send an
> > opcode and no additional data/address, the SPI controller will read one
> > byte too few from the chip. Basically, the last byte of the chip
> > response is discarded and will not end up in the FIFO. It is unclear if
> > the CS# line is set high too early as well.
> > That hardware bug is undocumented as of now, but I'm working with AMD to
> > add a detailed description of it to the errata.
> >
> > Add loads of additional debugging to SB600/SB700 init.
> >
> > Add explanatory comments for unintuitive code flow.
> >
> > Thanks go to Uwe for testing quite a few iterations of the patch.
> >
> > Kill the SB600 flash chip status register special case, which was a
> > somewhat misguided workaround for that hardware erratum.
> >
> > Note for future added features in the SB600 SPI driver: It may be
> > possible to read up to 15 bytes of command response with overlapping
> > reads due to the ring buffer design of the FIFO if the command can be
> > repeated without ill effects. Same for skipping up to 7 bytes between
> > command and response.
> >
> > Signed-off-by: Carl-Daniel Hailfinger
>
> Interesting.. good work!

Thanks! Took me a few hours to figure out the trick. By the way, this
also fixes all SPI ID strangeness we saw on SB600 in the past.
> Acked-by: Stefan Reinauer

Thanks, r661.

Regards,
Carl-Daniel