[flashrom] [PATCH 3/4] add spi_block_erase_62

[Stefan Tauner]

this is used by the AT25F series (only?), but is generic enough to reside in spi25.c.
the only currently supported chip is the AT25F512B. other members of that series
need some additional infrastructure code, hence we add the erase function to the
AT25F512B only.

Signed-off-by: Stefan Tauner 
---
 chipdrivers.h |    1 +
 flashchips.c  |    3 +++
 spi.h         |    5 +++++
 spi25.c       |   47 +++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/chipdrivers.h b/chipdrivers.h
index ccbd86b..7918308 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -38,6 +38,7 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int
 int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen);
+int spi_block_erase_62(struct flashchip *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen);
 int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len);
 int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
diff --git a/flashchips.c b/flashchips.c
index 0020f6f..e021cbc 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -1679,6 +1679,9 @@ const struct flashchip flashchips[] = {
    		}, {
    			.eraseblocks = { {64 * 1024, 1} },
    			.block_erase = spi_block_erase_c7,
+			}, {
+				.eraseblocks = { {64 * 1024, 1} },
+				.block_erase = spi_block_erase_62,
    		}
    	},
    	.printlock	= spi_prettyprint_status_register_at25f512b,
diff --git a/spi.h b/spi.h
index b908603..adb9109 100644
--- a/spi.h
+++ b/spi.h
@@ -61,6 +61,11 @@
 #define JEDEC_CE_60_OUTSIZE	0x01
 #define JEDEC_CE_60_INSIZE	0x00

+/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
+#define JEDEC_CE_62		0x62
+#define JEDEC_CE_62_OUTSIZE	0x01
+#define JEDEC_CE_62_INSIZE	0x00
+
 /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
 #define JEDEC_CE_C7		0xc7
 #define JEDEC_CE_C7_OUTSIZE	0x01
diff --git a/spi25.c b/spi25.c
index 8db9539..a21e75b 100644
--- a/spi25.c
+++ b/spi25.c
@@ -488,6 +488,43 @@ int spi_chip_erase_60(struct flashchip *flash)
    return 0;
 }

+int spi_chip_erase_62(struct flashchip *flash)
+{
+	int result;
+	struct spi_command cmds[] = {
+	{
+		.writecnt	= JEDEC_WREN_OUTSIZE,
+		.writearr	= (const unsigned char[]){ JEDEC_WREN },
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= JEDEC_CE_62_OUTSIZE,
+		.writearr	= (const unsigned char[]){ JEDEC_CE_62 },
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= 0,
+		.writearr	= NULL,
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}};
+	
+	result = spi_send_multicommand(cmds);
+	if (result) {
+		msg_cerr("%s failed during command execution\n",
+			__func__);
+		return result;
+	}
+	/* Wait until the Write-In-Progress bit is cleared.
+	 * This usually takes 2-5 s, so wait in 100 ms steps.
+	 */
+	/* FIXME: We assume spi_read_status_register will never fail. */
+	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(100 * 1000);
+	/* FIXME: Check the status register for errors. */
+	return 0;
+}
+
 int spi_chip_erase_c7(struct flashchip *flash)
 {
    int result;
@@ -707,6 +744,16 @@ int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int
    return spi_chip_erase_60(flash);
 }

+int spi_block_erase_62(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+	if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
+		msg_cerr("%s called with incorrect arguments\n",
+			__func__);
+		return -1;
+	}
+	return spi_chip_erase_62(flash);
+}
+
 int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
 {
    if ((addr != 0) || (blocklen != flash->total_size * 1024)) {