Hello!
2010/9/15 Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net:
--- a/chipset_enable.c +++ b/chipset_enable.c @@ -802,6 +802,23 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) return 0; }
+static int enable_flash_osb4(struct pci_dev *dev, const char *name) +{
- uint8_t tmp;
- buses_supported = CHIP_BUSTYPE_PARALLEL;
- tmp = INB(0xc06);
- tmp |= 0x1;
- OUTB(tmp, 0xc06);
- tmp = INB(0xc6f);
- tmp |= 0x40;
- OUTB(tmp, 0xc6f);
- return 0;
+}
Funny. The 0xc6f access looks very similar to parts of the SB400 chipset enable. (Side note: we should ask AMD if the SB400 chipset enable is correct.)
Peter, could you please attach /proc/ioports and check if dmesg mentions 0xc06 or 0xc6f or anything close to that?
Attached /proc/ioports and dmesg contents.