Hi Roger,
thanks for your report.
Auf 12.01.2011 07:39, Roger schrieb:
localhost2 bios # flashrom -w /home/roger/src/coreboot-tyan_s1832dl/coreboot/build/coreboot.rom flashrom v0.9.3-r1205 on Linux 2.6.37-gentoo (i686), built with libpci 3.1.4, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. This chipset supports the following protocols: Parallel. Found chip "SST SST39SF040" (512 KB, Parallel) at physical address 0xfff80000. Note: If the following flash access fails, try -m <vendor>:<mainboard>. Writing flash chip... Erasing flash chip... SUCCESS.
Erase verification apparently worked.
Programming page: DONE!ss: 0x0007f000 COMPLETE.
Programming didn't return any immediate problems either.
Verifying flash... VERIFY FAILED at 0x0003fc9e! Expected=0xff, Read=0x4f, failed byte count from 0x00000000-0x0007ffff: 0x231f7
Now it explodes. This is very strange.
DIGI-KEY Part No. SST39SF040-70-4C-PHE IC FLASH MPF 4MBIT (512KBYTES) 70NS 32DIP
That should have worked. Can you try to update to the very latest flashrom from svn and write the old image back? I hope that survives the verify. Please also send a log of the write attempt with latest flashrom from svn. Maybe it has some useful info.
This is flashing using a Tyan S1832DL board 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) ... 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02)
(... am I getting this right, flashrom uses the ISA bridge to write to flash part?)
Correct. On that board, the flash chip is attached to the ISA bridge. Later boards have a LPC bridge to which the flash chip is attached.
Regards, Carl-Daniel