Am Mittwoch, den 16.12.2009, 02:26 +0100 schrieb Carl-Daniel Hailfinger:
Today's systems are quite capable of running 2^32 reads in short time. Some chips may be slow enough to fall off the loop here. Other chips may be slow enough to cause delays of more than 2^20 read cycles.
If the JEDEC Toggle Bit algorithm needs more than 2^20 loops, it is a good sign we should have used delays between toggle bit reads.
The Winbond W39V040C requires a 50 ms delay between toggle bit reads during erase according to the datasheet. Turns out a 2 ms delay is sufficient. Use a safety factor of 4 and default all erase operations to 8 ms delay between toggle reads. This is short enough not to have a substantial negative impact on erase times, and should improve reliability.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
While your patch looks OK, I somehow dislike your comment. The main problem addressed is not falling out of the loop, but the Winbond chip being slow on toggling, so that you read two times the same value of the toggle bit while the operation is still in progress, unless you wait for some ms between reads. Looks like the toggling of the toggle bit is implemented in "software" in that chip instead of being implemented in hardware driven by the read instructions.
2^20 iterations should be around 1 second on ISA, and i doubt that LPC or FWH are much faster. For LPC, 15 LPC clocks are needed for read/write. As an example, I checked the maximum LPC clock of the W39V040C which is 33MHz. So 2^20 iterations still are 0.5 seconds.
Still, as the code is OK: Acked-By: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Regards, Michael Karcher