Hello,
TLDR We discovered a bug in erase/write, which reproduces when layout region is not aligned with any of eraseblocks and layout end boundary needs to be extended. Bugtracker https://ticket.coreboot.org/issues/494 Patch https://review.coreboot.org/c/flashrom/+/78984
More details below.
The exact case when the bug can be reproduced is the following.
Logical layout has at least one region which is not aligned with the size of any eraseblocks. For example, if a chip has eraseblocks of 4K, 32K, 64K and layout has a region with size 5K -> this region cannot be aligned with any of eraseblocks. To perform an operation, in this example, the region boundary needs to be extended by 3K, so that it becomes 5+3=8K in total and can be aligned with the 4K block. Another condition for the bug to reproduce, is to have different bytes in the written image vs original image *for that unaligned region*. If bytes are the same, the bug won't be noticeable.
There are more details in the bugtracker https://ticket.coreboot.org/issues/494 also there is a patch with potential fix https://review.coreboot.org/c/flashrom/+/78984. Note the patch needs to go through reviews and more testing.
If you are building flashrom from head and want to erase/write the chip, you can check whether the bug affects you *before writing*. If it does affect you, then the options are: 1) wait for the patch to be submitted 2) use latest release 1.3 (the code in question is newer than that) 3) apply the patch locally, and rebuild. *Only do it if you have a way to recover*, and please respond to the thread whether it works or not. thanks!
If you have never heard of layouts and never set any layouts, then flashrom creates a default layout which is one region covering the whole chip. This case is not affected by the bug.
Any help with reviewing and testing the patch is very much appreciated! Thank you. Also feel free to ask for more details.