On 24.03.2010 00:22, RayeR wrote:
Carl-Daniel Hailfinger wrote:
Ah yes. That's a limitation of the DOS port of flashrom. Usually the SB600 SPI base address is near the top of the address space (4 GB). On your board it is below 1 MB, and AFAIK Rudolf said that we can't map any region below 1 MB as uncached due to CWSDPMI/DJGPP limitations.
Acessing memory below 1MB is possible via dosmemput/dosmemget which use _dos_ds selector.
OK. Can you or Rudolf implement this? The current code simply copies all memory from 0-1 MB to a high area for easier access because we didn't know that some systems out there have MMIO in that region. That copy is still OK for any cached readonly accesses, but for uncached read/write accesses (MMIO) below 1 MB we need dosmemget/dosmemput.
About caching - I think it's not a job for DPMI server to set cache mode. It's task for BIOS to configure CPU MTRR. I know that is possible to change cache mode of A0000 window for VGA. CPU has some number of MTRRs that can be set to specific base address, size and cache mode. It's done via rdmsr/wrmsr instruction and it may be CPU vendor specific. I know only the intel way...
I have worked a lot with MTRRs and know them pretty well. If needed, I can code up something that ensures correct cache mode, but for now we can try to use what the BIOS gives us. If we're lucky, the BIOS performs a correct MTRR setup and things will start working without having to write special flashrom MTRR code.