Auf 05.03.2011 00:30, Michael Karcher schrieb:
Am Freitag, den 04.03.2011, 22:45 +0100 schrieb Michał Janke:
Well, it IS strange - sometimes the chip gets flashed ok in spite of an error during erease and sometimes there is either no such error or the error causes writing to fail. I attach a console script log showing how it looks like (a series ofnon-verbose flashing attempts) and one verbose log.
[This is a HP board with i810 chipset and an SST49LF004A flash chip that randomly ignores erase instructions, both sector or block erase]
As we found out in a private IRC discussion, the observed random failure of erase commands (command seems to get ignored by the chip) disappear on either of
- using current flashrom with interleaved erase/write
- removing the programmer_delay(10) calls from
erase_sector_jedec_common
But they are still present on current flashrom in erase-only mode (flashrom -E), so it's no general change in flashrom behaviour. Also switching to single user mode did not help.
If I understand it correctly, the delays in erase_sector_jedec_common are mostly for chips that need commands to be written so slowly - these chips should require a probe delay, too. So would there be a problem to put these delays into a "probe timing not zero" test?
AFAIK the erase delay is used on chips which need the probe delay anyway, so your test would indeed cover those problems. However, there is one exception: Winbond W39V040C. See the mail at http://www.flashrom.org/pipermail/flashrom/2009-December/001330.html We could add a new feature bit for this...
I strongly support your approach, but we should handle W39V040C as corner case.
Regards, Carl-Daniel