AMD SB700 and later have an integrated microcontroller (IMC) which runs from shared flash. The IMC will happily issue reads while we write, issue writes while we read, and generally cause lots of havoc due to the concurrent accesses it performs while flashrom is running. A failing or corrupted read can be detected since r1145, and the worst case is that the read aborts and the user has to retry. A failing write is much more serious. It can be detected since r1145, but if the SPI interface locks up, we can't continue writing nor can we read the current chip contents.
If the IMC is inactive, there is no reason to worry. If the IMC is active, flashrom will refuse to erase/write the chip with this patch.
The correct fix would be to stop the IMC during flashing, but apparently the relevant registers are undocumented, so we take the safe route for now until someone from AMD can give us more info.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-sb700_imc_refuse_write/sb600spi.c =================================================================== --- flashrom-sb700_imc_refuse_write/sb600spi.c (Revision 1171) +++ flashrom-sb700_imc_refuse_write/sb600spi.c (Arbeitskopie) @@ -294,6 +294,24 @@ return 0; }
+ reg = pci_read_byte(dev, 0x40); + msg_pdbg("SB700 IMC is %sactive.\n", (tmp & (1 << 7)) ? "" : "not "); + if (tmp & (1 << 7)) { + /* If we touch any region used by the IMC, the IMC and the SPI + * interface will lock up, and the only way to recover is a + * hard reset, but that is a bad choice for a half-erased or + * half-written flash chip. + * There appears to be an undocumented register which can freeze + * or disable the IMC, but for now we want to play it safe. + */ + msg_perr("The SB700 IMC is active and may interfere with SPI " + "commands. Disabling write.\n"); + /* FIXME: Should we only disable SPI writes, or will the lockup + * affect LPC/FWH chips as well? + */ + programmer_may_write = 0; + } + /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer();